CN104952831A - 具有穿通电极的半导体器件及其制造方法和半导体封装体 - Google Patents

具有穿通电极的半导体器件及其制造方法和半导体封装体 Download PDF

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CN104952831A
CN104952831A CN201410459197.5A CN201410459197A CN104952831A CN 104952831 A CN104952831 A CN 104952831A CN 201410459197 A CN201410459197 A CN 201410459197A CN 104952831 A CN104952831 A CN 104952831A
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semiconductor layer
electrode
rear side
pattern
semiconductor
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CN104952831B (zh
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朴完春
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

一种半导体器件，包括：半导体层，其具有第一表面和第二表面；穿通电极，其穿通半导体层，并且具有在半导体层的第二表面之上突出的突出部分；前侧凸块，其设置在半导体层的第一表面上，且与穿通电极电耦接；钝化图案，其包括第一绝缘图案和第二绝缘图案，所述第一绝缘图案包围穿通电极的突出部分的侧壁并且延伸至半导体层的第二表面上，所述第二绝缘图案覆盖第一绝缘图案并且具有相对于第一绝缘图案的刻蚀选择性；以及后侧凸块，其覆盖穿通电极的突出部分的端面并且延伸至钝化图案上。

Description

具有穿通电极的半导体器件及其制造方法和半导体封装体
相关申请的交叉引用
本申请要求2014年3月28日提交的申请号为10-2014-0036525的韩国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开的实施例涉及具有穿通电极的半导体器件、其制造方法以及包括其的半导体封装体。
背景技术
随着更小、高性能的电子产品的发展，越来越需要具有大存储容量的超小型半导体器件。可以将多个半导体芯片组装在单个半导体封装体中以增加半导体器件的数据存储容量。即，利用多芯片封装技术可以容易地增加半导体器件的数据存储容量。
然而，虽然多芯片封装技术可以增加半导体器件的数据存储容量，但随着半导体芯片的数量增加，难以在多芯片封装体中的多个半导体芯片之间获得用于电连接的足够空间。近来，已经提出了穿通硅通孔(TSV)来解决多芯片封装技术的限制。可以在晶片级将TSV形成为穿通多个芯片，并且可以通过TSV将层叠在封装体中的芯片彼此电连接和物理连接。因此，如果在封装体中使用TSV，则可以改善封装体的性能和存储容量。
发明内容
各种实施例针对一种具有穿通电极的半导体器件、其制造方法以及包括其的半导体封装体。
根据一些实施例，一种半导体器件包括：半导体层，其具有第一表面和第二表面；穿通电极，其穿通半导体层以在半导体层的第二表面之上具有突出预定高度的突出部分；前侧凸块，其设置在半导体层的第一表面上且与穿通电极电耦接；钝化图案，其包括第一绝缘图案和第二绝缘图案，所述第一绝缘图案包围穿通电极的突出部分的侧壁并且延伸至半导体层的第二表面上，所述第二绝缘图案覆盖第一绝缘图案并且具有相对于第一绝缘图案的刻蚀选择性；以及后侧凸块，其覆盖穿通电极的突出部分的端面并且延伸至钝化图案上。
根据另外的实施例，一种半导体器件包括：半导体层，其具有第一表面和第二表面；穿通电极，其穿通半导体层以在半导体层的第二表面之上具有突出预定高度的突出部分；前侧凸块，其设置在半导体层的第一表面上并且与穿通电极电连接；钝化图案，其包围穿通电极的突出部分的侧壁并且延伸至半导体层的第二表面上；以及后侧凸块，其覆盖穿通电极的突出部分的端面并且延伸至钝化图案上。钝化图案在后侧凸块之下的位置处具有第一厚度，以及在半导体层的第二表面上的与后侧凸块不重叠的位置处具有第二厚度。
根据另外的实施例，一种制造半导体器件的方法包括：提供包括穿通电极的晶片和形成在晶片的第一表面上并且与穿通电极电连接的前侧凸块；将晶片的第二表面凹陷以形成穿通电极的从晶片的凹陷的第二表面突出预定高度的突出部分；形成包围穿通电极的突出部分的侧壁并且覆盖晶片的凹陷的第二表面的钝化图案；以及形成覆盖穿通电极的突出部分并且延伸至钝化图案上的后侧凸块。钝化图案被形成为包括具有不同刻蚀速率的至少两种绝缘图案。
根据另外的实施例，一种半导体封装体包括：封装体衬底、安装在封装体衬底上的第一半导体芯片、以及层叠在第一半导体芯片的与封装体衬底相对的表面上的至少一个另外的半导体芯片。第一半导体芯片和所述至少一个另外的半导体芯片中的每个包括：半导体层；穿通电极，其穿通半导体层以具有从半导体层的后侧表面突出的突出部分；前侧凸块，其设置在半导体层的前侧表面上并且与穿通电极电连接；后侧凸块，其设置在半导体层的后侧表面之上并且与穿通电极的突出部分电连接；以及钝化图案，其包围穿通电极的突出部分的侧壁并且延伸至半导体层的后侧表面上。
附图说明
根据附图和所附详细描述，本公开的实施例将变得更加明显，在附图中：
图1是说明根据一个实施例的半导体器件的截面图；
图2是说明根据另一个实施例的半导体器件的截面图；
图3至图12是说明根据一个实施例的制造半导体器件的方法的截面图；以及
图13是说明根据一些实施例的包括半导体器件的半导体封装体的截面图；
图14是说明根据一个实施例的包括封装体的电子系统的框图；
图15是说明根据一个实施例的包括封装体的另一个电子系统的框图。
具体实施方式
参见图1，半导体器件包括半导体层10、穿通半导体层10的穿通电极35、设置在半导体层10的第一表面10a上并且与穿通电极35电耦接的前侧凸块29、以及设置在半导体层10的与前侧凸块29相对的第二表面10b上并且与穿通电极35电耦接的后侧凸块59。
第一表面10a可以对应于半导体层10的与有源区相邻的前侧表面，第二表面10b可以对应于半导体层10的与第一表面10a相对的后侧表面。晶体管的源极/漏极区14设置在与第一表面10a相邻的有源区中，晶体管的栅电极12设置在第一表面10a上。半导体层10的第一表面10a和晶体管的栅电极12被层间绝缘层16覆盖。电路图案18，诸如用于将电信号施加至晶体管的位线，可以设置在层间绝缘层16的与半导体层10相对的表面上。
穿通电极35可以包括穿通金属电极34，所述穿通金属电极34填充从第一表面10a向第二表面10b穿通半导体层10的通孔30。穿通金属电极34可以包括例如铜材料。穿通电极35还可以包括设置在穿通金属电极34和半导体层10之间的并且包围穿通金属电极34的侧壁的阻挡层32。阻挡层32可以抑制或防止穿通金属电极34中的金属原子扩散至半导体层10中。
穿通电极35可以包括与半导体层10的第一表面10a相邻的第一端面35a和与半导体层10的第二表面10b相邻的第二端面35b。穿通电极35的第一端面35a可以与电路图案18电连接。电路图案18可以与电连接至外部电路衬底(未示出)的接合焊盘20电连接，并且接合焊盘20可以通过覆盖电路图案18的绝缘层22的开口而暴露。
前侧凸块29附接至接合焊盘20的暴露部分。前侧凸块29可以包括填充开口24的金属柱体26和设置在金属柱体26的与接合焊盘20相对的表面上的焊接凸块28。金属柱体26可以包括铜材料。
穿通电极35的第二端面35b可以从半导体层10的第二表面10b突出预定高度。即，穿通电极35可以具有与半导体层10的第二表面10b相邻的突出部分。穿通电极35的第二端面35b可以接触后侧凸块59。后侧凸块59可以包括顺序地层叠在穿通电极35的第二端面35b上的晶种金属图案50、第一金属层53和第二金属层55。晶种金属图案50可以包括铜材料，第一金属层53可以包括铜材料。第二金属层55可以包括镍材料或金材料。
钝化图案45可以设置在后侧凸块59和半导体层10之间。钝化图案45可以包围穿通电极35的从半导体层10的第二表面10b突出的突出部分的侧壁，并且可以覆盖后侧凸块59的底表面。即，钝化图案45可以具有与从穿通电极35的突出部分至后侧凸块59的侧壁的距离相对应的第一宽度57。在一些实施例中，钝化图案45可以横向地延伸以覆盖半导体层10的第二表面10b的整个部分。
钝化图案45可以包括至少两个不同的材料层。例如，钝化图案45可以包括第一绝缘图案39和具有相对于第一绝缘图案39的刻蚀选择性的第二绝缘图案40，并且第一绝缘图案39和第二绝缘图案40顺序地层叠在半导体层10的第二表面10b上。第一绝缘图案39可以包括氮化物层，第二绝缘图案40可以包括具有相对于氮化物层的刻蚀选择性的材料。例如，如果第一绝缘图案39包括氮化物层，则第二绝缘图案40可以包括氧化物层。
尽管图1说明了钝化图案45包括两层第一绝缘图案39和第二绝缘图案40的实例，但是实施例不局限于此。例如，钝化图案45可以具有多层结构，所述多层结构是以交替的方式重复地层叠至少两个不同的材料层来形成的。后侧凸块59可以具有比穿通电极35的突出部分的平面区域更大的平面区域。即，后侧凸块59可以覆盖穿通电极35的第二端面35b，并且可以在钝化图案45上横向地延伸第一宽度57，有效地增加了后侧凸块超过穿通电极35的宽度的平面区域。
在一些实施例中，钝化图案45的设置在后侧凸块59之下的部分可以具有第一厚度a1，而钝化图案45的位于半导体层10的第二表面10b上的不与后侧凸块59重叠的位置处的部分具有小于第一厚度a1的第二厚度c1。钝化图案45的具有第二厚度c1的部分的顶表面可以比钝化图案45的具有第一厚度a1的部分的顶表面低预定深度b1。因而，后侧凸块59的高度H1相对于钝化图案45具有一致厚度a1的器件增加了预定深度b1。结果，当包括穿通电极35以及凸块29和59的多个半导体层10被垂直地层叠时，由于后侧凸块59具有相对地增加了预定深度b1的高度H1，所以层叠的半导体层10之间的电连接可以更成功。
参见图2，根据另一个实施例的半导体器件包括半导体层100、穿通半导体层100的穿通电极125、设置在半导体层100的第一表面100a上且与穿通电极125电连接的前侧凸块129、以及设置在半导体层100的与前侧凸块129相对的第二表面100b上且与穿通电极125电连接的后侧凸块160。第一表面100a可以对应于半导体层100的与有源区相邻的前侧表面，而第二表面100b可以对应于半导体层100的与第一表面100a相对的后侧表面。晶体管的源极/漏极区104可以设置在与第一表面100a相邻的有源区中，晶体管的栅电极102可以设置在第一表面100a上。半导体层100的第一表面100a和晶体管的栅电极102可以被层间绝缘层106覆盖，电路图案108可以设置在层间绝缘层106的与半导体层100相对的表面上。
穿通电极125可以包括填充穿通半导体层100的通孔120的穿通金属电极124。穿通金属电极124可以包括例如铜材料。穿通电极125还可以包括设置在穿通金属电极124和半导体层100之间以包围穿通金属电极124的侧壁的阻挡层122。阻挡层122可以抑制或防止穿通金属电极124中的金属原子扩散至半导体层100中。穿通电极125可以包括与半导体层100的第一表面100a相邻的第一端面125a和与半导体层100的第二表面100b相邻的第二端面125b。穿通电极125的第一端面125a可以与电路图案108电连接。电路图案108可以与接合焊盘110电连接，并且接合焊盘110可以通过覆盖电路图案108的绝缘层112的开口124而暴露。
前侧凸块129可以附接至暴露出的接合焊盘110。前侧凸块129可以包括填充开口124的金属柱体126和设置在金属柱体126的与接合焊盘120相对的表面上的焊接凸块128。
穿通电极125的第二端面125b可以从半导体层100的第二表面100b突出预定高度。即，穿通电极125可以具有与半导体层100的第二表面100b相邻的突出部分。穿通电极125的突出部分的侧壁和半导体层100的第二表面100b可以被钝化图案133覆盖。穿通电极125的第二端面125b可以接触后侧凸块160。后侧凸块160可以从穿通电极125的突出部分的侧壁横向地延伸第一宽度155以覆盖钝化图案133的一部分。钝化图案133可以具有单材料层。例如，钝化图案133可以由单个氮化物层形成。钝化图案133可以覆盖穿通电极125的突出部分的侧壁并且防止穿通电极125的突出部分受损。
钝化图案133的位于后侧凸块160之下的位置处的部分可以具有第一厚度a2，而位于半导体层100的第二表面100b上的不与后侧凸块160重叠的位置处的部分可以具有小于第一厚度a2的第二厚度c2。钝化图案133的具有第二厚度c2的部分的顶表面可以比钝化图案133的具有第一厚度a2的部分的顶表面低预定深度b2。因而，后侧凸块160的高度H2可以从钝化图案133的具有第二厚度c2的顶表面增加预定深度b2。由于具有高度H2的后侧凸块160增加了预定深度b2，所以当包括穿通电极125以及凸块129和160的多个半导体层100被垂直层叠时，因为后侧凸块160具有相对增加了预定深度b2的高度H2，所以层叠的半导体层100之间的电连接可以更成功。
后侧凸块160可以包括顺序地层叠在穿通电极125的第二端面125b上的晶种金属图案140、第一金属层145和第二金属层150。后侧凸块160可以具有比穿通电极125的突出部分的平面区域更大的平面区域。即，后侧凸块160可以覆盖穿通电极125的第二端面125b，并且可以在钝化图案133上横向地延伸第一宽度155以增加其平面区域。
现在将参照图3至图12来描述根据一个实施例的制造半导体器件的方法。参见图3，可以提供具有穿通电极225和与穿通电极225电连接的前侧凸块219的晶片200。晶片200可以是例如具有前侧表面200a和位于相对侧上的后侧表面200b的硅晶片。晶片200可以是在制造半导体存储器件、半导体逻辑器件、照相设备或显示单元时使用的衬底。前侧表面200a可以与形成有有源元件或无源元件的有源区相邻，后侧表面200b可以是晶片200的位于与前侧表面200a相对侧上的表面。
晶体管可以被形成在晶片200上或晶片200中，并且与前侧表面200a相邻。每个晶体管可以包括栅电极202和源极/漏极区204。层间绝缘层206可以被形成在前侧表面200a上以覆盖晶体管，诸如位线的电路图案208可以被形成在层间绝缘层206中或层间绝缘层206上。可以经由电路图案208将电气信号施加至栅电极202和源极/漏极区204。
穿通电极225(其可以是穿通硅通孔(TSV))可以被形成在晶片200中。可以通过图案化晶片200以形成具有从前侧表面200a向后侧表面200b的预定深度的沟槽孔220、通过在沟槽孔220的内表面上形成阻挡层222、通过形成填充由阻挡层222包围的沟槽孔220的穿通金属层、以及通过将穿通金属层和阻挡层222平坦化以在沟槽孔220中形成单独的穿通金属电极224，来形成穿通电极225。穿通电极225可以被形成为彼此分开预定距离。穿通金属电极224可以被形成为包括铜材料、银材料或锡材料。阻挡层222可以被形成为防止穿通金属电极224中的金属原子或金属离子扩散至晶片200中。每个穿通电极225可以被形成为具有与晶片200的前侧表面200a相邻的第一端面225a。电路图案208可以被形成为连接至穿通电极225的第一端面225a。
接合焊盘210可以被形成在穿通电极225上。接合焊盘210可以被形成为经由电路图案208电连接至穿通电极225。接合焊盘210可以电连接至外部电路衬底(未示出)等。绝缘层212可以被形成在层间绝缘层206上以覆盖接合焊盘210和电路图案208。绝缘层212然后可以被图案化以形成暴露出接合焊盘210的开口214。
上述工艺是在晶片200被定向成使得初始的后侧表面200b被提供作为晶片200的底表面、并且前侧表面200a被提供作为晶片200的顶表面时执行的，如图3的定向所示。如图4中所示，在使用粘附层226将载体衬底227附接至前侧凸块219之后，翻转晶片200，使得晶片200的初始的后侧表面200b被提供作为晶片200的顶表面，并且前侧表面200a被提供作为晶片200的底表面。
前侧凸块219可以被形成在暴露出的接合焊盘210上。每个前侧凸块219可以被形成为包括层叠在接合焊盘210上的金属柱体216和焊接凸块218。金属柱体216可以具有圆柱形状。然而，实施例不局限于此。例如，在一些实施例中，金属柱体216可以被形成为具有多边形的横截面轮廓。如图3中所示，金属柱体216上的焊接凸块218可以在截面图中具有半圆形轮廓。更具体地，焊接凸块218可以具有半球形外表面。
参见图4，载体衬底227可以被附接至形成在晶片200的前侧表面200a上的前侧凸块219。可以利用粘附层226将载体衬底227附接至前侧凸块219。可以将粘附层226形成至足够的厚度以覆盖所有的前侧凸块219。
参见图5，可以对后侧表面(图4的200b)应用刻蚀工艺以暴露出穿通电极225的后侧端部。具体地，可以对后侧表面200b应用研磨工艺以将晶片200的一部分去除预定的厚度，以及可以使用刻蚀工艺来选择性地刻蚀晶片200以暴露出穿通电极225的后侧端部且形成凹陷的后侧表面200c。可以使用干法刻蚀工艺或湿法刻蚀工艺来执行刻蚀工艺。作为刻蚀工艺的结果，穿通电极225的后侧端部可以从晶片200的凹陷的后侧表面200c突出预定高度230。在一些实施例中，可以使用选自研磨工艺、化学机械抛光(CMP)工艺、各向同性蚀刻工艺和各向异性蚀刻工艺中的至少一种来将晶片200的后侧表面200b凹陷。
参见图6，钝化层236可以被形成在晶片200的凹陷的后侧表面200c和穿通电极225的突出部分上。可以将钝化层236形成至足够的厚度以覆盖穿通电极225的突出部分。可以通过在晶片200的凹陷的后侧表面200c和穿通电极225的突出部分上顺序地层叠第一绝缘层233和第二绝缘层235来形成钝化层236。包括第一绝缘层233和第二绝缘层235的钝化层236的厚度可以根据钝化层236的位置而不同。例如，与穿通电极225的突出部分的侧壁相邻的钝化层236可以被形成为具有比穿通电极225的突出部分的高度230更大的第一厚度237a，而远离穿通电极225的突出部分的侧壁的钝化层236可以被形成为具有比第一厚度237a小的第二厚度237b。第二绝缘层235可以由具有相对于第一绝缘层233的刻蚀选择性的材料层形成。例如，如果第一绝缘层233包括氮化物层，则第二绝缘层235可以包括氧化物层。尽管图6示出了钝化层236包括第一绝缘层233和第二绝缘层235的两个不同的层，但是实施例不局限于此。例如，钝化层236可以具有通过以交替的方式重复地层叠至少两种不同材料层来制造的多层结构。可替选地，钝化层236可以是单材料层。
参见图7，可以对钝化层236应用平坦化工艺以形成钝化图案236a。作为平坦化工艺的结果，穿通电极225的与前侧凸块219相对的第二端面225b可以被暴露。钝化图案236a可以被形成为包括第一绝缘图案233a和第二绝缘图案235a。用于形成钝化图案236a的平坦化工艺可以是化学机械抛光(CMP)工艺。在对钝化层236应用平坦化工艺期间，穿通电极225的后侧端部可以被去除，使得穿通电极225的第二端面225b与具有第二厚度237b的钝化图案236a的顶表面共面。因此，穿通电极225的第二端面225b中的每个可以包括穿通金属电极224的表面和阻挡层222的表面。
参见图8，晶种金属层240可以被形成在钝化图案236a上以覆盖穿通电极225的第二端面225b。尽管在附图中未示出，但在形成晶种金属层240之前，可以额外地在钝化图案236a上形成粘附层。可以形成粘附层以改善钝化图案236a和晶种金属层240之间的粘附强度。粘附层可以被形成为包括选自钛(Ti)材料、钨(W)材料和钛钨(TiW)材料中的至少一种。如果在钝化图案236a上形成粘附层，则可以在粘附层上形成晶种金属层240。可以利用化学气相沉积(CVD)工艺或物理气相沉积(PVD)工艺由铜层形成晶种金属层240。
随后，可以在晶种金属层240上形成具有开口250的掩模图案245。开口250可以限定形成后侧凸块的区域。具体地，可以在晶种金属层240的整个表面之上淀积光致抗蚀剂材料。可以利用曝光工艺和显影工艺将光致抗蚀剂材料图案化，以形成具有暴露出晶种金属层240的一部分的开口250的掩模图案245。开口250可以被定位为暴露出穿通电极225。
参见图9，可以在晶种金属层240的由每个开口250暴露出的部分上顺序地形成第一金属层255和第二金属层260。可以利用电镀工艺来形成第一金属层255和第二金属层260。如果利用电镀工艺来形成第一金属层255和第二金属层260，则可以在晶种金属层240的由开口250暴露出的部分上选择性地生长第一金属层255和第二金属层260。第一金属层255可以被形成为包括铜材料，第二金属层260可以被形成为包括镍材料或金材料。
参见图10，可以利用灰化工艺或剥离工艺来去除掩模图案(图9的245)。作为去除掩模图案245的结果，可以暴露出晶种金属层240的被掩模图案245覆盖的部分。
参见图11，可以选择性地刻蚀晶种金属层240的暴露部分以形成保留在第一金属层255之下的晶种金属图案240a。在刻蚀晶种金属层240的暴露部分时，第一金属层255和第二金属层260可以起到刻蚀掩模的作用。因而，可以利用毯式刻蚀工艺(例如，不使用光掩模的干法刻蚀工艺)选择性地刻蚀晶种金属层240的暴露部分。可以执行应用于晶种金属层240的毯式刻蚀工艺以去除晶种金属层240的未被第一金属层255和第二金属层260覆盖的部分。结果，可以形成包括晶种金属图案240a、第一金属层255和第二金属层260的后侧凸块259。可以在第二金属层260上额外地形成粘附金属层(未示出)。粘附金属层可以被形成为包括银材料和锡材料。
在刻蚀晶种金属层240以形成晶种金属图案240a时，可以经过晶种金属层240刻蚀钝化图案236a的第二绝缘图案235a以形成具有预定深度b3的凹陷区。因此，钝化图案236a的位于后侧凸块259之下的部分可以具有第一厚度a3，而钝化图案236a的位于后侧凸块259和晶片200的不重叠区中的部分可以具有比第一厚度a3小预定深度b3的第二厚度c3。因而，后侧凸块259的从钝化图案236a的一部分的顶表面开始的高度H3可以是第二厚度c3和预定深度b3之和。
组成钝化图案236a的第一绝缘图案233a和第二绝缘图案235a可以在某些刻蚀剂或某些刻蚀气体中表现出不同的刻蚀速率。即，第二绝缘图案235a可以被形成为具有相对于第一绝缘图案233a的刻蚀选择性。因而，即使在刻蚀晶种金属层240以形成晶种金属图案240a时第二绝缘图案235a被过度刻蚀，第一绝缘图案233a也可以被最小地刻蚀以保持与其原始厚度大体相同的厚度。例如，如在图12中所示，即使在刻蚀晶种金属层240以形成晶种金属图案240a时对第二绝缘图案235a执行的刻蚀工艺暴露出第一绝缘图案233a，第一绝缘图案233a也可以起到刻蚀停止层的作用以防止底层材料层受损。即，即使在不使用任何光掩模的情况下对晶种金属层240应用毯式刻蚀工艺以形成晶种金属图案240a，第一绝缘图案233a也可以保持在晶片200的凹陷的后侧表面200c上，并且防止晶片200因为在毯式刻蚀工艺中使用的刻蚀源而受损。
此外，穿通电极225的突出部分的侧壁可以被钝化图案236a覆盖。因而，即使毯式刻蚀工艺的刻蚀源可能在用于形成晶种金属图案240a的毯式刻蚀工艺期间沿横向270渗入，但是钝化图案236a的具有第一厚度a3的部分也可以防止穿通电极225的突出部分受损。
同时，当包括穿通电极225以及凸块219和259的多个晶片200被垂直地层叠时，由于后侧凸块259具有在钝化图案236a之上延伸预定深度b3的高度H3，所以晶片200之间的电连接可以更成功。以下将参照图13来描述这个特征的方面。
参见图13，根据一个实施例的半导体封装体可以包括封装体衬底400和设置在封装体衬底400之上的至少两个半导体芯片300。所述至少两个半导体芯片可以包括垂直层叠在封装体衬底400上的第一半导体芯片300-1，第二半导体芯片300-2和第三半导体芯片300-3。与最低芯片相对应的第一半导体芯片300-1可以附接至封装体衬底400的顶表面。尽管在附图中未示出，但多个互连线可以设置在封装体衬底400中或封装体衬底400上。包括焊球的外部连接构件405还可以被设置在封装体衬底400的与第一半导体芯片300-1相对的底表面上。每个半导体芯片300可以是根据本公开的实施例的芯片，诸如图1的芯片。
第一半导体芯片300-1可以包括诸如硅层的半导体层200-1、穿通半导体层200-1的穿通电极225-1、设置在半导体层200-1的前侧表面上且与相应的穿通电极225-1电连接的前侧凸块219-1、以及设置在半导体层200-1的后侧表面上且与相应的穿通电极225-1电连接的后侧凸块259-1。第二半导体芯片300-2可以包括诸如硅层的半导体层200-2、穿通半导体层200-2的穿通电极225-2、设置在半导体层200-2的前侧表面上且与相应的穿通电极225-2电连接的前侧凸块219-2、以及设置在半导体层200-2的后侧表面上且与相应的穿通电极225-2电连接的后侧凸块259-2。类似地，第三半导体芯片300-3可以包括诸如硅层的半导体层200-3、穿通半导体层200-3的穿通电极225-3、设置在半导体层200-3的前侧表面上且与相应的穿通电极225-3电连接的前侧凸块219-3，以及设置在半导体层200-3的后侧表面上且与相应的穿通电极225-3电连接的后侧凸块259-3。
穿通电极225-1的后侧端部可以从半导体层200-1的后侧表面突出。穿通电极225-2的后侧端部也可以从半导体层200-2的后侧表面突出。类似地，穿通电极225-3的后侧端部可以从半导体层200-3的后侧表面突出。
钝化图案236a-1可以设置在后侧凸块259-1和半导体层200-1之间并且包围穿通电极225-1的后侧端部的侧壁，并且可以延伸至半导体层200-1的后侧表面上。钝化图案236a-2可以设置在后侧凸块259-2和半导体层200-2之间以包围穿通电极225-2的后侧端部的侧壁，并且可以延伸至半导体层200-2的后侧表面上。钝化图案236a-3可以设置在后侧凸块259-3和半导体层200-3之间并且包围穿通电极225-3的后侧端部的侧壁，并且可以延伸至半导体层200-3的后侧表面。钝化图案236a-1、236a-2和236a-3中的每个可以包括在某些刻蚀剂或某些刻蚀气体中具有不同刻蚀速率的多个层。
钝化图案236a-1可以在后侧凸块259-1之下的位置处具有第一厚度，以及在半导体层200-1的后侧表面上的不与后侧凸块259-1重叠的位置处具有小于第一厚度的第二厚度。钝化图案236a-2也可以在后侧凸块259-2之下的位置处具有第一厚度，以及在半导体层200-2的后侧表面上的不与后侧凸块259-2重叠的位置处具有小于第一厚度的第二厚度。类似地，钝化图案236a-3也可以在后侧凸块259-3之下的位置处具有第一厚度，以及在半导体层200-3的后侧表面上的不与后侧凸块259-3重叠的位置处具有小于第一厚度的第二厚度。因此，后侧凸块259-1、259-2和259-3的高度H可以突出第一厚度与第二厚度之差。因而，当第一半导体芯片300-1、第二半导体芯片300-2、第三半导体芯片300-3被垂直层叠时，即使前侧凸块219-1、219-2和219-3的高度不一致时，由于后侧凸块259具有相对增加的高度H1，所以层叠的半导体芯片300-1、300-2、300-3之间的电连接也可以被更成功地实现。
上述的封装体可以被应用至各种电子系统。
参见图14，根据一个实施例的封装体可以被应用至电子系统1710。电子系统1710可以包括控制器1711、输入/输出单元1712和存储器1713。控制器1711、输入/输出单元1712和存储器1713可以经由提供传送数据的路径的总线1715而彼此耦接。
例如，控制器1711可以包括至少一个微处理器、至少一个数字信号处理器、至少一个微控制器以及能够执行与这些部件相同的功能的逻辑器件中的至少任何一种。控制器1711和存储器1713中的至少一个可以包括根据本公开的实施例的封装体的至少任何一种。输入/输出单元1712可以包括选自小型键盘(keypad)、键盘、显示设备、触摸屏等之中的至少一种。存储器1713是用于储存数据的设备。存储器1713可以储存数据和/或要由控制器1711执行的命令等。
存储器1713可以包括诸如DRAM的易失性存储器件和/或诸如快闪存储器的非易失性存储器件。例如，快闪存储器可以被安装至诸如移动终端或台式计算机的信息处理系统。快闪存储器可以组成固态磁盘(SSD)。在这种情况下，电子系统1710可以在快闪存储系统中稳定地储存大量的数据。
电子系统1710还可以包括适于向通信网络发送数据和从通信网络接收数据的接口1714。接口1714可以是有线或无线的类型。例如，接口1714可以包括天线或有线或无线收发器。
电子系统1710可以被实现为移动系统、个人计算机、工业计算机或执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板电脑、移动电话、智能电话、无线电话、笔记本电脑、存储卡、数码音乐系统、以及信息传输/接收系统中的任何一种。
在电子系统1710是能够执行无线通信的设备的实施例中，电子系统1710可以用在如下的通信系统中，诸如使用CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强型时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)以及Wibro(无线宽带因特网)中的一种或更多种的系统。
参见图15，根据实施例的封装体可以以存储卡1800的形式提供。例如，存储卡1800可以包括诸如非易失性存储器件的存储器1810和存储器控制器1820。存储器1810和存储器控制器1820可以储存数据或读取储存的数据。
存储器1810可以包括应用本公开的实施例的封装技术的至少一种非易失性存储器件。存储器控制器1820可以控制存储器1810，使得响应于来自主机1830的读取/写入请求来读取储存的数据或储存数据。
已出于说明性的目的公开了本公开的实施例。本领域中的技术人员将理解的是，在不脱离在所附权利要求中公开的范围的情况下，可以作出各种修改、增加和删减。
通过以上实施例可以看出，本申请提供了以下的技术方案。
技术方案1.一种半导体器件，包括：
半导体层，其具有第一表面和第二表面；
穿通电极，其穿通所述半导体层，并且具有在所述半导体层的所述第二表面之上突出预定高度的突出部分；
前侧凸块，其设置在所述半导体层的所述第一表面之上，并且与所述穿通电极电耦接；
钝化图案，其包括第一绝缘图案和第二绝缘图案，所述第一绝缘图案包围所述穿通电极的所述突出部分的侧壁，并且延伸至所述半导体层的所述第二表面上，所述第二绝缘图案覆盖所述第一绝缘图案，并且具有相对于所述第一绝缘图案的刻蚀选择性；以及
后侧凸块，其覆盖所述穿通电极的所述突出部分的端面并且在所述钝化图案之上延伸。
技术方案2.如技术方案1所述的半导体器件，其中，所述半导体层的所述第一表面是与所述半导体层的有源区相邻的前侧表面，所述半导体层的所述第二表面是与所述前侧表面相对的后侧表面。
技术方案3.如技术方案1所述的半导体器件，其中，所述穿通电极包括与所述半导体层的所述第一表面相邻的第一端面，并且所述突出部分具有第二端面。
技术方案4.如技术方案3所述的半导体器件，其中，所述穿通电极的所述第二端面与所述钝化图案的表面共面。
技术方案5.如技术方案1所述的半导体器件，其中，所述第一绝缘图案包括氮化物层，所述第二绝缘图案包括氧化物层。
技术方案6.如技术方案1所述的半导体器件，其中，所述钝化图案的位于所述后侧凸块之下的部分具有第一厚度，而所述钝化图案的位于所述半导体层的所述第二表面上的不与所述后侧凸块重叠的部分具有小于所述第一厚度的第二厚度。
技术方案7.如技术方案1所述的半导体器件，其中，所述前侧凸块包括金属柱体和设置在所述金属柱体之上的焊接凸块。
技术方案8.如技术方案1所述的半导体器件，其中，所述后侧凸块包括晶种金属图案、设置在所述晶种金属图案之上的第一金属层、以及设置在所述第一金属层之上的第二金属层。
技术方案9.一种半导体器件，包括：
半导体层，其具有第一表面和第二表面；
穿通电极，其穿通所述半导体层，并且具有在所述半导体层的所述第二表面之上突出预定高度的突出部分；
前侧凸块，其设置在所述半导体层的所述第一表面之上，并且与所述穿通电极电连接；
钝化图案，其包围所述穿通电极的所述突出部分的侧壁，并且延伸至所述半导体层的所述第二表面上；以及
后侧凸块，其覆盖所述穿通电极的所述突出部分的端面并且延伸至所述钝化图案上，
其中，所述钝化图案的位于所述后侧凸块之下的第一部分具有第一厚度，而所述钝化图案的位于所述半导体层的所述第二表面上的不与所述后侧凸块重叠的位置处的第二部分具有第二厚度。
技术方案10.如技术方案9所述的半导体器件，其中，所述穿通电极包括与所述半导体层的所述第一表面相邻的第一端面，并且所述突出部分具有第二端面。
技术方案11.如技术方案9所述的半导体器件，其中，所述钝化图案包括氮化物材料的单材料层。
技术方案12.如技术方案9所述的半导体器件，其中，所述钝化图案的所述第二厚度比所述钝化图案的所述第一厚度小。
技术方案13.一种半导体封装体，包括：
封装体衬底；
第一半导体芯片，其安装在所述封装体衬底上；以及
至少一个半导体芯片，其设置在所述第一半导体芯片之上，
其中，所述第一半导体芯片和所述至少一个半导体芯片中的每个包括：半导体层、穿通所述半导体层并且具有从所述半导体层的后侧表面突出的突出部分的穿通电极、设置在所述半导体层的前侧表面之上并且与所述穿通电极电连接的前侧凸块、设置在所述半导体层的所述后侧表面之上并且与所述穿通电极的所述突出部分电连接的后侧凸块、以及包围所述穿通电极的所述突出部分的侧壁并且延伸至所述半导体层的所述后侧表面上的钝化图案。
技术方案14.如技术方案13所述的半导体封装体，其中，所述钝化图案包括具有不同刻蚀速率的至少两种绝缘图案。
技术方案15.如技术方案13所述的半导体封装体，
其中，所述钝化图案包括第一绝缘图案和位于所述第一绝缘图案上的第二绝缘图案；以及
其中，所述第一绝缘图案包括氮化物层，所述第二绝缘图案包括氧化物层。
技术方案16.如技术方案14所述的半导体封装体，其中，所述钝化图案的位于所述后侧凸块之下的第一部分具有第一厚度，而所述钝化图案的位于所述半导体层的所述后侧表面上的不与所述后侧凸块重叠的第二部分具有小于所述第一厚度的第二厚度。
技术方案17.如技术方案14所述的半导体封装体，其中，所述后侧凸块在所述钝化图案之上延伸。
技术方案18.如技术方案1所述的半导体器件，其中，所述半导体器件被包括在电子系统中，所述电子系统还包括：
存储器；以及
控制器，其经由总线与所述存储器耦接，
其中，所述存储器或所述控制器包括所述封装体。
技术方案19.如技术方案9所述的半导体器件，其中，所述半导体器件被包括在电子系统中，所述电子系统还包括：
存储器；以及
控制器，其经由总线与所述存储器耦接，
其中，所述存储器或所述控制器包括所述封装体。
技术方案20.一种如技术方案13所述的半导体封装体，其中，所述半导体封装体被包括在电子系统中，所述电子系统还包括：
存储器；以及
控制器，其经由总线与所述存储器耦接，
其中，所述存储器或所述控制器包括所述封装体。

Claims (10)

1.一种半导体器件，包括：
半导体层，其具有第一表面和第二表面；
穿通电极，其穿通所述半导体层，并且具有在所述半导体层的所述第二表面之上突出预定高度的突出部分；
前侧凸块，其设置在所述半导体层的所述第一表面之上，并且与所述穿通电极电耦接；
钝化图案，其包括第一绝缘图案和第二绝缘图案，所述第一绝缘图案包围所述穿通电极的所述突出部分的侧壁，并且延伸至所述半导体层的所述第二表面上，所述第二绝缘图案覆盖所述第一绝缘图案，并且具有相对于所述第一绝缘图案的刻蚀选择性；以及
后侧凸块，其覆盖所述穿通电极的所述突出部分的端面并且在所述钝化图案之上延伸。
2.如权利要求1所述的半导体器件，其中，所述半导体层的所述第一表面是与所述半导体层的有源区相邻的前侧表面，所述半导体层的所述第二表面是与所述前侧表面相对的后侧表面。
3.如权利要求1所述的半导体器件，其中，所述穿通电极包括与所述半导体层的所述第一表面相邻的第一端面，并且所述突出部分具有第二端面。
4.如权利要求3所述的半导体器件，其中，所述穿通电极的所述第二端面与所述钝化图案的表面共面。
5.如权利要求1所述的半导体器件，其中，所述第一绝缘图案包括氮化物层，所述第二绝缘图案包括氧化物层。
6.如权利要求1所述的半导体器件，其中，所述钝化图案的位于所述后侧凸块之下的部分具有第一厚度，而所述钝化图案的位于所述半导体层的所述第二表面上的不与所述后侧凸块重叠的部分具有小于所述第一厚度的第二厚度。
7.如权利要求1所述的半导体器件，其中，所述前侧凸块包括金属柱体和设置在所述金属柱体之上的焊接凸块。
8.一种半导体器件，包括：
半导体层，其具有第一表面和第二表面；
穿通电极，其穿通所述半导体层，并且具有在所述半导体层的所述第二表面之上突出预定高度的突出部分；
前侧凸块，其设置在所述半导体层的所述第一表面之上，并且与所述穿通电极电连接；
钝化图案，其包围所述穿通电极的所述突出部分的侧壁，并且延伸至所述半导体层的所述第二表面上；以及
后侧凸块，其覆盖所述穿通电极的所述突出部分的端面并且延伸至所述钝化图案上，
其中，所述钝化图案的位于所述后侧凸块之下的第一部分具有第一厚度，而所述钝化图案的位于所述半导体层的所述第二表面上的不与所述后侧凸块重叠的位置处的第二部分具有第二厚度。
9.一种半导体封装体，包括：
封装体衬底；
第一半导体芯片，其安装在所述封装体衬底上；以及
至少一个半导体芯片，其设置在所述第一半导体芯片之上，
其中，所述第一半导体芯片和所述至少一个半导体芯片中的每个包括：半导体层、穿通所述半导体层并且具有从所述半导体层的后侧表面突出的突出部分的穿通电极、设置在所述半导体层的前侧表面之上并且与所述穿通电极电连接的前侧凸块、设置在所述半导体层的所述后侧表面之上并且与所述穿通电极的所述突出部分电连接的后侧凸块、以及包围所述穿通电极的所述突出部分的侧壁并且延伸至所述半导体层的所述后侧表面上的钝化图案。
10.一种如权利要求9所述的半导体封装体，其中，所述半导体封装体被包括在电子系统中，所述电子系统还包括：
存储器；以及
控制器，其经由总线与所述存储器耦接，
其中，所述存储器或所述控制器包括所述封装体。
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