CN104851890A - 一种多晶硅层形成方法、ltps阵列基板及显示装置 - Google Patents
一种多晶硅层形成方法、ltps阵列基板及显示装置 Download PDFInfo
- Publication number
- CN104851890A CN104851890A CN201510179587.1A CN201510179587A CN104851890A CN 104851890 A CN104851890 A CN 104851890A CN 201510179587 A CN201510179587 A CN 201510179587A CN 104851890 A CN104851890 A CN 104851890A
- Authority
- CN
- China
- Prior art keywords
- layer
- amorphous silicon
- polysilicon layer
- formation method
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 title claims abstract description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 64
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 56
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 32
- 150000002500 ions Chemical class 0.000 claims abstract description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000000137 annealing Methods 0.000 claims abstract description 9
- -1 phosphonium ions Chemical class 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 39
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 238000002425 crystallisation Methods 0.000 claims description 10
- 230000008025 crystallization Effects 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 230000001939 inductive effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- XNMARPWJSQWVGC-UHFFFAOYSA-N 2-[3-[11-[[5-(dimethylamino)naphthalen-1-yl]sulfonylamino]undecanoylamino]propoxy]-4-[(5,5,8,8-tetramethyl-6,7-dihydronaphthalene-2-carbonyl)amino]benzoic acid Chemical compound CC1(C)CCC(C)(C)C=2C1=CC(C(=O)NC=1C=C(C(=CC=1)C(O)=O)OCCCNC(=O)CCCCCCCCCCNS(=O)(=O)C1=C3C=CC=C(C3=CC=C1)N(C)C)=CC=2 XNMARPWJSQWVGC-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005499 laser crystallization Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910012990 NiSi2 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明提供一种多晶硅层形成方法,包括:在一基板的一表面上沉积形成非晶硅离子参杂层及氮化硅层,所述氮化硅层位于非晶硅离子参杂层之上;其中,所述非晶硅离子参杂层中含有磷离子;在所述氮化硅层上形成非晶硅层;在所述非晶硅层上形成镍层;形成多晶硅层,即对形成镍层后的非晶硅层进行退火并诱发所述非晶硅层结晶。本发明还提供一种LTPS阵列基板及显示装置。
Description
技术领域
本发明涉及液晶显示制造领域,尤其涉及一种制多晶硅层形成方法、LTPS阵列基板及显示装置。
背景技术
目前LTPS阵列基板的多晶硅层的结晶技术可分为雷射结晶(ELA)技术,金属诱发结晶(MIC)与固相结晶技术(SPC),其中最为广泛使用的量产技术为雷射结晶技术,然而造成制造成本高。而传统的SPC技术有温度过高退火时间过久的缺点,不适合量产。而金属诱发结晶的技术就是能够克服SPC的缺点,利用金属在非晶矽中形成金属矽化物来诱发结晶,可降低退火温度和减少退火时间,但是在多晶硅层会产生金属污染的问题,在基板制作时会造成漏电流过大而影响到电晶体的效能,进而影响液晶面板的质量。
发明内容
本发明提供一种多晶硅层形成方法,可以减少多晶硅层的金属污染,保证液晶面板的质量。
本发明还涉及一种LTPS阵列基板。
本发明提供一种多晶硅层形成方法,包括:
在一基板的一表面上沉积形成非晶硅离子参杂层及氮化硅层,所述氮化硅层位于非晶硅离子参杂层之上;其中,所述非晶硅离子参杂层中含有磷离子;
在所述氮化硅层上形成非晶硅层;
在所述非晶硅层上形成镍层;
形成多晶硅层,即对形成镍层后的非晶硅层进行退火并诱发所述非晶硅层结晶。
其中,所述非晶硅离子参杂层为N型离子与非晶硅通过化学气相沉积方式形成。
其中,所述氮化硅层通过化学气相沉积方式形成。
其中,所述氮化硅层厚度为500~1000埃,成型温度300~450度。
其中,所述非晶硅离子参杂层的厚度为500埃,成型温度300~450度。
其中,所述对形成镍层后的非晶硅层进行退火的步骤是在有氮气的环境且恒温进行。
其中,所述在所述非晶硅层上形成镍层的方式是通过物理溅射沉积方式形成。
其中,在形成多晶硅层的步骤中,所述镍层的一部分镍与非晶硅层中的硅元素形成金属硅化物进行诱发结晶,另一部分镍被吸附到非晶硅离子参杂层及氮化硅层内。
本发明还提供一种LTPS阵列基板,其特征在于,所述LTPS阵列基板包括基板及多晶硅层,所述多晶硅层通过以上所述的多晶硅层形成方法形成于所述基板上。
本发明还提供一种显示装置,其包括以上所述的LTPS阵列基板。。
本发明的LTPS阵列基板设有非晶硅离子参杂层,用于吸附多晶硅层结晶时剩余部分的镍;进而使剩余的镍远离所述多晶硅层,减少金属杂质的污染。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明的多晶硅层形成方法流程图。
图2-图4是图1所示的多晶硅层形成方法制造流程中的截面示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明保护一种多晶硅层形成方法,主要是形成LTPS阵列基板的半导体层。请参阅图1与图2,所述多晶硅层形成方法包括:
步骤S1,在一基板11的一表面上沉积形成非晶硅离子参杂层12及氮化硅层13,所述氮化硅层13位于非晶硅离子参杂层12之上;其中,所述非晶硅离子参杂层12中含有磷离子。本实施例中,所述非晶硅离子参杂层12为P离子与非晶硅a-si通过化学气相沉积方式形成。所述非晶硅离子参杂层12的厚度为500埃,成型温度300~450度,可经由流量与成分比例控制来沈积适合的非晶硅离子掺杂层,一般的成分为SiH4,H2与PH3。此非晶硅离子掺杂层不掺杂时,即沈积成分中没有PH3也有同样的吸附效果。
本实施例中,所述氮化硅层13通过化学气相沉积方式形成。所述氮化硅层13的厚度为500~1000埃,成型温度300~450度。
步骤S2,在所述氮化硅层13上形成非晶硅层14。
请一并参阅图3,步骤S3,在所述非晶硅层14上形成镍层15。本实施例中,所述在所述非晶硅层14上形成镍层15的方式是通过物理溅射沉积方式形成,可藉由控制沈积的功率与流量来控制镀覆的镍的浓度。
请参阅图4,步骤S4,形成多晶硅层16,即对形成镍层后的非晶硅层进行退火并诱发所述非晶硅层结晶,一般退火温度为500~600度数小时,或者使用快速退火炉(RTA)可降低退火的时间到数分钟都可达到退火的效果本实施例中,在形成多晶硅层的步骤中,镍层15的一部分镍与硅元素形成金属硅化物进行诱发结晶,另一部分镍被吸附到非晶硅离子参杂层及氮化硅层内。
本实施例中,所述对形成镍层后的非晶硅层进行退火的步骤是在有氮气的环境且恒温进行。
现有技术在半导体制程中,由于会受到晶格缺陷或金属类杂质污染的影响,造成元件漏电流而影响元件特性的技术问题,而本发明恰好避免了这个技术问题,即本发明的多晶硅层形成方法通过在非晶硅层下方形成具有吸附作用的非晶硅离子参杂层12及氮化硅层13,当退火时镍会和硅发生化学反应形成NiSi2(金属硅化物)进行诱发结晶,也会有剩余部分没反应的镍存在,而这些存在的镍会因浓度差的关系被氮化硅层13吸附,同时与非晶硅离子参杂层12层中的磷和镍发生反应形成稳定的磷化物,即非晶硅离子参杂层12层同样吸附剩余部分的镍;进而使剩余的镍远离所述多晶硅层16,减少金属杂质的污染。
本发明还提供一种LTPS阵列基板及具有所述阵列基板的显示装置,所述LTPS阵列基板包括基板11及多晶硅层16,所述多晶硅层通过所述的多晶硅层形成方法形成于所述基板11上。所述基板11为玻璃板。所述LTPS阵列基板的多晶硅层以上的其余部分结构(图未示)制造方法,均是通过现有技术光刻工艺以及刻蚀、预定图形的工艺、光刻胶、掩模板、曝光机等形成图形等工艺形成,再次不做赘述。
以上所揭露的仅为本发明一种较佳实施例而已,当然不能以此来限定本发明之权利范围,本领域普通技术人员可以理解实现上述实施例的全部或部分流程,并依本发明权利要求所作的等同变化,仍属于发明所涵盖的范围。
Claims (10)
1.一种多晶硅层形成方法,包括:
在一基板的一表面上沉积形成非晶硅离子参杂层及氮化硅层,所述氮化硅层位于非晶硅离子参杂层之上;其中,所述非晶硅离子参杂层中含有磷离子;
在所述氮化硅层上形成非晶硅层;
在所述非晶硅层上形成镍层;
形成多晶硅层,即对形成镍层后的非晶硅层进行退火并诱发所述非晶硅层结晶。
2.如权利要求1所述的多晶硅层形成方法,其特征在于,所述非晶硅离子参杂层为P型离子与非晶硅通过化学气相沉积方式形成。
3.如权利要求1或2所述的多晶硅层形成方法,其特征在于,所述氮化硅层通过化学气相沉积方式形成。
4.如权利要求1或2所述的多晶硅层形成方法,其特征在于,所述氮化硅层厚度为500~1000埃,成型温度300~450度。
5.如权利要求1或2所述的多晶硅层形成方法,其特征在于,所述非晶硅离子参杂层的厚度为500埃,成型温度300~450度。
6.如权利要求1或2所述的多晶硅层形成方法,其特征在于,所述对形成镍层后的非晶硅层进行退火的步骤是在有氮气的环境且恒温进行。
7.如权利要求1或2所述的多晶硅层形成方法,其特征在于,所述在所述非晶硅层上形成镍层的方式是通过物理溅射沉积方式形成。
8.如权利要求2所述的多晶硅层形成方法,其特征在于,在形成多晶硅层的步骤中,所述镍层的一部分镍与非晶硅层中的硅元素形成金属硅化物进行诱发结晶,另一部分镍被吸附到非晶硅离子参杂层及氮化硅层内。
9.一种LTPS阵列基板,其特征在于,所述LTPS阵列基板包括基板及多晶硅层,所述多晶硅层通过权利要求1-8任一项所述的多晶硅层形成方法形成于所述基板上。
10.一种显示装置,其特征在于,其包括权利要求9所述的LTPS阵列基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510179587.1A CN104851890A (zh) | 2015-04-16 | 2015-04-16 | 一种多晶硅层形成方法、ltps阵列基板及显示装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510179587.1A CN104851890A (zh) | 2015-04-16 | 2015-04-16 | 一种多晶硅层形成方法、ltps阵列基板及显示装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104851890A true CN104851890A (zh) | 2015-08-19 |
Family
ID=53851402
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510179587.1A Pending CN104851890A (zh) | 2015-04-16 | 2015-04-16 | 一种多晶硅层形成方法、ltps阵列基板及显示装置 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104851890A (zh) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020192884A1 (en) * | 2001-03-06 | 2002-12-19 | United Microelectronics Corp. | Method for forming thin film transistor with reduced metal impurities |
CN101064246A (zh) * | 2006-04-27 | 2007-10-31 | 香港科技大学 | 非晶硅的金属诱导结晶和金属吸除技术 |
CN101192519A (zh) * | 2006-11-27 | 2008-06-04 | 中华映管股份有限公司 | 半导体元件及其制作方法 |
-
2015
- 2015-04-16 CN CN201510179587.1A patent/CN104851890A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020192884A1 (en) * | 2001-03-06 | 2002-12-19 | United Microelectronics Corp. | Method for forming thin film transistor with reduced metal impurities |
CN101064246A (zh) * | 2006-04-27 | 2007-10-31 | 香港科技大学 | 非晶硅的金属诱导结晶和金属吸除技术 |
CN101192519A (zh) * | 2006-11-27 | 2008-06-04 | 中华映管股份有限公司 | 半导体元件及其制作方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1058583C (zh) | 半导体的制造方法 | |
US8436355B2 (en) | Thin-film transistor, manufacturing method therefor, and electronic device using a thin-film transistor | |
KR20100100187A (ko) | 다결정 실리콘층의 제조방법 | |
US10700211B2 (en) | Thin film transistors with epitaxial source/drain contact regions | |
US20130023111A1 (en) | Low temperature methods and apparatus for microwave crystal regrowth | |
CN109786440A (zh) | 阵列基板的制造方法、装置及阵列基板 | |
TW201346060A (zh) | 形成鍺薄膜之方法 | |
JPH0391239A (ja) | 半導体装置の製造方法 | |
CN102832169A (zh) | 阵列基板及其制备方法、显示器件 | |
CN107275191A (zh) | 一种薄膜晶体管及制备方法、阵列基板和显示面板 | |
TW200824003A (en) | Semiconductor device and manufacturing method thereof | |
KR100628989B1 (ko) | 비정질 실리콘 박막의 결정화 방법 | |
US20220375753A1 (en) | Doping Techniques | |
CN104851890A (zh) | 一种多晶硅层形成方法、ltps阵列基板及显示装置 | |
CN103943509A (zh) | 薄膜晶体管的制程方法 | |
WO2007061273A1 (en) | Method of forming silicon film by two step deposition | |
TW201833996A (zh) | 在鰭式場效電晶體(finfet)裝置上形成共形磊晶半導體覆層材料之方法 | |
CN108666209B (zh) | 一种半导体衬底的制作方法 | |
KR100452444B1 (ko) | 다결정 실리콘 박막트랜지스터 제조방법 | |
CN112736087A (zh) | 一种阵列基板的制作方法、阵列基板及显示面板 | |
EP4174209A1 (en) | Method of forming a doped polysilicon layer | |
CN108666259A (zh) | 贴合晶圆的制造方法以及贴合晶圆 | |
CN104465346B (zh) | 形成栅极的方法 | |
KR100447893B1 (ko) | 박막 트랜지스터 제조방법 | |
KR100472855B1 (ko) | 반도체소자의다결정실리콘박막제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
EXSB | Decision made by sipo to initiate substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150819 |
|
RJ01 | Rejection of invention patent application after publication |