CN104851882A - 半导体集成电路、包括该电路的开关电源以及包括该电源的控制系统 - Google Patents

半导体集成电路、包括该电路的开关电源以及包括该电源的控制系统 Download PDF

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CN104851882A
CN104851882A CN201510155020.0A CN201510155020A CN104851882A CN 104851882 A CN104851882 A CN 104851882A CN 201510155020 A CN201510155020 A CN 201510155020A CN 104851882 A CN104851882 A CN 104851882A
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三岛健人
永井富幸
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Mitsumi Electric Co Ltd
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    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
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    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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Abstract

本发明提供一种半导体集成电路，其可以防止由寄生元件动作引起的不稳定动作。该半导体集成电路包括：构成电流镜的一对晶体管(63、65)，该电流镜具有使输入输出为不同电流值的输入输出比特性；以及根据所述电流镜的输出电流生成基准电压的输出晶体管。该半导体集成电路的特征在于一对晶体管(63、65)中的所述电流值小的晶体管(63)侧的集电极区域(85A)的总面积与一对晶体管(63、65)中的所述电流值大的晶体管(65)侧的集电极区域(82)和(88)合起来的总面积彼此相等。

Description

半导体集成电路、包括该电路的开关电源以及包括该电源的控制系统
本申请是申请号为201110226277.2、发明名称为“半导体集成电路、包括该电路的开关电源以及包括该电源的控制系统”的专利申请的分案申请。
技术领域
本发明涉及半导体集成电路、包括该电路的开关电源以及包括该电源的控制系统，该半导体集成电路包括构成具有使输入输出为不同电流值的输入输出比特性的电流镜的一对晶体管、以及根据所述电流镜的输出电流来输出基准电压的输出晶体管。
背景技术
图1是作为开关电源的一个例子的降压开关调节器100的结构图。降压开关调节器100是DC-DC变换器，将由连接到一对电源输入端子2、3上的外部电源1提供的输入电压VB降压，将从输出端子10输出的输出电压VOUT调节为预定目标电压。降压开关调节器100包括：平滑输入电压VB的输入电容器4；形成高侧(High side)的驱动晶体管24和低侧(Low side)的驱动晶体管25的半导体集成电路20；一端连接到驱动晶体管24和驱动晶体管25的接点上、另一端连接到输出端子10上的电感器6；以及被提供电感器6中积累的能量，平滑输出电压VOUT的输出电容器9。作为驱动晶体管24等的半导体开关元件的具体例子，例如有MOSFET、双极性晶体管。
如公知那样，半导体集成电路20的PWM驱动电路23根据从振荡器22输出的周期信号和从误差放大器26输出的误差放大信号，以同步整流的方式对用于驱动电感器6的驱动晶体管24、25进行PWM驱动，从而从输出端子10输出把以接地端子29为基准、从电源端子27提供的输入电压VB降压调整为预定的目标电压后的输出电压VOUT。误差放大器26放大基准电压VREF与反馈电压VFB的差。基准电压VREF由基准电压生成电路21基于输入电压VB生成，并且由连接到基准电压端子28上的电容器5进行平滑。反馈电压VFB是由电阻7、8将输出电压VOUT分压之后由反馈端子31输入的电压。
图2是表示形成驱动晶体管25等的半导体集成电路20的结构的截面图。在P型半导体衬底41的表面上形成n型井42。在n型井42内形成n+型源极区域44和n+型漏极区域47。在源极区域44和漏极区域47之间形成栅极氧化膜45。也就是，在图2中示出的半导体集成电路20中，形成具有设置在源极区域44上的源电极、设置在漏极区域47上的漏电极53以及设置在栅极氧化膜45上的栅电极52的N沟道MOSFET。
当该N沟道MOSFET是在图1中所示的低侧驱动晶体管25时，源极区域44连接到地，漏电极53连接到在图1中所示的开关端子30。也就是，漏电极53相当于驱动晶体管24和驱动晶体管25的接点。
在这样的结构的情况下，当高侧驱动晶体管24关断时，漏电极53的电位VDB如图3所示那样瞬间降低到负电位。由此，形成为n+型漏极区域47构成发射极、P型半导体衬底41构成基极、以及与驱动晶体管24形成在同一半导体集成电路20的P型半导体衬底41上的另一元件的n+区域49构成集电极的NPN型双极性晶体管的寄生元件56，进行将电流从该另一元件的n+区域49导引到P型半导体衬底41侧的动作。
但是，由于通过寄生元件56的这样的动作，使设置在n+区域49上的漏电极54的电位VDA也如图3所示那样地降低，所以有可能导致使用n+区域49的另一元件和包含该另一元件的另一电路误动作。作为防止这样的误动作的手段，已知设置护圈(Guardring)以抑制寄生元件的动作的技术(例如参考专利文献1)。
专利文献1日本特开2001－77682号公报
专利文献2日本特开平11－65690号公报
专利文献3日本特开2006－313438号公报
发明内容
因此得出，形成在半导体集成电路内部的寄生元件的动作是使在该半导体集成电路中形成的其它电路的动作不稳定的主要原因。例如，作为导致动作变得不稳定的电路例举为基准电压生成电路。
图4是基准电压生成电路21A的电路图。基准电压生成电路21A是在图1中所示的基准电压生成电路21的一个例子，其电路结构例如已在专利文献2、3中公开。基准电压生成电路21A包括构成具有使输入输出为不同电流值的输入输出比特性的电流镜的一对晶体管(63、65)、以及根据该电流镜的输出电流生成基准电压VREF的输出晶体管67。在把该电流镜构成为使晶体管65流动相对于晶体管63的集电极电流N倍的集电极电流的情况下，当在以晶体管63的集电极区域为集电极的寄生晶体管68中流动的电流为I时，在以晶体管65的集电极区域为集电极的寄生晶体管69中流动的电流为N×I。根据图5说明其装置结构。
图5是表示形成有构成电流镜的一对晶体管(63、65)的现有的半导体集成电路的结构的截面图和顶视图，该电流镜具有使输入输出为不同电流值的输入输出比特性。图5表示构成为晶体管65中流动相对于晶体管63的集电极电流2倍(即N＝2)的集电极电流的情况。当由于连接到漏电极53上的晶体管(例如在图1中示出的高侧驱动晶体管24)的动作，使得漏电极53的电位VDB降低到负电位时，由于作为NPN型双极性晶体管形成的寄生元件94动作而流动寄生通路电流。也就是，在晶体管63的n+型集电极区域85、P型半导体衬底81、n+型漏极区域47的路径中，流动电流值I的寄生通路电流时，由于晶体管65的集电极区域82和88合起来的总面积是晶体管63的集电极区域85的面积的2倍，所以在晶体管65的集电极区域82、88、P型半导体衬底81、漏极区域47的路径中，流动电流值(2×I)的寄生通路电流。
因此，由于这样的寄生通路电流流动，使得由晶体管63、65构成的电流镜的动作电流失去平衡，所以由图4所示的输出晶体管67生成的基准电压VREF偏离预定的目标值(设计值)。
这样的基准电压生成电路的不稳定动作可能会引起利用由基准电压生成电路生成的基准电压VREF的开关电源产生不稳定动作(例如输出电压VOUT产生偏差)，另外还可能会引起利用由该开关电源生成的输出电压VOUT的控制系统产生不稳定动作(例如检测出输出电压VOUT异常)。
因此，本发明的目的是提供可以防止由寄生元件动作引起的不稳定动作的、具有生成基准电压的电路的半导体集成电路、包括该集成电路的开关电源以及包括该开关电源的控制系统。
为了实现上述目的，本发明的半导体集成电路，包括：构成电流镜的一对晶体管，该电流镜具有使输入输出为不同电流值的输入输出比特性；以及根据所述电流镜的输出电流生成基准电压的输出晶体管，该半导体集成电路的特征在于，所述一对晶体管中的所述电流值小的第一晶体管侧的集电极区域的总面积和所述一对晶体管中的所述电流值大的第二晶体管侧的集电极区域的总面积彼此相等。
此外，为了实现上述目的，本发明的开关电源，包括：该半导体集成电路；由形成在所述半导体集成电路的半导体衬底上的驱动晶体管驱动的感应元件；以及被提供积累在所述感应元件中的能量的电容元件；
所述驱动晶体管根据所述基准电压和在所述电容元件中产生的输出电压的反馈电压，驱动所述感应元件，从而使所述输出电压恒定。
此外，为了实现上述目的，本发明的控制系统，包括：该开关电源、以及具有用于检测所述输出电压的异常的异常检测部的控制装置。
根据本发明，可以防止由寄生元件动作引起的不稳定动作。
附图说明
图1是作为开关电源的一个例子的降压开关调节器100的结构图。
图2是表示形成驱动晶体管25等的半导体集成电路20的结构的截面图。
图3是驱动晶体管24开关时的波形图。
图4是基准电压生成电路21A的电路图。
图5是表示现有的半导体集成电路的结构的截面以及顶视图；
图6是表示本发明第一实施方式的半导体集成电路的结构的截面和顶视图；
图7是基准电压生成电路21B的电路图。
图8是表示本发明第二实施方式的半导体集成电路的结构的截面和顶视图；
图9是表示负载电流IL和基准电压VREF的关系的图。
图10是作为开关电源的一个例子的升压开关调节器200的结构图。
图11是具有利用由开关调节器100(或200)生成的输出电压VOUT的控制装置300的控制系统400的结构图。
符号说明
6  电感器(感应元件)
9  输出电容器(电容元件)
20  半导体集成电路
24、25  驱动晶体管
41、81  P型半导体衬底
56、68、69、71、72、94  寄生NPN型双极性晶体管
100  降压开关调节器
200  升压开关调节器
300  控制装置
400  控制系统
具体实施方式
以下将参考附图说明实施本发明的实施方式。
(实施例1)
实施例1的基准电压生成电路的电路结构与在图4中表示的基准电压生成电路21A相同。晶体管63的集电极和基极相互连接并且经由电阻62连接到恒定电流源61的下游侧。晶体管63的发射极接地。晶体管65的集电极连接到晶体管67的基极，并经由电阻64连接到恒定电流源61的下游侧。晶体管65的发射极经由电阻66接地。晶体管67的集电极连接到恒定电流源61的下游侧，晶体管67的发射极接地。恒定电流源61的上游侧连接到输入电压VB。通过这样的电路结构，在晶体管67的集电极上生成恒定的基准电压VREF。
由一对晶体管(63、65)构成的电流镜的输入输出比特性是1：N(N是除1以外的正数)。即，输入侧的晶体管63的集电极电流(电流镜的输入电流)和输出侧的晶体管65的集电极电流(电流镜的输出电流)的电流比是1：N。
图6表示N＝2的情况。晶体管63、65可分别由一个晶体管元件构成，也可以由并联连接的多个晶体管元件构成。在图6的情况中，晶体管63由一个晶体管元件构成，晶体管65由并联连接的两个晶体管元件构成。由于晶体管65的发射极区域84和90合起来的总面积为晶体管63的发射极区域87的面积的N倍(即在图6的情况中是2倍)，所以输入侧的晶体管63的集电极电流(电流镜的输入电流)和输出侧的晶体管65的集电极电流(电流镜的输出电流)的电流比是1：2。
在图6的情况中，作为各晶体管元件的晶体管的特性彼此相同。例如，如图6所示，各晶体管元件的n+型发射极区域84、87、90的面积彼此相等。此外，各晶体管元件的P型基极区域83、86、89的面积彼此相等。
此外，一对晶体管(63、65)中的集电极电流小的晶体管63侧的集电极区域85A的面积与一对晶体管(63、65)中的集电极电流大的晶体管65侧的集电极区域82和88的面积合起来的总面积相等。根据这样的结构，即使由于漏电极53的电位VDB降低到负电位，使作为NPN型双极性晶体管形成的寄生元件94动作，由晶体管63、65构成的电流镜的动作电流也不会失去平衡，所以可以防止由寄生元件94动作引起的不稳定动作。
这个原因是，即使由于漏电极53的电位VDB降低到负电位，而使晶体管65的集电极区域82、88、P型半导体衬底81、漏极区域47的路径中流动电流值为(2×I)的寄生通路电流，而由于晶体管65的集电极区域82和88合起来的总面积与晶体管63的集电极区域85A的面积相同，所以在晶体管63的n+型的集电极区域85A、P型半导体衬底81、n+型的漏极区域47的路径中也流动与电流值(2×I)相同的寄生通路电流。
也就是，在构成电流镜的一对晶体管中，在一个晶体管(第一晶体管)的集电极电流的电流值和另一个晶体管(第二晶体管)的集电极电流的电流值的比是1：N的情况下，并且构成第二晶体管的多个晶体管元件的集电极区域的面积彼此相同的情况下，使第一晶体管侧的集电极区域的总面积等于构成第二晶体管的一个晶体管元件的集电极区域的面积的N倍即可。由此，由于在第一晶体管侧流动的寄生通路电流与在第二晶体管侧流动的寄生通路电流成为相同的电流值(N×I)，所以在由第一晶体管和第二晶体管构成的电流镜中流动的动作电流不会失去平衡，从而可以防止由寄生元件94动作引起的不稳定动作。
(实施例2)
图7是表示实施例2的基准电压生成电路21B的电路结构图。在此省略与图4相同的结构的说明。由一对晶体管(63、65)构成的电流镜的输入输出比特性是1：N(N是除1以外的正数)。图7表示相对于图4的电路结构增加了(N－1)个晶体管70的电路结构。(N－1)个晶体管70的各集电极连接到晶体管63的集电极。此外，基极、发射极和集电极相互被短路，以使得各晶体管70不动作。
通过这样的结构，当在将晶体管65的集电极区域作为集电极的寄生晶体管72中流动的电流为N×I时，在将晶体管63的集电极区域作为集电极的寄生晶体管71中流动的电流也为N×I。原因是晶体管70的(N－1)个集电极区域和晶体管63的一个集电极区域合起来后的N个集电极区域的总面积等于晶体管65的N个集电极区域的总面积。
图8表示N＝2的情况。在此省略与图6相同的结构的说明。一对晶体管(63、65)中的集电极电流小的晶体管63侧的集电极区域85和95合起来后的总面积与一对晶体管(63、65)中的集电极电流大的晶体管65侧的集电极区域82和88合起来后的总面积彼此相等。
根据这样的结构，与实施例1相同，由于晶体管65的集电极区域82和88合起来的总面积与晶体管63的集电极区域85和95合起来的总面积相同，所以即使漏电极53的电位VDB降低到负电位，而使作为NPN型双极性晶体管形成的寄生元件94动作，由于由晶体管63、65构成的电流镜的输入侧和输出侧两侧中都流动与(2×I)相同的电流值的寄生通路电流，所以该电流镜的动作电流不会失去平衡，从而可以防止由寄生元件94动作引起的不稳定动作。
图9是表示在现有的图5的结构和作为本发明实施例的图8的结构这两种情况中，在图1的降压开关调节器100的输出端子10中流动的负荷电流IL和基准电压VREF的关系的图。由于随着负载电流IL的增加，向漏电极53的电位VDB的负侧的降低量变大，所以容易引起基准电压生成电路的不稳定动作。结果，在图5的结构中，在负荷电流IL大的区域中基准电压VREF产生升高，而在图8的结构中，可以抑制产生这样的升高，并且维持生成恒定的基准电压VREF。
虽然在上文中详细地说明了本发明的优选实施例，但是本发明不限于上述实施例，在不脱离本发明的范围内可以对上述实施例进行各种变形和置换。
例如，在图1中，也可以将驱动晶体管25置换为二极管11，或者在驱动晶体管24和驱动晶体管25的接点与电感器6之间增加二极管11，从而通过二极管整流方式(非同步整流方式)驱动电感器6。此外，还可以将N沟道型或NPN型驱动晶体管24置换为P沟道型或PNP型驱动晶体管，同时去除驱动晶体管25，从而通过二极管整流方式((非同步整流方式)驱动电感器6。
此外，作为本发明的实施方式，虽然在图1中示例了降压开关调节器100，但是也可以是升压开关调节器。图10是升压开关调节器200的结构图。在升压开关调节器200的情况下，由于连接有用于驱动电感器6的驱动晶体管25的源电极的地电位容易变化，所以以地电位为基准生成的基准电压VREF容易产生偏差。本发明可以有效地抑制该偏差。
此外，可以防止具有利用输出电压VOUT的控制装置的控制系统的不稳定动作，该输出电压VOUT由利用基准电压VREF的开关电源生成。图11是具有利用由开关调节器100(或200)生成的输出电压VOUT的控制装置300的控制系统400的结构图。把输出电压VOUT输入到控制装置300的输入端子12。
控制系统400包括开关调节器100(或200)和控制装置300。控制装置300包括检测输出电压VOUT的异常的异常检测部310、以及将输出电压VOUT作为电源电压而输入的控制部320。在控制装置300为微型计算机的情况下，作为控制部320的具体例子，例如有中央运算处理装置。根据上述结构，由于不会由于寄生元件动作而导致输出电压VOUT不稳定，所以即使实际发生寄生元件动作，也可以防止由于该动作引起异常检测部310检测为输出电压VOUT异常。此外，因为不会由于寄生元件动作而导致输出电压VOUT不稳定，所以可以防止将不稳定的输出电压VOUT输入到控制部320中。

Claims (8)

1.一种半导体集成电路，其包括：
电流镜，其具有预定的输入输出比特性，由接受输入电流的具有晶体管元件的第一晶体管和输出输出电流的具有2个以上晶体管元件的第二晶体管构成；以及
根据所述电流镜的输出电流生成基准电压的输出晶体管，
该半导体集成电路的特征在于，
在将N设为比1大的正整数时，所述输出电流的值是所述输入电流的值的N倍，
所述第二晶体管的1个以上的晶体管元件具有1个以上的在表面图案配置中具有大致相同总面积的集电极区域，
所述第一晶体管的晶体管元件的集电极区域在表面图案配置中的总面积是所述第二晶体管的各集电极区域分别在表面图案配置中的总面积的N倍。
2.根据权利要求1所述的半导体集成电路，其特征在于，
所述第一晶体管的发射极区域的总面积与所述第二晶体管的发射极区域的总面积不同。
3.一种开关电源，其特征在于，
包括：
根据权利要求1所述的半导体集成电路；
由形成在所述半导体集成电路的半导体衬底上的驱动晶体管驱动的感应元件；以及
被提供积累在所述感应元件中的能量的电容元件，
所述驱动晶体管根据所述基准电压和在所述电容元件中产生的输出电压的反馈电压，驱动所述感应元件，从而使所述输出电压恒定。
4.根据权利要求3所述的开关电源，其特征在于，
所述开关电源是降压开关调节器。
5.根据权利要求3所述的开关电源，其特征在于，
所述开关电源是升压开关调节器。
6.一种控制系统，其特征在于，包括：
根据权利要求3所述的开关电源；以及
具有用于检测所述输出电压的异常的异常检测部的控制装置。
7.根据权利要求6所述的控制系统，其特征在于，
所述控制装置是微型计算机。
8.一种半导体集成电路，其包括：
电流镜，其具有预定的输入输出比特性，由接受输入电流的第一晶体管和输出输出电流的第二晶体管构成；
基极区域和发射极区域以及集电极区域彼此被短路的第三晶体管；以及
根据所述电流镜的输出电流生成基准电压的输出晶体管，
该半导体集成电路的特征在于，
所述输出电流的值大于所述输入电流的值，
所述第三晶体管的集电极区域与所述第一晶体管的集电极区域连接，所述第一晶体管的集电极区域和所述第三晶体管的集电极区域合在一起后的区域的总面积大致与所述第二晶体管的1个以上的集电极区域的总面积相等。
CN201510155020.0A 2010-08-23 2011-07-18 半导体集成电路、包括该电路的开关电源以及包括该电源的控制系统 Active CN104851882B (zh)

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