CN104851866A - 一种利用金属硬度差优化管脚排布的封装件及其制造方法 - Google Patents

一种利用金属硬度差优化管脚排布的封装件及其制造方法 Download PDF

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CN104851866A
CN104851866A CN201510203312.7A CN201510203312A CN104851866A CN 104851866 A CN104851866 A CN 104851866A CN 201510203312 A CN201510203312 A CN 201510203312A CN 104851866 A CN104851866 A CN 104851866A
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郭秋卫
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Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本发明公开了一种利用金属硬度差优化管脚排布的封装件及其制造方法,所述封装件主要由第一金属层、第二金属层、芯片、第一金属线、第二金属线、塑封体组成,所述第一金属层材料的硬度比第二金属层的硬度大。该发明具有成本低,管脚位置和排布更灵活的特点。

Description

一种利用金属硬度差优化管脚排布的封装件及其制造方法
技术领域
本发明属于集成电路封装技术领域,具体涉及一种利用金属硬度差优化管脚排布的封装件及其制造方法。
背景技术
目前,传统QFN框架利用铜材正反面不同图形腐蚀得到牢靠引脚的框架结构,其塑封还需要贴膜,存在成本较高的缺点。
发明内容
为了克服上述现有技术存在的问题,本发明提供了一种利用金属硬度差优化管脚排布的封装件及其制造方法,其通过金属层之间的硬度差,调整塑封过程的压强适合,在塑封时使得硬度软的金属层变形内陷,这样形成的结构可以保证引脚牢靠,排布灵活。
一种利用金属硬度差优化管脚排布的封装件,所述封装件主要由第一金属层、第二金属层、芯片、第一金属线、第二金属线、塑封体组成,所述第一金属层和第二金属层连接,第一金属层和第二金属层组成的联合金属层分为相互分离的左中右三段,所述芯片与联合金属层中间段的第一金属层连接,第一金属线连接芯片与联合金属层中间段的第一金属层,第二金属线连接芯片与联合金属层左段、右段的第一金属层,塑封体包围第一金属层、第二金属层、芯片、第一金属线、第二金属线。
所述第一金属层的材料为银、铜、镍、钯、金或者其复合金属,其硬度较第二金属层大。
所述第二金属层的材料为锡、锌、铝或者其复合金属。
一种利用金属硬度差优化管脚排布的封装件的制造方法,所述方法的具体步骤如下:
第一步,框架制作,依次连接第一金属层、第二金属层、第三金属层,将第一金属层和第二金属层组成的联合金属层分为相互分离的左中右三段;
第二步,装片,联合金属层中间段的第一金属层与芯片连接,第一金属线连接芯片与联合金属层中间段的第一金属层;
第三步,打线,第二金属线连接芯片与联合金属层左段、右段的第一金属层;
第四步,塑封,塑封体包围第一金属层、第二金属层、芯片、第一金属线、第二金属线;
第五步,去除第三金属层;
第六步,切割整条产品形成单个单元。
其中,所述第一金属层材料的硬度比第二金属层的硬度大。
所述第三金属层的材料为铜、铁或者其复合金属层。
附图说明
图1为框架制作示意图;
图2为装芯片示意图;
图3为打线示意图;
图4为塑封示意图;
图5为去除第三金属层示意图;
图6位切割产品为单个单元示意图。
图中,1-第一金属层、2-第二金属层、3-第三金属层、4-芯片、5-第一金属线、6-第二金属线、7-塑封体。
具体实施方式
下面结合附图对本发明做进一步的说明。
如图5所示,一种利用金属硬度差优化管脚排布的封装件,所述封装件主要由第一金属层1、第二金属层2、芯片4、第一金属线5、第二金属线6、塑封体7组成,所述第一金属层1和第二金属层2连接,第一金属层1和第二金属层2组成的联合金属层分为相互分离的左中右三段,所述芯片4与联合金属层中间段的第一金属层1连接,第一金属线5连接芯片4与联合金属层中间段的第一金属层1,第二金属线6连接芯片4与联合金属层左段、右段的第一金属层1,塑封体7包围第一金属层1、第二金属层2、芯片4、第一金属线5、第二金属线6。
所述第一金属层1的材料为银、铜、镍、钯、金或者其复合金属,其硬度较第二金属层2大。
所述第二金属层2的材料为锡、锌、铝或者其复合金属。
一种利用金属硬度差优化管脚排布的封装件的制造方法,所述方法的具体步骤如下:
第一步,框架制作,依次连接第一金属层1、第二金属层2、第三金属层3,将第一金属层1和第二金属层2组成的联合金属层分为相互分离的左中右三段,如图1所示;
第二步,装片,联合金属层中间段的第一金属层1与芯片4连接,第一金属线5连接芯片4与联合金属层中间段的第一金属层1,如图2所示;
第三步,打线,第二金属线6连接芯片4与联合金属层左段、右段的第一金属层1,如图3所示;
第四步,塑封,塑封体7包围第一金属层1、第二金属层2、芯片4、第一金属线5、第二金属线6,如图4所示;
第五步,去除第三金属层3,如图5所示;
第六步,切割整条产品形成单个单元,如图6所示。
其中,所述第一金属层1材料的硬度比第二金属层2的硬度大。
所述第三金属层3的材料为铜、铁或者其复合金属层。

Claims (5)

1.一种利用金属硬度差优化管脚排布的封装件,其特征在于,所述封装件主要由第一金属层(1)、第二金属层(2)、芯片(4)、第一金属线(5)、第二金属线(6)、塑封体(7)组成,所述第一金属层(1)和第二金属层(2)连接,第一金属层(1)和第二金属层(2)组成的联合金属层分为相互分离的左中右三段,所述芯片(4)与联合金属层中间段的第一金属层(1)连接,第一金属线(5)连接芯片(4)与联合金属层中间段的第一金属层(1),第二金属线(6)连接芯片(4)与联合金属层左段、右段的第一金属层(1),塑封体(7)包围第一金属层(1)、第二金属层(2)、芯片(4)、第一金属线(5)、第二金属线(6);所述第一金属层(1)材料的硬度比第二金属层(2)的硬度大。
2.根据权利要求1所述的一种利用金属硬度差优化管脚排布的封装件,其特征在于,所述第一金属层(1)的材料为银、铜、镍、钯、金或者其复合金属。
3.根据权利要求1所述的一种利用金属硬度差优化管脚排布的封装件,其特征在于,所述第二金属层(2)的材料为锡、锌、铝或者其复合金属。
4.一种利用金属硬度差优化管脚排布的封装件的制造方法,其特征在于,所述方法的具体步骤如下:
第一步,框架制作,依次连接第一金属层(1)、第二金属层(2)、第三金属层(3),将第一金属层(1)和第二金属层(2)组成的联合金属层分为相互分离的左中右三段;
第二步,装片,联合金属层中间段的第一金属层(1)与芯片(4)连接,第一金属线(5)连接芯片(4)与联合金属层中间段的第一金属层(1);
第三步,打线,第二金属线(6)连接芯片(4)与联合金属层左段、右段的第一金属层(1);
第四步,塑封,塑封体(7)包围第一金属层(1)、第二金属层(2)、芯片(4)、第一金属线(5)、第二金属线(6);
第五步,去除第三金属层(3);
第六步,切割整条产品形成单个单元;
其中,所述第一金属层(1)材料的硬度比第二金属层(2)的硬度大。
5.根据权利要求4所述的一种利用金属硬度差优化管脚排布的封装件的制造方法,其特征在于,所述第三金属层(3)的材料为铜、铁或者其复合金属层。
CN201510203312.7A 2015-04-24 2015-04-24 一种利用金属硬度差优化管脚排布的封装件及其制造方法 Pending CN104851866A (zh)

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CN110265377A (zh) * 2018-03-12 2019-09-20 意法半导体股份有限公司 引线框架表面精整
US11735512B2 (en) 2018-12-31 2023-08-22 Stmicroelectronics International N.V. Leadframe with a metal oxide coating and method of forming the same

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