CN104835750A - 用于半导体基板的电镀方法 - Google Patents
用于半导体基板的电镀方法 Download PDFInfo
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- CN104835750A CN104835750A CN201510064920.4A CN201510064920A CN104835750A CN 104835750 A CN104835750 A CN 104835750A CN 201510064920 A CN201510064920 A CN 201510064920A CN 104835750 A CN104835750 A CN 104835750A
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- CSGQJHQYWJLPKY-UHFFFAOYSA-N CITRAZINIC ACID Chemical compound OC(=O)C=1C=C(O)NC(=O)C=1 CSGQJHQYWJLPKY-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 241000500881 Lepisma Species 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000002202 Polyethylene glycol Substances 0.000 description 1
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- 239000000460 chlorine Substances 0.000 description 1
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- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- BSXVKCJAIJZTAV-UHFFFAOYSA-L copper;methanesulfonate Chemical compound [Cu+2].CS([O-])(=O)=O.CS([O-])(=O)=O BSXVKCJAIJZTAV-UHFFFAOYSA-L 0.000 description 1
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- 238000007654 immersion Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
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- 239000012071 phase Substances 0.000 description 1
- 229920001223 polyethylene glycol Polymers 0.000 description 1
- 239000004323 potassium nitrate Substances 0.000 description 1
- 235000010333 potassium nitrate Nutrition 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
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- 239000013049 sediment Substances 0.000 description 1
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- 235000010344 sodium nitrate Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/48—After-treatment of electroplated surfaces
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1689—After-treatment
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- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
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- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- C25F3/00—Electrolytic etching or polishing
- C25F3/02—Etching
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- C25F3/00—Electrolytic etching or polishing
- C25F3/02—Etching
- C25F3/14—Etching locally
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- C25F3/00—Electrolytic etching or polishing
- C25F3/16—Polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
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- Electroplating Methods And Accessories (AREA)
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Abstract
本申请公开了用于半导体基板的电镀方法。对非均匀初始金属膜进行非均匀除镀以在基板上提供更加均匀的金属膜。可通过将基板放置在特定为除镀而非为电镀配制的除镀浴中来执行电化学除镀。除镀浴可具有0.3或更小的均镀能力;或1mS/cm至250mS/cm的浴电导率。通过除镀浴传导的反向电流非均匀地电蚀刻或除镀金属膜。
Description
技术领域
本发明的领域是电镀半导体材料基板或晶片,以及电镀类似类型的基板。
背景技术
电连接的金属化已被广泛用于许多半导体应用,范围从双镶嵌结构到各种封装结构,包括C4凸块(bumping)、柱、微凸起(micro-bump)、再分布层(redistribution layer;RDL)、硅通孔(thru-silicon via;TSV)等。通常使用不同金属(比如铜、金、镍、焊锡和其他金属)的诸如电沉积和无电沉积之类的技术实施这种金属化。随着技术进步,芯片(chip)布局日益具有难以均匀电镀或金属化的特征结构和图案密度。
先进微电子器件封装的电沉积(electro-deposition)经常使用掩模或光刻胶层来界定金属线或触点的图案。所述图案还可以由非反应性或非导电性表面界定。如本文使用的,术语“图案化基板”是指具有掩模或光刻胶层或者非反应性或非导电性区域的基板。图案密度可在稀疏图案化区域与密集图案化区域之间变化。这造成了局部电流密度和离子浓度差的相应变化,从而影响小片(die)内的沉积厚度均匀性(即所谓的小片内非均匀性或WID非均匀性)。
一种用于提高厚度均匀性或厚度调平的技术是整体减小所施加的电流密度。或者,可使用具有高均镀能力的电镀浴。均镀能力可被定义为电镀浴在具有宏观不规则性的阴极上产生差不多均匀厚度的沉积物的能力。均镀能力越高,所得沉积物越均匀。例如,在铜酸浴的情况中,具有高均镀能力的常见浴配方会是具有低铜浓度和高酸浓度的浴。减小高均镀能力浴中的电流密度的另一种替代方案是使用周期性反向电流波形。然而,需要改进的电镀技术。
发明内容
本发明提供用于提高电镀厚度均匀性和平面性的方法。在一个方面中,一种方法包括提供电镀的图案化基板,并随后电蚀刻或除镀所述基板。可通过电镀、无电电镀或通过另一种液相或气相薄膜沉积技术(此处统称为电镀)在基板上形成电镀的图案化基板。除镀步骤使基板不均匀地除镀。除镀浴可具有低均镀能力和或低电导率,以增大稀疏区域中的局部电流密度。除镀步骤可优先从具有较厚初始膜或层的基板区域中去除电镀膜中的一些,以使得在除镀步骤后,基板具有更均匀的沉积金属膜。
附图说明
图1是电镀期间的基板的示意图。
图2是图1所示基板在除镀期间的示意图。
具体实施方式
包括除镀步骤的电镀为人们所熟知。在这些方法中,在电镀工艺期间可周期性地施加反向电流波形,以试图改善电镀结果。对保持在电镀浴中的基板执行除镀,以便使用同一浴电镀和除镀。因此,除镀步骤的均匀性类似于电镀步骤。然而,本案发明人已发现,可通过非均匀除镀获得改善的结果,即通过以非均匀方式和/或以与金属最初如何被电镀到基板上无关的方式从基板去除电镀的金属。
一种典型工艺可包括以下步骤:
提供图案化的电镀基板。所述基板可以是电镀有初始图案化铜膜的硅晶片,然而可使用其他类型的基板和金属。图案化影响电镀期间的电流密度,使得初始电镀膜在一定程度上是非均匀的。例如,初始膜可以是至少3%、5%、8%或10%非均匀的(每三Σ/平均值(per three sigma/mean))。能以各种方式形成初始金属膜,所述方式比如电化学沉积(电镀)、无电沉积、化学或物理气相沉积。
a)将电镀的基板移动到适合于非均匀除镀的除镀浴中。例如,除镀浴可具有低均镀能力,比如小于0.3的均镀能力。或者,除镀浴可具有低电导率,例如,1mS/cm至250mS/cm,或从10mS/cm至100mS/cm。
b)通过传导反向电流穿过基板和浴来在除镀浴中对电镀的基板部分地电蚀刻或除镀。除镀步骤是非均匀的。除镀步骤从突起部分去除金属比从周围区域去除金属更快。从而使得剩余的金属膜更加均匀。初始非均匀性可下降至少30%。使用电镀到300mm硅晶片上的铜的测试数据显示非均匀性下降约60%。此步骤可通过任何形式的电化学去除来执行,比如蚀刻、抛光、炼制、碾磨、粗糙化、光亮化、平滑化、钝化等。
c)可清洗除镀的基板并使除镀的基板干燥,和/或然后移动除镀的基板以用于额外的化学或电化学处理。
此处可互换使用术语“晶片”、“工件”和“基板”。基板可具有各种形状、尺寸和材料。本发明方法可用于电镀铜以及其他金属,比如银、金、镍、钴、钯等。
图案化基板是指具有界定图案的光刻胶或掩模层的基板。或者,图案化基板可以指含有已图案化的结构的基板,比如去除光刻胶后的再分布层或电镀后的硅通孔(TSV)层。虽然在基板上图案化经常是电镀膜非均匀性的来源,但是本发明方法可用于提供更均匀的电镀膜,而不考虑初始电镀膜中非均匀性的来源。
在电镀中获得图案化均匀金属膜的常规途径是使用适当添加剂在高均镀能力浴中电镀基板,并且以适当电流密度操作最佳化波形,以促进小片内图案的稀疏(或隔离)区域和密集区域上的膜厚度均匀性。通常认为低均镀能力是电镀中对于均匀电镀的不良特性。
本发明方法使用不同的途径。在一个实施方式中,可将基板先有意电镀至远高于最终期望或目标厚度的厚度,例如大于目标厚度10%或20%。然后,在低均镀能力或低电导率的除镀浴中除镀基板以获得最终膜厚度和均匀性。除镀浴中的反向极性电流引起优先或选择性金属去除或蚀刻。除镀后的结果是具有改善的均匀性的膜。由于除镀步骤中将使得初始膜更加均匀,因此初始膜的非均匀性便不太关键。因此,可经由高沉积速率快速镀上初始膜。也可以仅使用连续正向电流或在不施加任何反向电流的情况下来镀上初始膜。
在通过电镀施加(apply)金属膜的情况中,电镀浴可适用于快速沉积,而非用于均匀沉积。与除镀浴相比,用于电镀初始膜的浴可以是高均镀能力或高电导率浴,而除镀浴可以是低均镀能力或低电导率浴。
均镀能力被定义为浴在具有宏观不规则性的阴极或阳极上产生或去除差不多均匀厚度沉积物的能力。在数学上,均镀能力可主观地表示为:
均镀能力可受到浴浓度、表面过电势、浴电导率和其他因素的影响。也可以通过改变浴中的添加剂和有机成分的化学特性来改变均镀能力。按照一般规定,我们定义高均镀能力为>0.7;且低均镀能力为<0.3。在一个实施方式中,通过电镀沉积金属膜。在具有高均镀能力(>0.7)的第一浴中执行电镀工艺,但随后在具有低均镀能力(<0.3)的第二浴中处理。
如图1所示,在晶片级封装应用中通过光刻胶电镀的情况中,在电镀浴中电镀基板10(比如半导体晶片)。掩模或光刻胶12在基板上形成图案。浴中的电场线20引发离子(通常为金属离子)沉积到基板上,从而在基板上形成膜或层14。由掩模或光刻胶12形成的图案通常具有多个密集区域16和稀疏(或相对较不密集)区域18。由暴露的基板与基板的掩模面积或掩蔽区域的面积相比的相对面积来确定区域的密度。局部电流分布受局部图案密度影响。以密集封装或更多开口特征结构为特征的较密集区域16具有低电流拥挤,如图1中的区域16处的电场线20所示。以稀疏或更多孤立特征结构为特征的较稀疏区域18具有高电流拥挤,如图1中的区域18处的电场线20所示。由于较密集区域16处的电流拥挤最小,因此在较密集区域16位置处的电镀膜14的厚度T1小于较稀疏区域18中的镀膜22的厚度T2。
如图2所示,除镀也选择性地受到电流拥挤的影响。因此,在除镀期间,较不密集或稀疏区域18中的膜22以比较密集区域16中的膜14更高的速率除镀。在除镀后,膜14和22两者因此更加均匀,接近共同的或期望的均匀厚度T3。
测试表明,这种工艺能将金属膜的WID非均匀性降低60%以上。能通过最优化和改变浴化学品(chemistry)、预处理或后处理和波形来实现进一步改进。
均镀能力可受到浴电导率和沉积动力的影响。酸浓度能用于改变浴电导率,所述电导率随后影响均镀能力。具有低均镀能力的浴可具有低酸浓度。例如,在硫酸的情况中,浓度范围从0g/L至50g/L,更优地从1g/L至25g/L。在另一实施方式中,其他离子(比如金属或简单盐)被用作电荷载体,使得酸浓度可为0g/L。在另一实施方式中,选择浓度以提供1mS/cm至250mS/cm,更优地从10mS/cm至100mS/cm的浴电导率。酸可以硫酸、磷酸、甲磺酸、铬酸等形式呈现。关于pH值,不同酸和不同浓度将影响pH值的操作范围。对于磷酸,pH值可以是约-1.5。对于硫酸,pH值可以从0.3至3.0。pH值还可受到其他电荷载体(比如金属离子)存在的影响。
金属浓度可从0g/L变化至饱和水平。在铜的情况中,铜可以硫酸铜、氧化铜(一价铜或二价铜)、甲磺酸铜等形式呈现。金属离子的浓度能影响浴中的气体逸出和氧化物形成。当然,可使用含有其他金属(比如镍、金、银、铟、钯、钴、铁、锡、锡银、铅锡、其他金属和合金等)的其他金属离子盐溶液。
第二浴可以是酸性或碱性的。出于特定去除目的或标准,除镀浴可配制有各种化学特性,比如粘度、pH值。例如,使用高粘度成分(比如磷酸、硫酸、乙二醇或聚乙二醇)可改变浴的物理特性和化学特性,以抑制不良特性(比如侧壁腐蚀)或以促进理想特性(比如降低表面粗糙度)。可使用其他浴成分:甲磺酸、羟基乙叉二膦酸(HEDP)、三聚磷酸钠(Na5P3O10)、硝酸钠/硝酸钾(NaNO3/KNO3)、硝酸、铬酸、氧化铜、醇等。浴选择也可以是基于金属性质来选择。例如,常规电抛光铌可使用包括氢氟酸的浴。因此,在选择具有理想特性的第二浴后,描述的方法可用于改善特征结构形状、表面形态或纹理。
添加剂可包括在除镀浴中,以改善工艺质量或补充理想化学特性。具体来说,诸如减蚀剂(比如苯并三唑(BTA)及其变体)之类的添加剂可用于最小化金属膜(比如铜)的腐蚀。通常被称为卤素(例如氯)、抑制剂、促进剂、匀平剂(leveler)、阻化剂和增亮剂的常规电镀浴添加剂也可以用于促进理想的膜特性。其他常见电抛光添加剂(比如乙酸、苯甲酸、柠嗪酸、柠檬酸、甘油、乙二醇、醇(比如甲醇、乙醇)、表面活性剂)可用于改善化学特性,比如铜溶解速率、湿润度、pH值稳定性或减少淤渣形成。
电镀速率理论上受到极限电流密度的限制,极限电流密度是所有金属离子进行反应(表面金属浓度是0)的最大电流密度。在极限电流密度以上,可发生除电镀以外的不良工艺。虽然较高电镀速率一般导致较高产量,但是较高电镀速率可带来其他负面影响,比如恶化均匀性。因此,工业生产经常抑制电镀速率以便实现更加均匀的沉积。虽然描述的方法能够实现更加均匀的沉积,但是替代地,作为额外益处,所述方法可用于实现较高整体工艺速率,同时实现相同的膜均匀性。此处的整体工艺速率被定义为最终厚度除以所有工艺时间的和。在这种应用中,即使电镀速率增加可能不利地影响厚度均匀性,但所述电镀速率仍增加。可接着在具有低均镀能力或低电导率的第二浴中处理基板以改善膜均匀性。组合结果是一种实现较高的整体工艺速率和在膜均匀性方面具有减少的不利影响或没有不利影响的工艺。
可配置不同排序(比如电镀,然后除镀,并随后返回重复电镀和/或除镀的循环)作为微调技术。
在除镀期间能应用不同波形,比如反向脉冲或正向脉冲。例如,在除镀期间使用短正向脉冲可暂时反转或减少惰性阴极表面处的气体逸出。正向电流还可以暂时减少出现于基板表面上的金属氧化物。另一示例性正向电流被用于含有金属的电解液中,以沉积金属薄层或改善除镀期间所引入的基板粗糙度。
不同工作循环(duty cycle)和频率的波形也能用于调制边界或阳极层。改变峰值电流密度能用于影响优先蚀刻的程度和所得膜上的晶粒尺寸和表面光洁度。例如,使用相同的浴、基板和安培时间(amp-time),较高电流密度倾向于改善这种选择性。能在电流控制模式、电压控制模式或所述两种模式的组合中施加电流。取决于设置,某些浴选择可用于电流控制模式中的电蚀刻和电压控制模式中的电抛光两者。在一个实施方式中,在使用磷酸的情况下,在直线范围(linear regime)内在电流控制模式中执行电蚀刻,并随后在极限电流范围内在电压控制模式中执行电抛光。
在除镀前或除镀后,所述工艺还可以补充有湿式蚀刻或清洁工艺。在电蚀刻前,可例如通过使用碱性预清洁、弱酸浸泡或清洗或者稀释的表面活性剂清洗来预处理基板。在电蚀刻后,可用碱性或酸性浸泡/清洗来后处理基板。
第二浴可以是单一用途化学品或多用途化学品。也可采用排放与馈给系统来延长浴的使用,以获得较长的浴寿命。
在一个实施方式中,可采用独立反应器腔室,其中第一腔室具有用于电镀金属层的第一浴,且第二腔室具有用于电蚀刻金属层的第二浴。在另一实施方式中,可视情况使用第三浴以便电抛光。在另一实施方式中,可在同一反应器腔室中实施电镀和电蚀刻和/或电抛光,同时通过将第一浴换出,并用第二浴替换第一浴来仍使用多个化学浴。在另一实施方式中,即使在同一腔室内,也可在改变基板位置和/或硬件配置后,将基板暴露于第二浴。
可通过在具有高均镀能力的第一浴(比如用于铜沉积的低铜高酸浴)中进行处理来沉积图案化导电金属膜。按照惯例地,低均镀能力对于均匀电镀并不是理想的浴特性,但由于其他原因或情况低均镀能力可能是理想的,所述其他原因或情况比如允许较高金属浓度或减少对抗蚀剂的酸侵蚀。在一个实施方式中,先在低均镀能力浴中沉积金属膜。随后,将金属膜暴露于用于金属去除工艺的另一低均镀能力浴(不同配方)以实现进一步均匀性改进。
虽然通常将第一浴的化学特性选择为与第二浴的化学特性不同,但是在某些情况下,第一浴和第二浴的化学特性可以是相同的;或者两个浴可以是相同浴。先前实施方式展现了在第一腔室中用第一浴电镀基板,并随后在第二腔室中用第二浴除镀基板。在另一实施方式中,第一浴和第二浴具有相同配方;在独立的第一腔室和第二腔室中执行电镀和除镀。在另一实施方式中,第一浴和第二浴共同是相同的浴;不同之处在于,与另一个浴形成对比,处理或过滤所述第一浴和第二浴中的一个浴,以便限制或去除源自反向极性处理的降解副产物。在另一实施方式中,第一浴和第二浴是相同浴,所述两个浴之间不存在差异。例如,先以低电镀速率电镀基板以促进低应力和均匀沉积,并随后以高除镀速率接着处理基板以改善均匀性。
在电镀中使用的阴极材料可以是可消耗的金属阴极或惰性材料。
所描述的方法还可以通过以适当的电流密度、工艺时间、浴特性进行处理而用于选择性金属去除。在一个实施方式中,可在低酸浴中通过仅增加工艺时间或电流密度来去除比密集区域中的厚度更厚的稀疏区域中的厚度。最终结果是稀疏区域中的厚度变得比密集区域中的厚度更薄;直到在稀疏区域中去除全部厚度。
在电沉积后,硅通孔(TSV)通常可在已填充的通孔上具有突起部分和在需要平坦化或回蚀刻的种晶层顶上具有过量积存。可在从突起部分比从周围区域除镀金属更快的除镀步骤中,通过上文描述的除镀方法减小或去除突起部分。除镀后剩余的更均匀金属膜需要较少化学机械抛光。
在一个实施方式中,在磷酸中电抛光基板以减少过量积存的厚度并增加膜平坦性。除磷酸之外,可使用诸如稀释的磷酸、乙二醇、三聚磷酸钠、硫酸、HEDP、氧化铜或上述物质的组合的其他物质。通过操控电流分布和质量转移,可使用进一步的处理去除金属下种晶和阻挡层。
Claims (16)
1.一种用于处理具有金属膜的基板的方法,所述方法包含:
放置所述基板与导电除镀浴接触;
传导电流穿过所述浴和所述金属膜,以电化学地非均匀地部分除镀所述金属膜,并使得所述金属膜更加均匀。
2.如权利要求1所述的方法,其中通过电化学沉积、无电沉积或通过化学或物理气相沉积将所述金属膜施加到所述基板上。
3.如权利要求1所述的方法,其中通过放置所述基板与电化学沉积浴接触,和通过以与用于电蚀刻所述导电膜的电流极性相反的极性传递电流穿过所述电化学沉积浴来通过电化学沉积施加所述膜。
4.如权利要求3所述的方法,其中所述基板被图案化。
5.如权利要求1所述的方法,其中所述导电除镀浴具有0.3或更小的均镀能力。
6.如权利要求4所述的方法,其中所述导电除镀浴具有在1g/L至25g/L之间的硫酸浓度。
7.如权利要求1所述的方法,其中所述导电除镀浴具有在10mS/cm至100mS/cm之间的电导率。
8.如权利要求1所述的方法,其中所述除镀步骤前的所述金属膜具有至少3%的非均匀性,且其中通过所述除镀步骤将所述非均匀性降低至少30%。
9.一种用于电镀基板的方法,所述方法包含:
放置所述基板与第一浴接触;
以第一极性传导电流穿过所述第一浴,以将初始层沉积到基板上;
放置所述基板与第二浴接触,所述第二浴与所述第一浴不同;和
以与所述第一极性相反的第二极性传导电流穿过所述第二浴以部分地除镀所述初始层。
10.如权利要求9所述的方法,其中所述第二浴具有0.3或更小的均镀能力。
11.如权利要求10所述的方法,其中所述第二浴具有0.3至0.1的均镀能力。
12.如权利要求9所述的方法,其中所述基板被图案化。
13.如权利要求12所述的方法,其中所述第二浴包含低电导率金属盐浴。
14.如权利要求9所述的方法,其中所述初始层具有至少3%的非均匀性。
15.如权利要求12所述的方法,其中所述第二浴具有在1mS/cm至250mS/cm之间的浴电导率。
16.如权利要求9所述的方法,进一步包含:从所述第一浴中取出所述基板,将所述基板暴露于所述第二浴,所述第一浴和所述第二浴皆处于同一处理腔室内。
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KR20150093620A (ko) | 2015-08-18 |
CN104835750B (zh) | 2019-03-08 |
US20150225866A1 (en) | 2015-08-13 |
TW201540877A (zh) | 2015-11-01 |
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