CN104822227B - 嵌入式印刷电路板 - Google Patents

嵌入式印刷电路板 Download PDF

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CN104822227B
CN104822227B CN201510062128.5A CN201510062128A CN104822227B CN 104822227 B CN104822227 B CN 104822227B CN 201510062128 A CN201510062128 A CN 201510062128A CN 104822227 B CN104822227 B CN 104822227B
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printed circuit
circuit board
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insulating substrate
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CN104822227A (zh
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权德淳
南相赫
郑元席
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LG Innotek Co Ltd
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Abstract

提供了一种嵌入式印刷电路板,该嵌入式印刷电路板包括:第一绝缘基板,包括第一腔和第二腔;设置在第一腔中的第一元件;粘合层,用于将第一绝缘基板粘合至第一元件并且包括第一元件所暴露的开口;以及第二绝缘基板,形成第一绝缘基板的下表面的接合层和第二腔的底表面。

Description

嵌入式印刷电路板
技术领域
本发明的实施方式涉及嵌入式印刷电路板。
背景技术
根据便携式终端的各种功能的增加,各种传感器元件已经被添加到便携式终端中。
然而,当将传感器元件安装到包括在便携式终端中的印刷电路板(PCB)时,由于印刷电路板的有限的面积而难以向便携式终端添加新的传感器元件。
同时,印刷电路板(PCB)是由于用导电材料在电绝缘基板上印刷印刷电路而产生的,并且为了在平板上密集地安装许多种元件,印刷电路板被配置成使得确定每个元件的安装位置,并且在平板的表面上印刷并固定连接元件的电路线。
常规的嵌入式印刷电路板被配置成使得在绝缘基板中形成腔,并且将元件安装在腔中。
然而,当常规的嵌入式印刷电路板具有缺陷时,问题在于嵌入的高价元件也要与嵌入式印刷电路板一起被丢弃。
发明内容
本发明的实施方式的一个方面提供了一种嵌入式印刷电路板,其能够通过仅在对应于已完成的正规产品的嵌入式印刷电路板上安装高价元件而不在生产过程期间在嵌入式印刷电路板上安装高价元件,来提高生产收得率并降低生产成本。
本发明的实施方式的另一方面提供了根据各元件的种类和价格的适合的嵌入方法,使得可以以嵌入形式设置多个元件。
根据本发明的实施方式的一个方面,一种嵌入式印刷电路板可以包括:第一绝缘基板,包括安装有第一元件的第一腔;第二腔,与第一腔分离并且被形成为穿过第一绝缘基板;以及第二绝缘基板,形成第二腔的底表面。
特别地,在这样的情况下,第二腔可以具有面对底表面并且是开放的顶表面,并且第二腔可以被形成为具有比第一腔的深度更大的深度。
附图说明
包括附图以提供对本发明的进一步理解,并且附图被并入到本说明书中并且构成本说明书的一部分。附图示出了本发明的示例性实施方式,并且连同说明书一起用于说明本发明的原理。在附图中:
图1至图11是被示出用于说明根据本发明的一个实施方式的嵌入式印刷电路板和制造该嵌入式印刷电路板的方法的视图。
具体实施方式
下文中,将参照附图描述本领域的普通技术人员能够实现的本发明的实施方式。说明书中的实施方式和附图中所示的构造被提供作为本发明的优选实施方式,并且应理解,可以存在能够在提交时替代的各种等同物和变型。此外,当涉及本发明的优选实施方式的操作原理时,在已知功能或功能似乎使本发明的主题内容不清楚的情况下,将从本发明的描述中省略这些功能。考虑到本发明的功能来限定以下术语,并且应通过对本说明书的整体部分进行判断来解释每个术语的含义,并且附图中的具有相似功能和操作的元件被赋予相同的附图标记。除非上下文另有清楚指明,否则如在本文中所使用的,单数形式也意在包括复数形式。
图1至图11是被示出用于说明根据本发明的一个实施方式的嵌入式印刷电路板和制造该嵌入式印刷电路板的方法的视图。
图11是示出了根据本发明的实施方式的嵌入式印刷电路板的结构的截面概念视图。
参照图11,根据本发明的实施方式的嵌入式印刷电路板可以包括:第一绝缘基板100,第一绝缘基板100包括其中安装有第一元件115的第一腔150;第二腔160,第二腔160与第一腔150分离并且被形成为穿过第一绝缘基板100;以及形成第二腔的底表面的第二绝缘基板300。特别地,以下述结构实现第二腔160:其中顶表面是开放的并且底表面由第二绝缘基板支承。通过这样的结构来确认印刷电路板是否符合要求,此后,仅仅关于对应于经测试的合格产品的嵌入式印刷电路板,可以在第二腔中安装高价元件,使得能够提高生产收得率并且能够降低生产成本。特别地,在本发明的实施方式中,嵌入式印刷电路板具有下述结构:其中至少一个导电层x暴露于第二腔160的内侧壁。优点在于该结构能够提高稍后安装元件所需的电信号的传输效率,并且能够消除由于不需要的电信号而产生的噪声。
如图11所示,第二腔160被实现为使得第二腔的面对底表面的顶表面是开放的并且第二腔具有比第一腔150的深度大的深度。特别地,第一腔150被实现为具有比第一绝缘基板的厚度(b)小的深度(a)。安装在第一腔中的第一元件115的厚度也可以被实现为小于第一绝缘基板的厚度。该结构可以被实现为使得能够在第一腔中稳固地嵌入基本感测元件。此外,第一元件115可以是具有感测部117的感测元件。如图11所示,感测部117可以被实现为暴露于外部。另外,根据本发明的实施方式的嵌入式印刷电路板还可以包括在第一绝缘基板上的粘合层114,其中,接合层覆盖第一腔的一部分和第一元件的上部的一部分。粘合层114使得能够在下述区域周围实现具有固定高度和厚度(d)的气体保持空间部从而使得能够提高感测效率:感测部117暴露于该区域。
第二腔160具有比第一腔150的深度(a)大的深度(c)。如图11所示,第二腔160可以被实现为完全穿过第一绝缘基板100以及穿过上部的接合层200。还可以包括暴露于第二腔的底表面的导电图案313,此后,可以将电学元件安装至导电图案。另外,可以在第二腔160的底表面上设置用于保护所安装的电学元件和导电图案的保护层171。
接合层200被设置在第一绝缘基板与第二绝缘基板之间,以将第一绝缘基板接合至第二绝缘基板。在这样的情况下,第二腔可以被实现为穿过接合层。特别地,接合层200可以由具有与第一绝缘基板100的热膨胀系数基本上相同的热膨胀系数的材料制成。这旨在使稍后由热膨胀造成的被接合的层之间的变形最小化。本文中说明的表述“基本上相同”是指由生产工艺或微小的污染源造成的厚度误差,即,在约0.01%的范围内的厚度误差,尽管存在元件的厚度彼此相同的事实。
另外,根据本发明的实施方式的嵌入式印刷电路板还可以包括通孔210和导电电路211,其中,通孔穿过第一绝缘基板和第二绝缘基板。此外,在第二绝缘基板300和第一绝缘基板100的外表面上还包括保护层170,使得能够保护电路。在这种情况下,第二腔的底表面的保护层170和第二绝缘基板的外表面的保护层170可以由相同材料制成。因而,可以在一个工艺中同时进行用于形成保护层的工艺,使得能够简化工艺。
下文中将参照图1至图11来描述根据本发明的一个实施方式制造嵌入式印刷电路板的方法。
如图1所示,制备载板410,在载板410中,在基板111的一个表面和另一表面上形成铜箔层112、113,并且在基板111的所述一个表面上的铜箔层113处形成电路。
此外,在载板410上形成粘合层114,并且通过CO2激光器、YAG激光器、钻孔机或模具冲压法形成开口151。
此时,可以用一个膜形成粘合层114,并且粘合层114的厚度可以在25μm至50μm的范围内。因此,当用一个膜形成粘合层114时,粘合层114可以被均匀地形成,并且可以容易地执行生产工艺。
同时,粘合层114的厚度可以在25μm至50μm的范围内。当粘合层114的厚度小于25μm时,难以确保用于保护传感器元件115的绝缘抵抗性(insulating resistance)。当粘合层114的厚度大于50μm时,问题在于:不管用于传感器元件115的保护的绝缘抵抗性没有额外地得到确保的事实,嵌入式印刷电路板的厚度会不必要地增大。
因此,根据本发明的一个实施方式,粘合层114被形成为具有25μm至50μm的厚度,使得能够确保用于保护传感器元件115的绝缘抵抗性。
然后,如图2所示,在载板410的粘合层114上安装第一元件115。
此时,第一元件115可以是红外线传感器、接近传感器、温度传感器、湿度传感器、气体传感器、图像传感器、RGB传感器以及姿势传感器中的任意一种。
然后,如图3所示,通过使载板410的铜箔层113、粘合层114和第一元件115留在在第一绝缘基板120上,并且通过移除对应于载板410的其余层的基板111和铜箔层112,来形成嵌入式印刷电路板。
更具体地,如图3所示,嵌入式印刷电路可以被配置成使得:在第一绝缘基板120中形成第一腔150,在第一腔150中安装第一元件115,并且还包括导电层116。
此时,可以通过将树脂材料包括在玻璃纤维中来形成第一绝缘基板120。
然后,如图4所示,通过对导电层116进行图案化并且通过进一步形成第二腔160来完成第一层叠部100。此时,第二腔可以利用钻孔机来形成。
如上所述形成的第二腔160是其中设置有元件的空间。当嵌入式印刷电路板作为经测试的合格产品没有缺陷时,可以在第二腔160中设置元件。
之后,如图5所示,利用激光钻孔机在第二绝缘基板311中形成过孔315,通过进行电镀和图案化来形成电镀过孔314和导电层312。然后,形成保护层313,并且通过进行表面处理形成第二层叠部300。
然后,如图6所示,可以形成用于将第一层叠部100接合至第二层叠部300的接合层200。此时,接合层200可以包括开口162。
然后,如图7所示,依次将第一层叠部100、接合层200和第二层叠部300进行层叠。
然后,如图8所示,形成通孔210和过孔171,并且通过进行电镀形成电镀过孔172。如图9所示,形成导电电路211。
此时,通孔210和过孔171可以通过使用激光器进行加工来形成。
此外,如图10所示,通过去除铜箔层113和粘合层114中的每个层的一部分来形成第二腔160。此时,第二腔160可以通过使用激光器进行加工来形成。
然后,如图11所示,可以进一步在嵌入式印刷电路板的两个表面上形成保护层170。
下文中将参照图11来描述根据本发明的一个实施方式的嵌入式印刷电路板的结构。
如图11所示,嵌入式印刷电路板包括:第一绝缘基板120、第一元件115、粘合层114和第二绝缘基板311。
更具体地,根据本发明的一个实施方式的嵌入式印刷电路板可以包括第一层叠部100、接合层200和第二层叠部300。第一层叠部100可以包括第一绝缘基板120、第一元件115、粘合层114和铜箔层113。第二层叠部300可以包括第二绝缘基板311和导电层321。
第一绝缘基板120包括多个腔150、160。
第一元件115设置在多个腔150、160中的第一腔150中。
粘合层114附接至第一绝缘基板120和第一元件115。
此外,粘合层114可以包括开口151,传感器元件115的感测部117暴露于开口151,并且粘合层114可以覆盖第一绝缘基板120和第一元件115的上部。
此时,接合层114的一部分可以形成在第一元件115上。
此外,可以用一个膜形成粘合层114,并且粘合层114的厚度可以在25μm至50μm的范围内。当用一个膜形成粘合层114时,粘合层114可以被均匀地形成,并且还可以简化生产工艺。
同时,粘合层114的厚度可以在25μm至50μm的范围内。当粘合层114的厚度小于25μm时,难以确保用于保护传感器元件115的绝缘抵抗性。当粘合层的厚度大于50μm时,问题在于:不管难以额外地确保用于保护传感器元件115的绝缘抵抗性的事实,印刷电路板的厚度会不必要地增大。
因此,根据本发明的一个实施方式,接合层114被形成为具有25μm至50μm的厚度,使得能够确保用于保护传感器元件115的绝缘抵抗性。
此外,在第一层叠部100中形成第二腔160。
也就是说,在第一层叠部100中所包括的第一绝缘基板120中形成第二腔160,并且包括在第二层叠部300中的第二绝缘基板311形成第二腔160的底表面。
此外,可以进一步包括接合层200,接合层200用于将第一层叠部的第一绝缘基板120接合至第二层叠部300的第二绝缘基板311。接合层200可以包括开口162,其中,开口162可以形成第二腔160。
接合层200将第一层叠部100接合至第二层叠部300。更具体地,接合层可以将第一绝缘基板120接合至第二绝缘基板311。
如上所述配置的嵌入式印刷电路板可以进一步包括在其两个表面上的保护层170。
第二腔160是其中设置有元件的空间。当如上所述配置的嵌入式印刷电路板为没有缺陷的经测试的合格产品时,可以在第二腔160中设置元件。
因此,当常规的嵌入式印刷电路板具有缺陷时,问题在于常规的嵌入式印刷电路板要与高价元件一起被丢弃,但是根据本发明的实施方式,在生产过程期间不将高价元件安装到嵌入式印刷电路板,此后,仅将元件安装到对应于经测试的合格产品的嵌入式印刷电路板中,使得能够提高生产收得率并且能够降低生产成本。
此外,根据本发明的实施方式,可以以嵌入型设置多个元件,并且可以根据各元件的种类和价格提供更适合的嵌入方法。
如上所述,根据本发明的一些实施方式,在生产过程期间不将高价元件安装到嵌入式印刷电路板,此后,仅将元件安装到对应于经测试的合格产品的嵌入式印刷电路板,使得能够提高生产收得率并且能够降低生产成本。因此,可以解决下述问题:当常规的嵌入式电路板具有缺陷时,高价嵌入式元件要与常规的嵌入式电路板一起被丢弃。
此外,根据本发明的一些实施方式,可以以嵌入型设置多个元件,并且可以根据各元件的种类和价格提供更适合的嵌入方法。
如前所述,在本发明的详细描述中,已经描述了本发明的详细示例性实施方式,应明显的是,在不偏离本发明的精神或范围的情况下,技术人员可以做出变型和变化。因此,应当理解的是,前述内容是本发明的说明性内容,并且不应被解释为限于所公开的具体实施方式,以及对所公开的实施方式的变型以及其他实施方式旨在包括在所附权利要求及其等同物的范围之内。

Claims (10)

1.一种嵌入式印刷电路板,包括:
第一绝缘基板,包括安装有第一元件的第一腔;
第二腔,与所述第一腔分离并且被形成为穿过所述第一绝缘基板;
第二绝缘基板,被形成在所述第二腔的底表面上;
在所述第一绝缘基板与所述第二绝缘基板之间的接合层;以及
粘合层,所述粘合层被形成在所述第一绝缘基板上以覆盖所述第一腔的一部分和所述第一元件的上部的一部分;
其中,所述第二腔具有面对所述底表面并且是开放的顶表面,并且所述第二腔的深度大于所述第一腔的深度。
2.根据权利要求1所述的嵌入式印刷电路板,其中,所述粘合层将所述第一绝缘基板附接至所述第一元件,并且包括开口,所述第一元件被暴露到所述开口。
3.根据权利要求2所述的嵌入式印刷电路板,其中,所述第一腔的深度小于所述第一绝缘基板的厚度。
4.根据权利要求3所述的嵌入式印刷电路板,其中,所述第一元件的厚度小于所述第一绝缘基板的厚度。
5.根据权利要求2所述的嵌入式印刷电路板,还包括暴露于所述第二腔的所述底表面的导电图案。
6.根据权利要求2所述的嵌入式印刷电路板,其中,所述开口暴露所述第一元件的感测部。
7.根据权利要求6所述的嵌入式印刷电路板,其中,所述第二腔在结构上被形成为穿过所述接合层。
8.根据权利要求6所述的嵌入式印刷电路板,其中,所述接合层的热膨胀系数与所述第一绝缘基板的热膨胀系数基本上相同。
9.根据权利要求6所述的嵌入式印刷电路板,其中,所述感测部被暴露到的所述开口具有:具有预定深度的气体保持空间部。
10.根据权利要求1所述的嵌入式印刷电路板,其中,所述粘合层的厚度在25μm至50μm的范围内。
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Families Citing this family (8)

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DE102015113324A1 (de) * 2015-08-12 2017-02-16 Schweizer Electronic Ag Leiterstrukturelement mit einlaminiertem Innenlagensubstrat und Verfahren zu dessen Herstellung
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KR102520038B1 (ko) 2018-01-10 2023-04-12 삼성전자주식회사 가스 센서 패키지 및 이를 포함하는 센싱 장치
CN109195315B (zh) * 2018-09-28 2022-01-25 电子科技大学 一种散热结构、埋嵌/贴装印制电路板及制作方法
US11342254B2 (en) * 2020-03-16 2022-05-24 Qualcomm Incorporated Multi-dielectric structure in two-layer embedded trace substrate
EP4017226A4 (en) * 2020-07-07 2023-07-19 Shennan Circuits Co., Ltd. INTEGRATED CIRCUIT CARD AND METHOD OF MANUFACTURING FOR INTEGRATED CIRCUIT CARD
US20220085002A1 (en) 2020-09-16 2022-03-17 Micron Technology, Inc. Circuit board with spaces for embedding components

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102224771A (zh) * 2008-10-31 2011-10-19 太阳诱电株式会社 印刷线路板及其制造方法
US8339796B2 (en) * 2010-09-28 2012-12-25 Samsung Electro-Mechanics, Co., Ltd Embedded printed circuit board and method of manufacturing the same
US8440544B2 (en) * 2010-10-06 2013-05-14 International Business Machines Corporation CMOS structure and method of manufacture

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340713A (ja) * 2004-05-31 2005-12-08 Nec Kansai Ltd マルチチップモジュール
JP4310467B2 (ja) * 2004-10-22 2009-08-12 株式会社村田製作所 複合多層基板及びその製造方法
US7459729B2 (en) * 2006-12-29 2008-12-02 Advanced Chip Engineering Technology, Inc. Semiconductor image device package with die receiving through-hole and method of the same
JP2009010358A (ja) * 2007-05-28 2009-01-15 Panasonic Corp 電子部品内蔵モジュール及びその製造方法
US20130050228A1 (en) * 2011-08-30 2013-02-28 Qualcomm Mems Technologies, Inc. Glass as a substrate material and a final package for mems and ic devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102224771A (zh) * 2008-10-31 2011-10-19 太阳诱电株式会社 印刷线路板及其制造方法
US8339796B2 (en) * 2010-09-28 2012-12-25 Samsung Electro-Mechanics, Co., Ltd Embedded printed circuit board and method of manufacturing the same
US8440544B2 (en) * 2010-10-06 2013-05-14 International Business Machines Corporation CMOS structure and method of manufacture

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