CN104795452A - Schottky rectifier and making method thereof - Google Patents
Schottky rectifier and making method thereof Download PDFInfo
- Publication number
- CN104795452A CN104795452A CN201410020540.6A CN201410020540A CN104795452A CN 104795452 A CN104795452 A CN 104795452A CN 201410020540 A CN201410020540 A CN 201410020540A CN 104795452 A CN104795452 A CN 104795452A
- Authority
- CN
- China
- Prior art keywords
- layer
- groove
- polysilicon
- conductive type
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 89
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 51
- 239000012535 impurity Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims description 83
- 238000007254 oxidation reaction Methods 0.000 claims description 35
- 238000000137 annealing Methods 0.000 claims description 33
- 238000000151 deposition Methods 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 16
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 15
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 13
- 238000002513 implantation Methods 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 150000003608 titanium Chemical class 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 38
- 230000005684 electric field Effects 0.000 abstract description 23
- 230000009471 action Effects 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 11
- 238000005452 bending Methods 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
The invention discloses a Schottky rectifier and a making method thereof. The Schottky rectifier comprises a first conductivity type substrate, a first conductivity type conductive layer formed on the surface of the first conductivity type substrate, at least one trench formed in the first conductivity type conductive layer, side wall oxide layers and bottom oxide layers formed in the trenches, polycrystalline silicon deposited in the trenches and doped with a second conductivity type impurity, and a metal layer formed on the surface of the first conductivity type conductive layer, wherein the doping concentration of the second conductive type impurity changes from high to low from the top to the bottom of the trenches in the depth direction of the trenches. According to the invention, a reverse electric field originally acting on a Schottky barrier quickly leaves a Schottky barrier region and is borne by a depletion layer, so that electric leakage due to original action of the electric field on the Schottky barrier is avoided, and the overall reverse withstand voltage of the device is greatly improved.
Description
Technical field
The present invention relates to a kind of rectifying device and preparation method thereof, particularly relate to a kind of high pressure resistant Schottky rectifier and preparation method thereof.
Background technology
As a kind of the most frequently used semiconductor diode, rectifier diode has unilateral conduction because of it, can resist high voltage withstanding under a reverse bias, thus be widely used in power rectifier, electric current control to, cut the electric equipment products field such as ripple.Along with mobile digital product, as mobile phone, panel computer etc. widely use, low forward voltage drop, and the rectifying device of at a high speed reaction is indispensable parts in these products especially.Schottky diode is a class rectifier diode wherein, and its forward and reverse conversion speed is fast, and forward conduction voltage drop is lower relative to the PN junction of silicon materials, at AC/DC conversion electric power, solar energy is extensively also widely used.
Traditional Schottky rectifying device have employed the mesa technique (structure such as shown in Fig. 1, mark 10 represents N-type substrate, 11 represent N+ doped layer, 12 represent metal), metal (as aluminium, molybdenum) has been bonded Schottky barrier with the silicon materials (as N-type is adulterated) of doping, it has rectification characteristic, and anode is metal, and negative electrode is the semiconductor of doping.Select different metals, different forward voltages can be obtained.Because Schottky junction structure is single charge carrier structure, it is electronics that anode injects the charge carrier of drift region, and there is not minority carrier in drift region, therefore without reverse recovery time, has the advantages such as switching speed is fast and is widely used in high-speed rectifier circuit.But the Schottky barrier of gold half contact is monolateral knot, have also been introduced larger reverse leakage while raising device speed, therefore, traditional schottky is withstand voltage general within hectovolt.Those are needed to the device application of high oppositely withstand voltage and low reverse leakage requirement, traditional schottky obviously cannot meet the demands.
For improving the deficiency that traditional table top Schottky junction structure exists, existing Schottky rectifier introduces MOS(in the industry to the abbreviation of field effect transistor on traditional structure) structure.
In conventional schottky structure, add trench MOS structure, the depletion layer pinch off Schottky barrier district utilizing mos capacitance to produce, the reversed electric field introduction means in Schottky barrier district is inner, to improve the anti-reflective of Schottky to voltage capability.Fig. 2 is the Schottky rectifying device adopting planar technique conceptual design, adds trench MOS structure therein.In Fig. 2,1A is highly doped substrate, and 1B is conductive layer, and metal 1D covers conductive layer 1B and groove 1C region; Metal 1D forms Schottky barrier after contacting with N-type conductive layer 1B, and this part region is Schottky barrier district.MOS structure is made up of metal 1D, groove 1C and N-type conductive layer 1B, and in groove 1C, oxide layer 1G and the doped polycrystalline silicon materials 1H inserted forms the grid of MOS structure, and around Schottky barrier area.Top metal 1D is the anode of Schottky rectifier, and base substrate 1A is negative electrode.When anode 1D adds forward voltage, when namely metal 1D is biased positive voltage, at this moment, MOS structure can not have an impact to Schottky barrier, and Schottky rectifier is forward conduction, has low forward conduction voltage, when anode adds negative voltage, namely during metal 1D negative voltage bias, Schottky barrier is reverse bias, bear reversed electric field, at this moment, mos capacitance will produce depletion layer 1E, this depletion layer raises with reverse voltage to be expanded in conductive layer 1B, finally touch, and expand downwards, by Schottky barrier district pinch off, as shown in Figure 3, at this moment, the reversed electric field in Schottky barrier district is incorporated in the inside of conductive layer 1B by the depletion layer 1E that mos capacitance produces, its effect have adjusted the Electric Field Distribution in MOS groove, reduce the electric field strength of schottky barrier junction, reduce the reverse leakage current of Schottky rectifier on the whole.The reverse voltage of Schottky rectifying device can be accomplished hundreds of volt by this structure, has again less reverse leakage current simultaneously.
Although existing MOS structure Schottky rectifier improves the holding capacity of reverse voltage, but can find out from Fig. 2 and Fig. 3, in reverse-biased situation, the depletion layer 1E that mos capacitance produces produces serious bending 1F at channel bottom, in this bending part reversed electric field high concentration, cause device to shift to an earlier date avalanche breakdown, height cannot be done by withstand voltage.
Improving one's methods of existing MOS structure Schottky rectifier, as shown in Figure 4, for problem as above, existing improving one's methods is that trench design is become structure wide at the top and narrow at the bottom, as can be seen from the structure shown in Fig. 4, width due to groove top is greater than the width of lower trench, namely the inner side bent angle of trench bottom surfaces and side is larger than the inner side bent angle of the groove structure shown in Fig. 3, therefore the depletion layer that mos capacitance produces slows down (representing to mark 2F) in the bending of bottom, and then reduce the electric field strength in this region, this inner angle is larger, and electric field is less.According to the different designs of medial angle, reverse breakdown is withstand voltage can improve 15-40% than the groove structure shown in Fig. 3.The shortcoming of this structure is, it is large that its top dimension must design as far as possible, just can more effectively be slowed down channel bottom electric field.This design is unfavorable for the area reducing device, and in addition, the electric field that bending causes is not eliminated, and still exists.
Summary of the invention
The technical problem to be solved in the present invention is reverse withstand voltage not high enough, defect that reverse leakage is larger in order to overcome Schottky rectifier in prior art, provides a kind of high pressure resistant Schottky rectifier and preparation method thereof.
The present invention solves above-mentioned technical problem by following technical proposals:
A kind of Schottky rectifier, it comprises one first conductivity type substrate, and its feature is, this Schottky rectifier also comprises:
Be formed at first conductive type conduction layer on this first conductivity type substrate surface;
Be formed at least one groove in this first conductive type conduction layer,
Be formed at the sidewall oxide in each groove and bottom oxidization layer, wherein this sidewall oxide is formed on the sidewall of groove, and this bottom oxidization layer is formed at the bottom of groove;
Be deposited on the polysilicon in groove, this polysilicon doping has the second conductive type impurity;
Be formed at the metal level on this first conductive type conduction layer surface,
Wherein, the thickness of this bottom oxidization layer is greater than the thickness of this sidewall oxide, and on the depth direction of groove, from the top of groove to the bottom of groove, in this polysilicon, the doping content of this second conductive type impurity is by high step-down.
In the present invention, in groove, the doping content of the second conductive type impurity of polysilicon is from top to bottom by high step-down, produced by mos capacitance like this, depletion layer (depletion layer between groove) and the trenched side-wall of groove sidepiece are certain angle of inclination, it is wide at the top and narrow at the bottom that (sidewall namely close to the depletion layer distance groove of this metal level is far away, and nearer away from the sidewall of the depletion layer distance groove of this metal level), compared to depletion layer in prior art in the design parallel with groove of groove sidepiece, depletion layer between groove can be made at top (close to the position of metal level, but not away from the position of metal level) touch more fast, down expand rapidly immediately, pinch off Schottky barrier area, the original work reversed electric field be used on Schottky barrier is allowed to speed away Schottky barrier district, born by depletion layer.Because this depletion layer is produced by the Contact of inversion layer and conductive layer (such as P type inversion layer and low-doped N-type conductive layer), its reversed electric field ability to bear is much larger than Schottky barrier, doing so avoids the electric leakage that original electric field action produces on Schottky barrier, the overall oppositely withstand voltage of device is improved greatly.
Preferably, the doping content being arranged in the polysilicon second conduction type impurity at groove top is 3:1 to 1:1 with the ratio of the doping content of the polysilicon second conduction type impurity being arranged in channel bottom.More preferably, the doping content being arranged in the polysilicon second conduction type impurity at groove top is 2.5:1 to 1.5:1 with the ratio of the doping content of the polysilicon second conduction type impurity being arranged in channel bottom.The concentration of polysilicon top to bottom is gradual change by high step-down, and wherein, the polysilicon being positioned at groove top is for close to this metal level polysilicon, and the polysilicon being positioned at channel bottom is the polysilicon close to this bottom oxidization layer.
Preferably, this gash depth is 5:2 to 3:1 with the ratio of the thickness of this bottom oxidization layer.
Preferably, the spacing of adjacent trenches is less than or equal to 2.5 with the ratio of the thickness of this bottom oxidization layer.
Preferably, overlook direction from the first conductive layer, this groove can be designed to the annular closed, and also can be designed to strip-shaped grooves.
Preferably, the doping content of the first conductive type impurity of this first conductivity type substrate is 0.001ohmcm-0.01ohmcm.
Preferably, the doping content of the first conductive type impurity of this first conductive type conduction layer is 0.5ohmcm-3ohmcm.
Preferably, the thickness of this first conductive type conduction layer is 3 μm-15 μm.
Preferably, the width of groove is 0.5 μm-2.5 μm, and gash depth is 1.5 μm-12 μm, and groove pitch is 1.3 μm-10 μm.
Preferably, the thickness of this bottom oxidization layer is 0.5 μm-4 μm.
Preferably, the thickness of this sidewall oxide is 0.5
-5000
.
Preferably, this metal level comprises titanium layer, and/or the thickness of this titanium layer is 0.3 μm-1.0 μm.In the present invention, adopt titanium as schottky metal, Main Function is combined with silicon to form schottky barrier junction.Titanium is adopted to obtain lower forward voltage drop.
A manufacture method for Schottky rectifier, its feature is, comprises the following steps:
The surface of one first conductivity type substrate forms one first conductive type conduction layer;
At least one groove is formed in this first conductive type conduction layer;
Form sidewall oxide and bottom oxidization layer in each trench, wherein this sidewall oxide is formed on the sidewall of groove, and this bottom oxidization layer is formed at the bottom of groove, and the thickness of this bottom oxidization layer is greater than the thickness of this sidewall oxide;
Depositing polysilicon in the trench, and the second conductive type impurity doping is carried out to this polysilicon;
Metal level is formed on the surface in this first conductive type conduction layer,
Wherein, the injection adopting the mode of ion implantation successively to carry out the second conductive type impurity for three times makes on the depth direction of groove, and from the top of groove to the bottom of groove, in this polysilicon, the doping content of this second conductive type impurity is by high step-down.
Preferably, the second conductive type impurity doping of polysilicon comprises the following steps:
Carry out the second conductive type impurity doping with the first injection condition to this polysilicon, and carry out high temperature propelling under the first annealing conditions, wherein this first injection condition is: implantation dosage is 1e13/cm
2-8e13/cm
2, Implantation Energy is 50keV-150keV, and this first annealing conditions is: annealing temperature 950 DEG C-1100 DEG C, and annealing time is 30 minutes-150 minutes;
Complete and with the second injection condition, the second conductive type impurity doping carried out to this polysilicon after ion implantation first, and under the second annealing conditions annealing in process, wherein this second injection condition is: implantation dosage is 1e14/cm
2-9e14/cm
2, Implantation Energy is 35keV-80keV, and this second annealing conditions is: annealing temperature 700-1000 DEG C, and annealing time is 10-60 minute;
With the 3rd injection condition, the second conductive type impurity doping is carried out to this polysilicon after completing twice ion implantation, and under the 3rd annealing conditions annealing in process, wherein the 3rd injection condition is: implantation dosage is 1e15/cm
2-5e15/cm
2, Implantation Energy is 15keV-50keV, and the 3rd annealing conditions is: annealing temperature 500-800 DEG C, and annealing time is 10-60 minute.
In the present invention, in order to be formed from top to bottom, concentration polysilicon doping from high to low, ion implantation first allows Doped ions arrive deep trench bottom for the first time, therefore Implantation Energy is higher, and then will advance for a long time, there is time enough, allow ion infiltrate and go down to channel bottom, certain concentration is not easily too high, the requirement that not so uncontrollable bottom is low-doped.Twice ion implantation afterwards correspondingly requires that concentration is high, energy Ratios first time is little, and the time is corresponding short, prevent ion from down expanding excessively dark, and keep concentration ratio lower trench to want high.Last ion implantation wants concentration the highest, and dosage is maximum, then shortest time (fire of namely backing off is just passable).
Preferably, this bottom oxidization layer is formed by following steps:
Adopt chemical vapor deposition in the trench deposited oxide layer so that trench fill is full;
Adopt dry etching come etching oxidation layer make the thickness of the remaining oxide layer of channel bottom be 0.5 μm-4 μm using as this bottom oxidization layer.
Preferably, this sidewall oxide is formed by following steps:
Adopting thermal oxidation technology to form thickness is on the sidewalls of the trench 0.5
-5000
oxide layer using as this sidewall oxide.
Preferably, polysilicon is filled by following steps:
Employing low pressure chemical phase technique in the trench deposition thickness is that the polysilicon of 1.2 μm-6 μm is to make to fill polysilicon completely in groove, and polysilicon is covered in the surface of this first conductive type conduction layer and exceeds 1 μm-1.5 μm, the surface of this first conductive type conduction layer, wherein deposition temperature is 600 DEG C-640 DEG C, preferably, deposition temperature is 620 DEG C, and deposition time is 60 minutes-240 minutes;
Without residual polycrystalline silicon on the surface that polysilicon on this first conductive type conduction layer surface is etched to make this first conductive type conduction layer by using plasma dry etching completely, namely only have in groove and be filled with polysilicon, and the polysilicon formed on the surface of this first conductive type conduction layer when deposit has all been etched away.After depositing polysilicon, unnecessary polysilicon is etched again after first carrying out ion implantation, can prevent from injecting contamination or damage that cause introduces at polysilicon doped regions through one polysilicon plasma etching, also can prevent on the first conductive layer surface that those do not need to carry out the impact that polysilicon doped regions suffers ion implantation.
Preferably, groove is formed by dry etching.More preferably, the width of groove is 0.5 μm-2.5 μm, and gash depth is 1.5 μm-12 μm, and groove pitch is 1.3 μm-10 μm.
Preferably, adopt chemical vapor deposition to form metal level on the surface in this first conductive type conduction layer, this metal level covers the surface of this first conductive type conduction layer and the surface of polysilicon.Preferably, carry out after completing metal level deposit anneal (annealing here, is the alloy for metal and silicon, forms shallow dissolving each other, and reduces gold-half contact resistance), annealing temperature is 600 DEG C-650 DEG C, and the time is 30-90 second.Preferably, this metal level is titanium layer.Preferably, the thickness of this metal level is 0.3 μm-1.0 μm.
On the basis meeting this area general knowledge, above-mentioned each optimum condition, can combination in any, obtains the preferred embodiments of the invention.
Material therefor of the present invention all commercially.
Positive progressive effect of the present invention is: in the present invention, the doping content of polysilicon in trench-gate is designed to top concentration high, the gradual transition that bottom concentration is low, under grid voltage effect, the depletion layer that mos capacitance produces also forms the pattern that top is wide, bottom is narrow, its effect allows depletion layer when reversed bias voltage effect, accelerates pinch off Schottky barrier district, high electric field is shifted out Schottky barrier district; In the present invention, the introducing of bottom thick oxide layer, the expansion of the depletion layer of mos capacitance can be blocked between the groove in the first conductive layer inner, in conjunction with the depletion layer tilted, Schottky rectifier is when puncturing, its depletion layer can in the linearity being parallel to substrate, and avoid in existing groove MOS Schottky rectifier, depletion layer causes high local fields after expanding to channel bottom.Resulting in a kind of oppositely withstand voltage higher Schottky rectifier.
Accompanying drawing explanation
Fig. 1-4 is the structural representation of the Schottky rectifier of prior art.
Fig. 5 is the structural representation of the Schottky rectifier of one embodiment of the invention.
Fig. 6-9 is the change schematic diagram with voltage of the depletion layer of the Schottky rectifier of one embodiment of the invention.
Figure 10-14 is the processing step schematic diagram of the Schottky rectifier making one embodiment of the invention.
Embodiment
Mode below by embodiment further illustrates the present invention, but does not therefore limit the present invention among described scope of embodiments.The experimental technique of unreceipted actual conditions in the following example, conventionally and condition, or selects according to catalogue.
With reference to figure 5, this Schottky rectifier comprises one first conductivity type substrate 100, and
Be formed at first conductive type conduction layer 101 on this first conductivity type substrate 100 surface;
Be formed at least one groove in this first conductive type conduction layer 101,
Be formed at the sidewall oxide 103 in each groove and bottom oxidization layer 104, wherein this sidewall oxide 103 is formed on the sidewall of groove, and this bottom oxidization layer 104 is formed at the bottom of groove;
Be deposited on the polysilicon 105 in groove, this polysilicon doping has the second conductive type impurity;
Be formed at the titanium layer 106 on this first conductive type conduction layer 101 surface,
Wherein, the thickness of this bottom oxidization layer 104 is greater than the thickness of this sidewall oxide 103, and on the depth direction of groove, from the top of groove to the bottom of groove, in this polysilicon, the doping content of this second conductive type impurity is by high step-down.
Wherein titanium layer 106 is as schottky metal, and this Schottky rectifier also comprises the anode metal layer 107 be formed on titanium layer 106 and the cathode metal layer 108 being formed at this first conductivity type substrate 100 bottom surface.
When metal level applies forward voltage, Schottky barrier is forward bias, is similar to the forward conduction of the whole potential barrier of normal Schottky.When metal level adds reverse voltage, Schottky barrier is reverse-biased, at this moment, MOS structure will have an impact to Schottky barrier district: in groove, be filled with polysilicon, when its upper metal negative voltage bias, to inversion layer be produced in groove periphery, between this inversion layer and the first conductive type conduction layer, produce the dotted line that depletion layer 109(is shown in Fig. 6).When the P type polysilicon (i.e. grid) in groove adulterates from top to down, concentration is reduced by height, electrical potential difference will be caused, namely grid top electromotive force is high, bottom electromotive force is low, indirectly cause the width of peripheral depletion layer to produce difference, its width narrows from the width from top to down gradually (W1>W2 in such as Fig. 6), is deflected condition with groove side.See Fig. 6.
When reverse voltage increases, be positioned at top depletion width and become large, the depletion layer between last two grooves touches mutually, sees Fig. 7; When reverse voltage increases further, expansion is continued in the direction of the depletion layer after touching gradually toward the first conductivity type substrate in the first conductive type conduction layer, until depletion layer is linearly, this straight line is parallel with titanium layer, Fig. 8.When reverse voltage improves further, depletion layer continues will expand downwards, in being bent downwardly state, with reference to figure 9, at this moment, by the reverse withstand voltage design load regulating Schottky rectifier different, adjustment gash depth, channel bottom oxidated layer thickness, numerical value in groove pitch and groove between polysilicon doping concentration, when can realize allowing the depletion layer of expansion in foregoing nearly linearity, device punctures just, Schottky rectifier produces reverse-conducting, as shown in Figure 8.The effect of such design is: when device reverse breakdown, depletion layer is between groove and groove, on channel bottom, eliminate in existing MOS structure Schottky rectifier, the buckling phenomenon that depletion layer is positioned at channel bottom and produces, avoid the high local fields intensity that bending depletion layer produces, prevent under high backward voltage, the electric leakage that high local fields can produce, and device may be caused to puncture in advance, and therefore, MOS structure Schottky rectifier of the present invention, its anti-reflective improves greatly to voltage capability, can meet the demand of high pressure resistant type rectification application.
In the present invention, the effect of certain thickness bottom thick oxide layer is, when reverse bias voltage raises, can stop that depletion layer is toward channel bottom Quick Extended, avoiding depletion layer creates bending around channel bottom, and then cause the electric field concentration phenomenon in this region, also just avoid device and produce electric leakage or puncture in advance.
In the present invention, in groove, doping content is gradual design, its effect is, produced by mos capacitance, the depletion layer of groove sidepiece and groove are skewed, wide at the top and narrow at the bottom, as shown in Figure 6 and Figure 7, compared to depletion layer in prior art in the design parallel with groove of groove sidepiece, the depletion layer between groove can be made to touch more fast at top, down expand rapidly immediately, pinch off Schottky barrier area, namely allow the original work reversed electric field be used on Schottky barrier speed away Schottky barrier district, born by depletion layer.Because this depletion layer is produced by the Contact of such as P type inversion layer and such as low-doped N-type conductive layer, its reversed electric field ability to bear is much larger than Schottky barrier, doing so avoids the electric leakage that original electric field action produces on Schottky barrier, the overall oppositely withstand voltage of device is improved greatly.
With reference to figure 10-14, the manufacture method of this Schottky rectifier, comprises the following steps:
The surface of one first conductivity type substrate 100 forms one first conductive type conduction layer 101;
At least one groove 102 is formed in this first conductive type conduction layer 101;
Form sidewall oxide 103 and bottom oxidization layer 104 in each trench, wherein this sidewall oxide 103 is formed on the sidewall of groove, and this bottom oxidization layer 104 is formed at the bottom of groove, and the thickness of this bottom oxidization layer is greater than the thickness of this sidewall oxide;
Depositing polysilicon 105 in the trench, and the second conductive type impurity doping is carried out to this polysilicon, etch away the unnecessary polysilicon overflowing groove;
Form titanium layer 106 on the surface in this first conductive type conduction layer 101, form anode metal layer 107 and cathode metal layer 108 afterwards again, final Schottky rectifier as shown in Figure 5.
Wherein, the injection adopting the mode of ion implantation successively to carry out the second conductive type impurity for three times makes on the depth direction of groove, and from the top of groove to the bottom of groove, in this polysilicon, the doping content of this second conductive type impurity is by high step-down.
Below with concrete craft embodiment, the manufacture craft of Schottky rectifier of the present invention is described again.
1, in N-type substrate (i.e. the first conductivity type substrate), form N-type epitaxy layer (i.e. the first conductive type conduction layer), N-type substrate is high-concentration dopant, and doping content is 0.005ohmcm, and the doping content of N-type epitaxy layer is 2.0ohmcm, and thickness is 10 μm.
2, in N-type epitaxy layer, technique carries out photoetching routinely, and then use dry etching to form multiple groove, groove width is 2 μm, and gash depth is 8 μm, and groove pitch is 3 μm.
3, use chemical vapor deposition method deposited oxide layer in groove, until groove is filled, then uses the oxide layer in dry etch process etching groove, ensure that bottom thickness is 3 μm; Use thermal oxidation technology, in groove, grow oxide layer, thickness is 1000
, form the gate oxide (i.e. sidewall oxide) of MOS structure.
4, in groove, insert polysilicon, adopt low pressure chemical phase technique depositing polysilicon material, polysilicon deposition thickness is 6 μm, deposition temperature is 620 DEG C, control deposition time, ensure to fill polysilicon completely in groove, and exceed N-type epitaxy layer upper face and be less than 1 μm.
5, utilize ion implantation to carry out the doping of P type to polysilicon, inject and be divided into three times, first time injects: ion is boron, and dosage is 5e13/cm
2, energy is 120keV, carries out high temperature propelling after ion implantation, and temperature is 1000 DEG C of times is 120 minutes; Second time ion implantation is: boron ion, dosage is 8e14/cm
2, energy 60keV, then carry out thermal anneal process, temperature is 900 DEG C, and the time is 60 minutes; Carry out third time ion implantation again, injection condition is: ion is boron fluoride, dosage 5e15/cm
2, energy 30keV, then carry out thermal anneal process, temperature is: 600 DEG C.
6, use dry process to carry out etching polysilicon, removing epi-layer surface polysilicon, retains polysilicon in groove.
7, on epitaxial loayer, chemical vapor deposition method depositing metal titanium is used, deposition thickness 5000
, Titanium covers the polysilicon region of N-type epitaxy layer and groove, and after completing metal level deposit, then carry out thermal annealing, annealing temperature is 625 DEG C, and the time is 40 seconds.
8, on schottky metal, deposit second layer metal, as Schottky rectifier anode, at substrate bottom deposit third layer metal as being Schottky rectifier anode, completes the making (final Schottky rectifier as shown in Figure 5) of Schottky rectifier.
In above-mentioned MOS Schottky rectifier structure, the negative electrode of the substrate connection Schottky rectifier that N-type is highly doped; Substrate is formed first conductive layer (i.e. the first conductive type conduction layer) of N-type doping, schottky metal is formed on the first conductive layer top, this schottky metal is connected to the anode of Schottky rectifier, and this schottky metal and ground floor conductive layer form Schottky barrier; In this first conductive layer, form multiple groove, form bottom thick oxide layer and side thin oxide layer, and insert from top to bottom, the P type polycrystalline silicon material of gradual doping in groove, the oxide layer in groove and doped polycrystalline silicon materials form the grid of MOS structure.When Schottky rectifier reverse bias (cathode bias positive voltage), between groove, mos capacitance produces depletion layer variation with voltage and raises expansion rapidly, and then mutually touch, and continue expansion, last pinch off Schottky barrier district, at this moment, the electric field that reverse bias voltage produces hightails Schottky as barrier region, shift to Schottky rectifier inside, namely the PN junction that electric field is formed by P type inversion layer and the first N-type conductive layer of mos capacitance is born, like this, avoid the low breakdown that Schottky barrier is intrinsic, improve the oppositely withstand voltage of Schottky rectifier.In the present invention, the doping content of polysilicon in trench-gate is designed to top concentration high, the gradual transition that bottom concentration is low, under grid voltage effect, the depletion layer that mos capacitance produces also produces the pattern that top is wide, bottom is narrow as shown in phantom in Figure 6, its effect allows depletion layer when reversed bias voltage effect, accelerates pinch off Schottky barrier district, high electric field is shifted out Schottky barrier district; In the present invention, the introducing of bottom thick oxide layer, the expansion of the depletion layer of mos capacitance can be blocked between the groove in the first conductive layer inner, in conjunction with the depletion layer tilted, Schottky rectifier is when puncturing, its depletion layer can in the linearity being parallel to substrate, and avoid in existing groove MOS Schottky rectifier, depletion layer causes high local fields after expanding to channel bottom.
In the present invention, by adjustment gash depth, ratio between groove pitch and channel bottom thick oxide layer thickness, the gradual doping content parameter of polysilicon gate in adjustment groove, finally can reach following effect: under device applies reverse voltage situation, when Schottky rectifier punctures, depletion layer is extended between the groove of the first conductive layer inside, away from Schottky barrier district, and linearly, produce without high local fields, this design can meet the demand of high-breakdown-voltage parameter.
The MOS structure Schottky diode manufactured and designed by the present invention, it is oppositely withstand voltage can reach 200V-1000V.
In order to clearly illustrate the structures such as each doped region, various oxide layer, polysilicon, the size of the above-mentioned various piece in accompanying drawing is not described in proportion, and those skilled in the art are to be understood that the ratio in accompanying drawing is not limitation of the present invention.In addition, above-mentioned surface and bottom surface, "up" and "down" are also all comparatively speaking, and surperficial, that bottom surface is such statement is for convenience of description, also not should be understood to limitation of the present invention, and those skilled in the art can know understanding principle of the present invention in conjunction with the description of specification and accompanying drawing.
Although the foregoing describe the specific embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, protection scope of the present invention is defined by the appended claims.Those skilled in the art, under the prerequisite not deviating from principle of the present invention and essence, can make various changes or modifications to these execution modes, but these change and amendment all falls into protection scope of the present invention.
Claims (10)
1. a Schottky rectifier, it comprises one first conductivity type substrate, it is characterized in that, this Schottky rectifier also comprises:
Be formed at first conductive type conduction layer on this first conductivity type substrate surface;
Be formed at least one groove in this first conductive type conduction layer,
Be formed at the sidewall oxide in each groove and bottom oxidization layer, wherein this sidewall oxide is formed on the sidewall of groove, and this bottom oxidization layer is formed at the bottom of groove;
Be deposited on the polysilicon in groove, this polysilicon doping has the second conductive type impurity;
Be formed at the metal level on this first conductive type conduction layer surface,
Wherein, the thickness of this bottom oxidization layer is greater than the thickness of this sidewall oxide, and on the depth direction of groove, from the top of groove to the bottom of groove, in this polysilicon, the doping content of this second conductive type impurity is by high step-down.
2. Schottky rectifier as claimed in claim 1, it is characterized in that, the doping content being arranged in the polysilicon second conduction type impurity at groove top is 3:1 to 1:1 with the ratio of the doping content of the polysilicon second conduction type impurity being arranged in channel bottom, the polysilicon top at top is gradual change to the concentration of bottom polysilicon by high step-down, wherein, the polysilicon being positioned at groove top is for close to this metal level polysilicon, and the polysilicon being positioned at channel bottom is the polysilicon close to this bottom oxidization layer;
Preferably, the doping content being arranged in the polysilicon second conduction type impurity at groove top is 2.5:1 to 1.5:1 with the ratio of the doping content of the polysilicon second conduction type impurity being arranged in channel bottom.
3. Schottky rectifier as claimed in claim 1, it is characterized in that, this gash depth is 5:2 to 3:1 with the ratio of the thickness of this bottom oxidization layer;
And/or the spacing of adjacent trenches is less than or equal to 2.5 with the ratio of the thickness of this bottom oxidization layer;
And/or overlook direction from the first conductive layer, this groove is closed annular or strip-shaped grooves.
4. the Schottky rectifier as described in claim 1-3 any one, is characterized in that, the doping content of the first conductive type impurity of this first conductivity type substrate is 0.001ohmcm-0.01ohmcm;
And/or the doping content of the first conductive type impurity of this first conductive type conduction layer is 0.5ohmcm-3ohmcm.
5. the Schottky rectifier as described in claim 1-3 any one, is characterized in that, the thickness of this first conductive type conduction layer is 3 μm-15 μm;
And/or the width of groove is 0.5 μm-2.5 μm, and gash depth is 1.5 μm-12 μm, and groove pitch is 1.3 μm-10 μm;
And/or the thickness of this bottom oxidization layer is 0.5 μm-4 μm;
And/or the thickness of this sidewall oxide is 0.5
-5000
;
And/or this metal level comprises titanium layer;
And/or the thickness of this titanium layer is 0.3 μm-1.0 μm.
6. a manufacture method for Schottky rectifier, is characterized in that, comprises the following steps:
The surface of one first conductivity type substrate forms one first conductive type conduction layer;
At least one groove is formed in this first conductive type conduction layer;
Form sidewall oxide and bottom oxidization layer in each trench, wherein this sidewall oxide is formed on the sidewall of groove, and this bottom oxidization layer is formed at the bottom of groove, and the thickness of this bottom oxidization layer is greater than the thickness of this sidewall oxide;
Depositing polysilicon in the trench, and the second conductive type impurity doping is carried out to this polysilicon;
Metal level is formed on the surface in this first conductive type conduction layer,
Wherein, the injection adopting the mode of ion implantation successively to carry out the second conductive type impurity for three times makes on the depth direction of groove, and from the top of groove to the bottom of groove, in this polysilicon, the doping content of this second conductive type impurity is by high step-down.
7. manufacture method as claimed in claim 6, is characterized in that, the second conductive type impurity doping of polysilicon comprises the following steps:
Carry out the second conductive type impurity doping with the first injection condition to this polysilicon, and carry out high temperature propelling under the first annealing conditions, wherein this first injection condition is: implantation dosage is 1e13/cm
2-8e13/cm
2, Implantation Energy is 50keV-150keV, and this first annealing conditions is: annealing temperature 950 DEG C-1100 DEG C, and annealing time is 30 minutes-150 minutes;
Complete and with the second injection condition, the second conductive type impurity doping carried out to this polysilicon after ion implantation first, and under the second annealing conditions annealing in process, wherein this second injection condition is: implantation dosage is 1e14/cm
2-9e14/cm
2, Implantation Energy is 35keV-80keV, and this second annealing conditions is: annealing temperature 700-1000 DEG C, and annealing time is 10-60 minute;
With the 3rd injection condition, the second conductive type impurity doping is carried out to this polysilicon after completing twice ion implantation, and under the 3rd annealing conditions annealing in process, wherein the 3rd injection condition is: implantation dosage is 1e15/cm
2-5e15/cm
2, Implantation Energy is 15keV-50keV, and the 3rd annealing conditions is: annealing temperature 500-800 DEG C, and annealing time is 10-60 minute.
8. manufacture method as claimed in claim 6, it is characterized in that, this bottom oxidization layer is formed by following steps:
Adopt chemical vapor deposition in the trench deposited oxide layer so that trench fill is full;
Adopt dry etching come etching oxidation layer make the thickness of the remaining oxide layer of channel bottom be 0.5 μm-4 μm using as this bottom oxidization layer;
And/or this sidewall oxide is formed by following steps:
Adopting thermal oxidation technology to form thickness is on the sidewalls of the trench 0.5
-5000
oxide layer using as this sidewall oxide.
9. manufacture method as claimed in claim 6, is characterized in that, fill polysilicon by following steps:
Employing low pressure chemical phase technique in the trench deposition thickness is that the polysilicon of 1.2 μm-6 μm is to make to fill polysilicon completely in groove, and polysilicon is covered in the surface of this first conductive type conduction layer and exceeds 1 μm-1.5 μm, the surface of this first conductive type conduction layer, wherein deposition temperature is 600 DEG C-640 DEG C, preferably, deposition temperature is 620 DEG C, and deposition time is 60 minutes-240 minutes;
Without residual polycrystalline silicon on the surface that polysilicon on this first conductive type conduction layer surface is etched to make this first conductive type conduction layer by using plasma dry etching completely.
10. as the manufacture method in claim 6-9 as described in any one, it is characterized in that, form groove by dry etching;
And/or the width of groove is 0.5 μm-2.5 μm;
And/or gash depth is 1.5 μm-12 μm;
And/or groove pitch is 1.3 μm-10 μm;
And/or adopt chemical vapor deposition to form metal level on the surface in this first conductive type conduction layer, this metal level covers the surface of this first conductive type conduction layer and the surface of polysilicon;
And/or anneal after completing metal level deposit, annealing temperature is 600 DEG C-650 DEG C, the time is 30-90 second;
And/or this metal level is titanium layer;
And/or the thickness of this metal level is 0.3 μm-1.0 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410020540.6A CN104795452B (en) | 2014-01-16 | 2014-01-16 | Schottky rectifier and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410020540.6A CN104795452B (en) | 2014-01-16 | 2014-01-16 | Schottky rectifier and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104795452A true CN104795452A (en) | 2015-07-22 |
| CN104795452B CN104795452B (en) | 2018-04-27 |
Family
ID=53560128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410020540.6A Active CN104795452B (en) | 2014-01-16 | 2014-01-16 | Schottky rectifier and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104795452B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293601A (en) * | 2016-04-12 | 2017-10-24 | 朱江 | A kind of Schottky semiconductor device and preparation method thereof |
| CN107768246A (en) * | 2016-08-18 | 2018-03-06 | 北大方正集团有限公司 | A kind of groove-type Schottky diode and its manufacture method |
| CN108010910A (en) * | 2017-11-21 | 2018-05-08 | 重庆大学 | A kind of groove-shaped Schottky contacts super barrier rectifier and preparation method thereof |
| WO2018103269A1 (en) * | 2016-12-05 | 2018-06-14 | 苏州捷芯威半导体有限公司 | Schottky barrier rectifier |
| CN110729346A (en) * | 2019-09-30 | 2020-01-24 | 东南大学 | Wide bandgap semiconductor rectifier device with low on-resistance and high voltage resistance |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901807A (en) * | 2010-06-23 | 2010-12-01 | 苏州硅能半导体科技股份有限公司 | Channel schottky barrier diode rectifying device and manufacturing method |
| US20120098082A1 (en) * | 2010-10-21 | 2012-04-26 | Vishay General Semiconductor Llc | Schottky rectifier |
| CN103378171A (en) * | 2012-04-28 | 2013-10-30 | 朱江 | Groove Schottky semiconductor device and preparation method thereof |
| CN103390651A (en) * | 2012-05-07 | 2013-11-13 | 朱江 | Groove schottky semiconductor device and manufacturing method thereof |
-
2014
- 2014-01-16 CN CN201410020540.6A patent/CN104795452B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901807A (en) * | 2010-06-23 | 2010-12-01 | 苏州硅能半导体科技股份有限公司 | Channel schottky barrier diode rectifying device and manufacturing method |
| US20120098082A1 (en) * | 2010-10-21 | 2012-04-26 | Vishay General Semiconductor Llc | Schottky rectifier |
| CN103378171A (en) * | 2012-04-28 | 2013-10-30 | 朱江 | Groove Schottky semiconductor device and preparation method thereof |
| CN103390651A (en) * | 2012-05-07 | 2013-11-13 | 朱江 | Groove schottky semiconductor device and manufacturing method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293601A (en) * | 2016-04-12 | 2017-10-24 | 朱江 | A kind of Schottky semiconductor device and preparation method thereof |
| CN107293601B (en) * | 2016-04-12 | 2021-10-22 | 朱江 | Schottky semiconductor device and preparation method thereof |
| CN107768246A (en) * | 2016-08-18 | 2018-03-06 | 北大方正集团有限公司 | A kind of groove-type Schottky diode and its manufacture method |
| WO2018103269A1 (en) * | 2016-12-05 | 2018-06-14 | 苏州捷芯威半导体有限公司 | Schottky barrier rectifier |
| JP2019506740A (en) * | 2016-12-05 | 2019-03-07 | 蘇州捷芯威半導体有限公司Ｇｐｏｗｅｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ，Ｉｎｃ． | Schottky barrier rectifier |
| CN108010910A (en) * | 2017-11-21 | 2018-05-08 | 重庆大学 | A kind of groove-shaped Schottky contacts super barrier rectifier and preparation method thereof |
| CN110729346A (en) * | 2019-09-30 | 2020-01-24 | 东南大学 | Wide bandgap semiconductor rectifier device with low on-resistance and high voltage resistance |
| CN110729346B (en) * | 2019-09-30 | 2023-10-13 | 东南大学 | Wide-forbidden-band semiconductor rectifying device with low on-resistance and high voltage withstand capability |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104795452B (en) | 2018-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5101985B2 (en) | Junction barrier Schottky diode | |
| CN107799587A (en) | A kind of reverse blocking IGBT and its manufacture method | |
| CN104795452A (en) | Schottky rectifier and making method thereof | |
| CN102789979B (en) | Schottky diode and forming method thereof | |
| EP2920816B1 (en) | Method of manufacturing trench-based schottky diode with improved trench protection | |
| CN105810754B (en) | A kind of metal-oxide-semiconductor diode with accumulation layer | |
| CN101800252A (en) | Groove-shaped Schottky barrier rectifier and manufacture method thereof | |
| US9929285B2 (en) | Super-junction schottky diode | |
| CN109509795B (en) | Silicon carbide schottky device with composite groove structure and manufacturing method thereof | |
| CN102969245A (en) | Manufacturing method of reverse-conducting integrated gate-commutated thyristor | |
| US8993426B2 (en) | Semiconductor device with junction termination extension structure on mesa and method of fabricating the same | |
| CN102064201B (en) | Shallow-slot metal oxide semiconductor diode | |
| CN103208529B (en) | Semiconductor diode and the method for forming semiconductor diode | |
| CN116404039B (en) | Power semiconductor device and manufacturing method thereof | |
| CN106129126A (en) | A kind of trench schottky diode and preparation method thereof | |
| US10304971B2 (en) | High speed Schottky rectifier | |
| CN103247538A (en) | Split-gate trench power MOS (Metal Oxide Semiconductor) device integrating schottky | |
| JP5476439B2 (en) | Junction barrier Schottky diode | |
| CN209981225U (en) | Silicon carbide schottky device with composite groove structure | |
| Lee et al. | A novel 4H-SiC Trench MOS Barrier Schottky rectifier fabricated by a two-mask process | |
| CN103594377A (en) | Manufacturing method of integrated Schottky split-gate type power MOS device | |
| CN102456570A (en) | Manufacturing method for schottky diode | |
| CN101707214B (en) | Semiconductor device | |
| Mudholkar et al. | Trench schottky rectifiers with non-uniform trench depths | |
| CN102129988A (en) | Manufacturing method of low-capacitance Schottky diode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |