CN104795353A - Method for making metal interconnect and chip with metal interconnect - Google Patents
Method for making metal interconnect and chip with metal interconnect Download PDFInfo
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- CN104795353A CN104795353A CN201410020498.8A CN201410020498A CN104795353A CN 104795353 A CN104795353 A CN 104795353A CN 201410020498 A CN201410020498 A CN 201410020498A CN 104795353 A CN104795353 A CN 104795353A
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Abstract
The invention discloses a method for making a metal interconnect. The metal interconnect comprises a bonding block area and a metal wire area. The method comprises the following steps: growing a metal layer of which the thickness is a predetermined first thickness on a substrate; etching a metal wire area of the metal layer to make the thickness reduced to a predetermined second thickness; and etching the metal wire area according to a wire pattern to form a metal interconnect. According to the invention, etching of an etching area is easy to implement while the thickness requirement of the metal layer in the bonding block area of the metal interconnect is met. Meanwhile, the invention discloses a chip with a metal interconnect made by the method.
Description
Technical field
The invention belongs to semiconductor chip fabrication process technical field, be specifically related to a kind ofly make the method for metal interconnecting wires and there is the chip of metal interconnecting wires.
Background technology
Routing (Wire Bonding) is also referred to as pressure welding, binding, bonding, wire bond, refer to and use wire (gold thread, aluminum steel etc.), utilize hot pressing or the ultrasonic energy, be bonded on the press welding block of the metal interconnecting wires of substrate, complete the connection of solid-state circuit internal mutual line in semiconductor device, the connection namely between chip and circuit or lead frame.
The development trend of chip package process is, progressively adopts copper cash to do routing wire rod, replaces gold thread in the past and aluminum steel.Mainly because copper cash has low resistivity, high thermal conductivity, cheap etc. a series of advantage.
But copper cash is relative to gold thread and aluminum steel, and its hardness ratio is higher, and is easily oxidized, and when routing, is easily broken by chip pressure welding block.So with copper cash when packaging and routing, also higher to the requirement of chip pressure welding block metal layer thickness, and thicker copper cash, require thicker to the metal layer thickness of press welding block.Existing chip manufacturing process before, the metal layer thickness of press welding block is just difficult to the requirement meeting copper cash routing.If the thickness of metal interconnecting wires on directly simple thickening substrate, then can control to the live width of metal interconnecting wires, etch and bring very large trouble.For same metal interconnected line width/spacing, metal level is thicker, the height of metal interconnecting wires and the ratio of etch areas width larger, the difficulty of metal etch is larger, as shown in Figure 1, for thick metal level, etch the lines of different width, in time needing the regional compare of etching narrow, the sordid situation of easy appearance etching, for the etched area 51 in Fig. 1, etched area 52, etched area 53, size is different, the complexity of etching is different, the size of etched area 53 is maximum, the most easily etch, the size of etched area 52 is minimum, the most difficult etching, just likely there is the sordid situation of etching, affect the quality of chip.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is exactly while the metal layer thickness of the press welding block meeting metal interconnecting wires requires, how to make the etching of etched area be easy to realize.
(2) technical scheme
In order to solve the problems of the technologies described above, according to a first aspect of the invention, the invention provides a kind of method making metal interconnecting wires, metal interconnecting wires comprises press welding block region and metal connecting line region, and the method comprises the following steps:
Step S1: the metal level at Grown thickness being the first predetermined thickness;
Step S2: the metal connecting line region of etching sheet metal, makes its reduced thickness to the second predetermined thickness;
Step S3: etch in metal connecting line region according to line pattern, forms metal interconnecting wires.
Preferably, substrate comprises substrate layer and dielectric layer, and metal level is formed on dielectric layer.
Preferably, step S1 is specially: use high-energy ion bombardment metallic target, metal material is splashed to the forming metal layer on surface of dielectric layer.
Preferably, the material of metal level is Al-Si-Cu alloy, and wherein the content of aluminium is 98.5%, and the content of silicon is 1%, and the content of copper is 0.5%.
Preferably, step S2 is specially: apply photoresist on the metal layer, covers press welding block region with mask, and the photoresist in exposure removing metal connecting line region, then etches metal connecting line region, make its reduced thickness to the second predetermined thickness.
Preferably, described the first predetermined thickness is 1.0-3.0 micron, and the second predetermined thickness is 0.5-0.9 micron.
Preferably, the method for described etching is: adopt certain density corrosive liquid to etch, and controls thinning thickness by controlling etch period.
Preferably, described step S3 is specially: apply photoresist on the metal layer, press welding block region and the metal connecting line region region except etched area is covered according to line pattern mask, the photoresist in metal connecting line region etch district is removed in exposure, then etch away the metal of etched area, form metal interconnecting wires.
Preferably, this chip comprises substrate layer and is positioned at the dielectric layer on substrate layer, dielectric layer also has the metal interconnecting wires that said method makes, wherein metal interconnecting wires comprises press welding block region and metal connecting line region, the metal thickness in press welding block region is the first thickness, the metal thickness in metal connecting line region is the second thickness, and the first thickness is greater than the second thickness.
Preferably, described first thickness is 1.0-3.0 micron, and described second thickness is 0.5-0.9 micron.
(3) beneficial effect
Use method of the present invention to make metal interconnecting wires, first thinning metal connecting line region keep the thickness in press welding block region before etching line, makes the metal level in press welding block region thicker, can meet the needs of routing, prevent the situation breaking press welding block; The metal level in metal connecting line district is thinner, can meet the process requirements of metal etch line, decreases the time of line etching technics and prevents the sordid situation of appearance etching, thus improve the electrical connection properties of metal interconnecting wires.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of the making metal interconnecting wires of prior art;
Fig. 2 is the flow chart of the method making metal interconnecting wires according to an embodiment of the invention;
Fig. 3 is the cross-sectional view of the substrate after growth metal level;
Fig. 4 is by the cross-sectional view of the substrate after thinning for metal connecting line region etch;
Fig. 5 is the cross-sectional view that the substrate of Fig. 4 removes after photoresist.
Fig. 6 is the cross-sectional view of coating photoresist substrate after mask exposure;
Fig. 7 has been the cross-sectional view of the substrate after the etching in metal connecting line region;
Fig. 8 is the cross-sectional view of the chip with the metal interconnecting wires that the inventive method makes;
Embodiment
Below in conjunction with drawings and Examples, embodiments of the present invention are described in further detail.Following examples only for illustration of the present invention, but can not be used for limiting the scope of the invention.
The method making metal interconnecting wires is described below in detail with an embodiment.Fig. 2 shows the overall procedure of the method, and step is as follows:
Step S1: at the metal level of predetermined the first thickness of Grown.As shown in Figure 3, substrate comprises substrate layer 1 and dielectric layer 2, and metal level 3 grows on dielectric layer 2, and dielectric layer is as being silicon dioxide layer.A kind of mode of growing metal layer 3 is use high-energy ion bombardment metallic target, metal material is splashed to the forming metal layer on surface 3 of dielectric layer 2.The modes such as evaporation can certainly be adopted to form metal level 3.The first predetermined thickness refers to the thickness needing setting according to routing, namely can not cause the thickness breaking press welding block during routing, set according to actual conditions.During growing metal layer 3, can reach the first predetermined thickness by the thickness controlling metal level 3 controlling sputtering time, the first thickness is about 1.0-3.0 micron.The material of metal level is preferably Al-Si-Cu alloy, and wherein the content of aluminium is 98.5%, and the content of silicon is 1%, and the content of copper is 0.5%.The silicon adding 1% makes the silicon in aluminium saturated, does not have a large amount of silicon like this enter in aluminium and affect electric conductivity when sputtering.The copper adding 0.5% can reduce electromigration, the extension lead life-span.
Step S2: the metal connecting line region of etching sheet metal, makes its reduced thickness to the second predetermined thickness.A kind of mode applies photoresist 4 on metal level 3; press welding block region 31 is covered with mask plate; the photoresist in exposure removing metal connecting line region 32; then metal connecting line region 32 is etched; make its reduced thickness; and press welding block region 31 can not be etched owing to there being the protection of photoresist, thickness can not change, and the situation of the chip after this step completes as shown in Figure 4.Such as adopt certain density corrosive liquid to etch, reach thinning predetermined thickness by controlling etch period, the second predetermined thickness in general thinning rear metal connecting line district is about 0.5-0.9 micron.Etch the photoresist in rear removing press welding block region, for next step is prepared, as shown in Figure 5.
Step S3: etch in metal connecting line region according to line pattern, forms metal interconnecting wires.A kind of mode applies photoresist 4 on metal level 3, covers press welding block region 31 and metal connecting line region 32 region except etched area with mask, and then the photoresist of the etched area in metal connecting line region 32 is removed in exposure, as shown in Figure 6; Then the metal of etched area is etched away, as shown in Figure 7; After finally removing photoresist, just define chip status as shown in Figure 8, the metal interconnecting wires comprising press welding block region 31 and metal connecting line region 32 completes.
The present invention also proposes a kind of embodiment of chip, as shown in Figure 8, this chip comprises substrate layer 1, the dielectric layer 2 be positioned on substrate layer 1, dielectric layer 2 has by the metal interconnecting wires 3 made by the method for embodiment above, the first thickness D1 in the press welding block region 31 of metal interconnecting wires 3 is greater than the second thickness D2 in metal connecting line region 32.Preferably, the first thickness D1 is 1.0-3.0 micron, and the second thickness D2 is 0.5-0.9 micron, and that is, the first thickness D1 is more than or equal to the twice of the second thickness D2.
Make metal interconnecting wires by method of the present invention, first thinning metal connecting line region keep the thickness in press welding block region before etching line, makes the metal level in press welding block region thicker, can meet the needs of routing, prevent the situation breaking press welding block; The metal level in metal connecting line region is thinner, can meet the process requirements of metal etch line, decreases the time of etching technics and prevents the sordid situation of appearance etching, thus improve the electrical connection properties of metal interconnecting wires.
Above embodiment is only for illustration of the present invention, but not limitation of the present invention.Although with reference to embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, various combination, amendment or equivalent replacement are carried out to technical scheme of the present invention, do not depart from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of claim of the present invention and scope.
Claims (10)
1. make a method for metal interconnecting wires, it is characterized in that, metal interconnecting wires comprises press welding block region and metal connecting line region, and the method comprises the following steps:
Step S1: the metal level at Grown thickness being the first predetermined thickness;
Step S2: the metal connecting line region of etching sheet metal, makes its reduced thickness to the second predetermined thickness;
Step S3: etch in metal connecting line region according to line pattern, forms metal interconnecting wires.
2. method according to claim 1, is characterized in that, substrate comprises substrate layer and dielectric layer, and metal level is formed on dielectric layer.
3. method according to claim 2, is characterized in that, step S1 is specially: use high-energy ion bombardment metallic target, metal material is splashed to the forming metal layer on surface of dielectric layer.
4., according to the method for claims 1 to 3 any one of it, it is characterized in that, the material of metal level is Al-Si-Cu alloy, and wherein the content of aluminium is 98.5%, and the content of silicon is 1%, and the content of copper is 0.5%.
5. according to the method for claims 1 to 3 any one of it, it is characterized in that, step S2 is specially: apply photoresist on the metal layer, press welding block region is covered with mask, the photoresist in exposure removing metal connecting line region, then etch metal connecting line region, make its reduced thickness to the second predetermined thickness.
6., according to the method for claims 1 to 3 any one of it, it is characterized in that, described the first predetermined thickness is 1.0-3.0 micron, and the second predetermined thickness is 0.5-0.9 micron.
7. according to the method for claims 1 to 3 any one of it, it is characterized in that, the method for described etching is: adopt certain density corrosive liquid to etch, and controls thinning thickness by controlling etch period.
8. according to the method for claims 1 to 3 any one of it, it is characterized in that, described step S3 is specially: apply photoresist on the metal layer, press welding block region and the metal connecting line region region except etched area is covered according to line pattern mask, the photoresist in metal connecting line region etch district is removed in exposure, then etch away the metal of etched area, form metal interconnecting wires.
9. a chip, it is characterized in that, this chip comprises substrate layer and is positioned at the dielectric layer on substrate layer, dielectric layer also has the metal interconnecting wires as the method for claim 1-8 any one of it makes, wherein metal interconnecting wires comprises press welding block region and metal connecting line region, the metal thickness in press welding block region is the first thickness, and the metal thickness in metal connecting line region is the second thickness, and the first thickness is greater than the second thickness.
10. chip according to claim 9, is characterized in that, described first thickness is 1.0-3.0 micron, and described second thickness is 0.5-0.9 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410020498.8A CN104795353A (en) | 2014-01-16 | 2014-01-16 | Method for making metal interconnect and chip with metal interconnect |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410020498.8A CN104795353A (en) | 2014-01-16 | 2014-01-16 | Method for making metal interconnect and chip with metal interconnect |
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| CN104795353A true CN104795353A (en) | 2015-07-22 |
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| CN201410020498.8A Pending CN104795353A (en) | 2014-01-16 | 2014-01-16 | Method for making metal interconnect and chip with metal interconnect |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050179068A1 (en) * | 2004-01-23 | 2005-08-18 | Michael Rueb | Integrated semiconductor circuit having a logic and power metallization without intermetal dielectric |
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
| CN103187323A (en) * | 2011-12-28 | 2013-07-03 | 北大方正集团有限公司 | Semiconductor chip and thickening manufacture method of pressure welding block metal layer of semiconductor chip |
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2014
- 2014-01-16 CN CN201410020498.8A patent/CN104795353A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050179068A1 (en) * | 2004-01-23 | 2005-08-18 | Michael Rueb | Integrated semiconductor circuit having a logic and power metallization without intermetal dielectric |
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
| CN103187323A (en) * | 2011-12-28 | 2013-07-03 | 北大方正集团有限公司 | Semiconductor chip and thickening manufacture method of pressure welding block metal layer of semiconductor chip |
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Application publication date: 20150722 |