CN105129725B - Redistribution layer manufacturing method and MEMS (Micro-Electro-Mechanical Systems) device manufacturing method - Google Patents
Redistribution layer manufacturing method and MEMS (Micro-Electro-Mechanical Systems) device manufacturing method Download PDFInfo
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Abstract
The invention provides a redistribution layer manufacturing method and an MEMS (Micro-Electro-Mechanical Systems) device manufacturing method. The redistribution layer manufacturing method comprises the following steps: performing dry etching on a conductive metal layer which is made of Al and the like and is not covered with any photoresist to reduce the conductive metal layer to a certain thickness; and switching to wet etching within Q-Time set in a process in order to remove the residual thickness of the conductive metal layer which is not covered with the photoresist. The etching can well be stopped on the surface of an etching barrier layer. Through the wet etching process, the fence defect of the side wall of the redistribution layer which is subjected to the dry etching is overcome, and over-etching consumption of a top interconnection structure is avoided. Meanwhile, the thickness of the wet etching is small, so that the key size of the redistribution layer which is subjected to the wet etching can fully meet a requirement; the accumulation of a large quantity of etching residues is avoided; the quality of the redistribution layer is ensured; and the device performance is enhanced finally.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of rewiring layer manufacturing method and mems device manufacturing method
Method.
Background technology
MEMS (micro-electro-mechanical systems, abbreviation mems) refers to Micrometer-Nanometer Processing Technology
Make, integrate microsensor, micro partses, micro actuator, signal processing, control circuit etc. microdevice or
System, its manufacture process is with thin film deposition, photoetching, extension, oxidation, diffusion, injection, sputtering, evaporation, etching, scribing and envelope
Dress etc. to manufacture the micro process of Complex Three-Dimensional Body for basic process steps, and size is generally in micron or nanoscale.?
In mems device manufacturing processes, it is connected internally or with external electrical it will usually in mems chip to realize mems device
Upper making of top-level metallic (top metal) reroute layer (redietribution layer, rdl redistribute interconnection layer), lead to
Cross the input/output that rdl layer realizes the signal of mems device, finally make mems play predetermined function.
Rewiring layer formation process of the prior art, usually in the top-level metallic interconnection layer (top of mems wafer
Metal, tm) surface sequentially forms the photoresist layer of etching barrier layer (titanium nitride tin), aluminum al layer and patterning, then adopts
To etch aluminium lamination with dry etch process (refer to Fig. 1 a) or wet-etching technology (refer to Fig. 1 b) and to form rewiring layer,
This rewiring layer can form conductive pad and welded gasket and the line with conductive pad and welded gasket.However, passing through dry etching
When technique directly forms rdl layer, etching be finally difficult to stop at etching barrier layer tin surface, easy over etching and cause tm layer
Loss, simultaneously laterally etched uneven during dry etching, easily form al fence defect (al fence defect)；And lead to
When crossing wet-etching technology and directly forming rdl layer, due to action of gravity, the etching liquid corrosion strength of etching window bottom is larger, holds
The critical size (cd) easily causing bottom al shrinks (shrink), has more residue simultaneously and is gathered in bottom.Obviously, above-mentioned
The reliability of the rewiring layer that dry etching or wet-etching technology are formed is relatively low, the performance of chip of the final encapsulation of impact and good
Rate.
Content of the invention
It is an object of the invention to provide a kind of reroute layer manufacturing method and mems device making method, dry method can be kept away
Etching forms loss and the problem rerouting layer defect itself when rerouting layer to top layer interconnecting metal layer, can also keep away simultaneously
Exempt from wet etching and form the problem that layer critical size shrinks and etch residue is more that reroutes when rerouting layer.
For solving the above problems, the present invention proposes a kind of rewiring layer manufacturing method, comprising:
There is provided semi-conductive substrate, sequentially form on the semiconductor substrate etching barrier layer, conductive metal layer and
The photoresist layer of patterning, the described conductive metal layer of the pattern definition of described photoresist layer forms the position rerouting layer；
With described photoresist layer as mask, using conductive metal layer described in dry etch process partial etching, to reduce
State the thickness of the unlapped conductive metal layer of photoresist layer, and make remaining conductive metal layer remain to cover described etching resistance comprehensively
Barrier；
In the rewiring layer etching processing procedure queue waiting time q-time setting, continue with described photoresist layer for covering
Film, removes the residual thickness of the unlapped conductive metal layer of described photoresist layer, etching stopping completely using wet-etching technology
In described etch stopper layer surface, formed and reroute layer.
Further, it is formed with mems device circuitry and electric connecting point, described rewiring in described Semiconductor substrate
Layer is electrically connected by electric connecting point with described mems device circuitry；Or, in described Semiconductor substrate, it is formed with mems device
Metal interconnection structure above circuit and mems device circuitry, described mems device circuitry pass through metal interconnection structure with described
Reroute layer electrical connection.
Further, described etching barrier layer is titanium nitride or tantalum nitride.
Further, described conductive metal layer is aluminum or copper.
Further, the conductive metal layer thickness being formed on a semiconductor substrate is 1 μm～2 μm, after described dry etching
The residual thickness of conductive metal layer is 0.15 μm～1.25 μm.
Further, described queue waiting time q-time is less than 12 hours, and the time of described wet-etching technology accounts for institute
State the 30%～70% of queue waiting time q-time.
Further, the technological parameter of described dry etching includes: process gas includes cl2、bcl3And n2, source radio frequency work(
Rate is 500w～1500w, and biasing radio-frequency power is 100w～200w, and the process time is 40s～100s；The work of described wet etching
Skill parameter includes: nitric acid 1%～2% volume ratio, phosphoric acid 75%～85% volume ratio, acetic acid 5%～10% volume ratio, water 10%
～20% volume ratio, 25 DEG C～50 DEG C of technological temperature, conductive metal layer etch rate is
The present invention also provides a kind of mems device making method, comprising:
The one mems substrate with mems device circuitry is provided, described mems substrate surface is formed with electric connecting point or
Person's metal interconnection structure；
According to one of above-mentioned method formed on described mems substrate surface rewiring layer, described rewiring layer with described
Electric connecting point or metal interconnection structure electrical connection.
Further, conductive salient point is formed in described rewiring layer surface using plating backflow or laser ball implanting technique.
Further, include in the described step rerouting layer surface formation conductive salient point:
Described rewiring layer surface forms interlayer dielectric layer；
Photoetching simultaneously etches described interlayer dielectric layer, forms conductive trench；
Using conductive trench described in bga process filling, form spherical conductive salient point.
Compared with prior art, the present invention provides rewiring layer manufacturing method and mems device making method, first right
The conductive metal layers such as the unlapped al of photoresist carry out dry etching, are allowed to reduce certain thickness, then in the q- of process set
In the time time, switch to wet etching, the residual thickness of the conductive metal layers such as unlapped for photoresist al is removed completely, etching
Etch stopper layer surface can be stopped at well, this wet etching process eliminates and reroutes layer side wall after dry etching
Fence defect, does not result in the over etching consumption of top layer interconnection structure, simultaneously because the thinner thickness of wet etching, it is possible to
The critical size making the rewiring layer after wet etching is fully achieved requirement, and avoids the accumulation of a large amount of etch residues,
Ensure that the quality rerouting layer, finally improve device performance.
Brief description
Fig. 1 a and Fig. 1 b is the sem of the al rewiring layer being respectively adopted dry etching and wet etching formation in prior art
Figure；
Fig. 2 is the rewiring layer manufacturing method flow chart of the specific embodiment of the invention；
Fig. 3 is the mems device making method flow chart of the specific embodiment of the invention；
Fig. 4 a to 4e is the device architecture profile in manufacture method shown in Fig. 3.
Specific embodiment
The essential core thought of technical solution of the present invention is that existing rewiring layer (rdl) etching processing procedure is divided into two sons
Processing procedure: dry etching and wet etching, and ensure that two sub- processing time sums can be with employing dry method single in prior art
The processing time of etching or wet etching is equal, and after this first dry etching, the method for wet etching not only has concurrently in prior art
Advantage when single employing dry etching or wet etching, and the defect under single lithographic method can also be eliminated.Therein dry
Method etch step can regard main etch step as, and wet etching step can regard over etching step, the work of wet etching as
The skill time not can exceed that the queue waiting time of setting in etching processing procedure, to ensure the etching effect with batch wafer.
For making the purpose of the present invention, feature become apparent, below in conjunction with the accompanying drawings the specific embodiment of the present invention is made
Further instruction, however, the present invention should can simply not be confined to described embodiment to be realized with different forms.
Refer to Fig. 2, the present invention provides a kind of rewiring layer manufacturing method, comprises the following steps:
S21, etching prepares: provides semi-conductive substrate, sequentially forms etching barrier layer on the semiconductor substrate, leads
Metal layer and the photoresist layer of patterning, the described conductive metal layer of the pattern definition of described photoresist layer forms and reroutes
The position of layer；
S22, dry etching: with described photoresist layer as mask, using conductive gold described in dry etch process partial etching
Belong to layer, to reduce the thickness of the unlapped conductive metal layer of described photoresist layer, and so that remaining conductive metal layer is remained to comprehensively
Cover described etching barrier layer；
S23, wet etching: in the rewiring layer etching processing procedure queue waiting time q-time setting, continue with described
Photoresist layer is mask, removes the remaining wall of the unlapped conductive metal layer of described photoresist layer completely using wet-etching technology
Degree, etching stopping, in described etch stopper layer surface, forms and reroutes layer.
Refer to Fig. 3, the present invention also provides a kind of mems device making method, comprising:
S1, provides a mems substrate with mems device circuitry, described mems substrate surface is formed with for being electrically connected
Connect electric connecting point or the metal interconnection structure of mems device circuitry；
S2, the method according to s21 to s23 formed on described mems substrate surface rewiring layer, described rewiring layer with
Described electric connecting point or metal interconnection structure electrical connection；
S3, removes described photoresist layer, forms conductive salient point in described rewiring layer surface.
Refer to Fig. 4 a, in step s1, provide the process of a mems substrate 40 with mems device circuitry to specifically include:
There is provided semi-conductive substrate 400 first, each mems device circuitry 401 is formed on this Semiconductor substrate 400；So
Interlayer dielectric layer 402 on the device surface forming each mems device circuitry 401 afterwards；Afterwards, in interlayer dielectric layer 402
Middle formation metal interconnection structure 403 and electric connecting point 404, or only form metal interconnection structure 403 and electric connecting point 404
One of (for example, conductive plunger, weld pad etc.), therefore top-level metallic tm includes the top layer interconnection metal of metal interconnection structure
And electric connecting point 404 top such as conductive plunger.
The detailed process that step s2 forms rewiring layer 41 on described mems substrate 40 surface includes:
S21, refer to Fig. 4 b, on mems substrate 40 surface being formed with metal interconnection structure 403 or electric connecting point 404
On sequentially form etching barrier layer 411, conductive metal layer 412 and patterning photoresist layer 413, described photoresist layer 413
The described conductive metal layer 412 of pattern definition be used for forming the position rerouting layer 41；Wherein, etching barrier layer 411 be titanium,
Tantalum, titanium nitride or tantalum nitride, described conductive metal layer 412 is one or more of al, cu, ag, au, pt, ni, ti or w,
It is preferably aluminum, thickness is 1 μm～2 μm.
S22, refer to Fig. 4 c, with described photoresist layer 413 as mask, leads using described in dry etch process partial etching
Metal layer 412, to remove the certain thickness of the unlapped conductive metal layer 412 of described photoresist layer 413, but remaining conduction
Metal level 412 remains to cover described etching barrier layer 411 comprehensively.This dry etching process can regard the master of conductive metal layer as
Etching process, it is therefore an objective to remove the conductive metal layer 412 of the certain thickness (being preferably more than half) that photoresist layer exposes, reduces
The conductive metal layer thickness of subsequent wet etching, can avoid the dry etching method settling at one go in prior art to bring simultaneously
Fence defect and the loss to top-level metallic, provide good process window for subsequent wet etching, reduce subsequent wet
The process time of corrosion and residue defect.Wherein, the parameter that described dry etching can be commonly used using industry, for example: work
Skill pressure is 5mtorr～15mtorr, chlorine cl2Flow is 50sccm～100sccm, bcl3Flow be 50sccm～
100sccm, nitrogen n2Flow is 3sccm～10sccm, and source radio-frequency power is 500w～1500w, and biasing radio-frequency power is 100w
～200w, the process time is 40s～100s, the residue of the unlapped conductive metal layer 412 of photoresist layer 413 after dry etching
Thickness is [0.2 μm +/- 0.05 μm]～[1.2 μm +/- 0.05 μm], that is, 0.15 μm～1.25 μm.According to different requirement on devices,
The residual thickness of the unlapped conductive metal layer 412 of photoresist layer 413 after dry etching can suitably change, and now dry method is carved
The technological parameter of erosion can require to carry out accommodation according to residual thickness.The work being selected according to technological requirement in the present embodiment
Skill parameter is as follows: process pressure is 10mtorr, chlorine cl2Flow is 70sccm, bcl3Flow is 60sccm, nitrogen n2Flow is
5sccm source radio-frequency power is 900w, and biasing radio-frequency power is 150w, and the process time is 60s, the photoresist layer after dry etching
The residual thickness of 413 unlapped conductive metal layers 412 is 0.2 μm.
S23, refer to Fig. 4 d, with described photoresist layer 413 as mask, continues etching using wet-etching technology remaining
Conductive metal layer 412, etching stopping, on described etching barrier layer 411 surface, is not covered with removing described photoresist layer 413 completely
Conductive metal layer 412, formed and reroute layer 41, wherein, described wet etching needs in the rewiring layer etching processing procedure requiring
Queue waiting time q-time in carry out and complete it can be understood as: on production line the rewiring layer of previous wafer manufacture into
Row in wet etching process, the rewiring layer manufacture of a wafer afterwards carries out in dry etching process, therefore previous wafer wet
Method etch period not can exceed that the dry etching time of a rear wafer, and after thereby guaranteeing that, the dry etching process of a wafer will not go out
Existing over etching, is provided with queue waiting time q-time, the process time of wet etching not can exceed that queuing of setting etc. for this
Treat time q-time, thereby guarantee that the quality of the rewiring layer ultimately forming.In the present embodiment, described wet-etching technology when
Between account for the 30%～70% of described queue waiting time q-time.The technological parameter of described wet etching includes: nitric acid 1%～
2% volume ratio, phosphoric acid 75%～85% volume ratio, acetic acid 5%～10% volume ratio, water 10%～20% volume ratio, process warm
Spend 25 DEG C～50 DEG C, conductive metal layer etch rate is Conduction due to wet etching
Metal level is thinning, and the therefore process time shortens, and etching can stop at etch stopper layer surface well, removes dry method quick
After etching while remaining conductive metal layer, not only do not result in conductive metal layer and the critical size of top-level metallic is obvious
Reduce, and the fence defect of dry etching formation can also be eliminated, it is to avoid produce a large amount of wet etching residues, thereby ensure that
Reroute the quality of layer, finally improve device performance.
Refer to Fig. 4 e, in step s3, ash is carried out using the technological temperature higher than 200 DEG C, oxygen, fluorine hybrid technique gas
Change is processed, to remove photoresist layer 413.Further, to the mems device to manufacture on the basis of the rewiring layer 41 exposing
Part is packaged, and specifically, forms a strata acid imide (polyimide-pi) or epoxy resin rerouting layer 41 surface
Etc. (epoxy) interlayer dielectric layer of material, forms bga conductive trench using photoetching, etching technics in interlayer dielectric layer；Using
Bga process filling bga conductive trench, forms bga stannum ball as conductive salient point 42.In other embodiments of the invention, permissible
Conductive salient point is formed in described rewiring layer surface using plating backflow or laser ball implanting technique.
In sum, the present invention provides rewiring layer manufacturing method and mems chip packaging method, first to photoresist
The conductive metal layers such as unlapped al carry out dry etching, are allowed to reduce certain thickness, then in the q-time of process set
Interior, switch to wet etching, the residual thickness of the conductive metal layers such as unlapped for photoresist al is removed completely, etching can be very
Stop at well etch stopper layer surface, the fence rerouting layer side wall after this wet etching process eliminates dry etching lacks
Fall into, do not result in the over etching consumption of top layer interconnection structure, simultaneously because the thinner thickness of wet etching, it is possible to making wet
The critical size of the rewiring layer after method etching is fully achieved requirement, and avoid a large amount of etch residues accumulation it is ensured that
Reroute the quality of layer, finally improve device performance.
Obviously, those skilled in the art can carry out the various changes and modification spirit without deviating from the present invention to invention
And scope.So, if these modifications of the present invention and modification belong to the claims in the present invention and its equivalent technologies scope it
Interior, then the present invention is also intended to comprise these changes and modification.
Claims (10)
1. a kind of rewiring layer manufacturing method is it is characterised in that include:
Semi-conductive substrate is provided, sequentially forms etching barrier layer, conductive metal layer and pattern on the semiconductor substrate
The photoresist layer changed, the described conductive metal layer of the pattern definition of described photoresist layer forms the position rerouting layer；
With described photoresist layer as mask, using conductive metal layer described in dry etch process partial etching, to reduce described light
The thickness of the unlapped conductive metal layer of photoresist layer, and make remaining conductive metal layer remain to cover described etch stopper comprehensively
Layer；
In the rewiring layer etching processing procedure queue waiting time q-time setting, continue with described photoresist layer as mask, adopt
Remove the residual thickness of the unlapped conductive metal layer of described photoresist layer with wet-etching technology completely, etching stopping is described
Etch stopper layer surface, forms and reroutes layer.
2. rewiring layer manufacturing method as claimed in claim 1 is it is characterised in that be formed with mems in described Semiconductor substrate
Device circuitry and electric connecting point, described rewiring layer is electrically connected by electric connecting point with described mems device circuitry；Or
Person, is formed with the metal interconnection structure above mems device circuitry and mems device circuitry in described Semiconductor substrate, described
Mems device circuitry passes through metal interconnection structure and described rewiring layer electrical connection.
3. as claimed in claim 1 rewiring layer manufacturing method it is characterised in that described etching barrier layer be titanium nitride or
Tantalum nitride.
4. as claimed in claim 1 rewiring layer manufacturing method it is characterised in that described conductive metal layer be aluminum, aluminium alloy,
Copper or copper alloy.
5. as claimed in claim 1 reroute layer manufacturing method it is characterised in that the conductive gold that formed on a semiconductor substrate
Belong to thickness degree and be 1 μm～2 μm, after described dry etching, the residual thickness of conductive metal layer is 0.15 μm～1.25 μm.
6. rewiring layer manufacturing method as claimed in claim 1 is it is characterised in that described queue waiting time q-time is less than
12 hours, the time of described wet-etching technology accounted for the 30%～70% of described queue waiting time q-time.
7. rewiring layer manufacturing method as claimed in claim 1 is it is characterised in that the technological parameter bag of described dry etching
Include: process gas includes cl2、bcl3And n2, source radio-frequency power is 500w～1500w, and biasing radio-frequency power is 100w～200w,
Process time is 40s～80s；The technological parameter of described wet etching includes: nitric acid 1%～2% volume ratio, and phosphoric acid 75%～
85% volume ratio, acetic acid 5%～10% volume ratio, water 10%～20% volume ratio, 25 DEG C～50 DEG C of technological temperature, conducting metal
Layer etch rate be
8. a kind of mems device making method is it is characterised in that include:
The one mems substrate with mems device circuitry is provided, described mems substrate surface is formed with electric connecting point or gold
Belong to interconnection structure；
According to the rewiring layer manufacturing method any one of claim 1 to 7, weight is formed on described mems substrate surface
Wiring layer, described rewiring layer and described electric connecting point or metal interconnection structure electrical connection.
9. mems device making method as claimed in claim 8 is it is characterised in that flowed back or laser ball implanting work using plating
Skill forms conductive salient point in described rewiring layer surface.
10. mems device making method as claimed in claim 9 is led it is characterised in that being formed in described rewiring layer surface
The step of electric salient point includes:
Described rewiring layer surface forms interlayer dielectric layer；
Photoetching simultaneously etches described interlayer dielectric layer, forms conductive trench；
Using conductive trench described in bga process filling, form spherical conductive salient point.
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