CN105129725A - Redistribution layer manufacturing method and MEMS (Micro-Electro-Mechanical Systems) device manufacturing method - Google Patents
Redistribution layer manufacturing method and MEMS (Micro-Electro-Mechanical Systems) device manufacturing method Download PDFInfo
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- CN105129725A CN105129725A CN201510490474.3A CN201510490474A CN105129725A CN 105129725 A CN105129725 A CN 105129725A CN 201510490474 A CN201510490474 A CN 201510490474A CN 105129725 A CN105129725 A CN 105129725A
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Abstract
The invention provides a redistribution layer manufacturing method and an MEMS (Micro-Electro-Mechanical Systems) device manufacturing method. The redistribution layer manufacturing method comprises the following steps: performing dry etching on a conductive metal layer which is made of Al and the like and is not covered with any photoresist to reduce the conductive metal layer to a certain thickness; and switching to wet etching within Q-Time set in a process in order to remove the residual thickness of the conductive metal layer which is not covered with the photoresist. The etching can well be stopped on the surface of an etching barrier layer. Through the wet etching process, the fence defect of the side wall of the redistribution layer which is subjected to the dry etching is overcome, and over-etching consumption of a top interconnection structure is avoided. Meanwhile, the thickness of the wet etching is small, so that the key size of the redistribution layer which is subjected to the wet etching can fully meet a requirement; the accumulation of a large quantity of etching residues is avoided; the quality of the redistribution layer is ensured; and the device performance is enhanced finally.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to one and to reroute layer manufacturing method and MEMS manufacture method.
Background technology
MEMS (Micro-Electro-MechanicalSystems, be called for short MEMS) refer to what Micrometer-Nanometer Processing Technology made, integrate microdevice or the system of microsensor, micro parts, micro actuator, signal transacting, control circuit etc., its manufacture process is that size is usually at micron or nanoscale with thin film deposition, photoetching, extension, oxidation, diffusion, injection, sputtering, evaporation, etching, scribing and encapsulation etc. for basic process steps is to manufacture the micro Process process of Complex Three-Dimensional Body.In MEMS manufacture process; in order to realize MEMS inner or be connected with external electrical; usual meeting to be rerouted layer (RedietributionLayer in the upper making of the top-level metallic (topmetal) of MEMS chip; RDL; distribution interconnect layer again); realized the I/O of the signal of MEMS by RDL layer, finally make MEMS play predetermined function.
The layer formation process that reroutes of the prior art, generally the top-level metallic interconnection layer (topmetal in MEMS wafer, TM) surface forms the photoresist layer of etching barrier layer (titanium nitride TiN), aluminium Al layer and patterning successively, then adopt dry etch process (please refer to Figure 1A) or wet-etching technology (please refer to Figure 1B) to etch aluminium lamination to form the layer that reroutes, this layer that reroutes can form conductive pad and welded gasket and the line with conductive pad and welded gasket.But, when directly forming RDL layer by dry etch process, etching is finally difficult to stop at etching barrier layer TiN surface, easy over etching and cause the loss of TM layer, side direction etching simultaneously during dry etching is uneven, easily forms Al fence defect (Alfencedefect); And when directly forming RDL layer by wet-etching technology, due to Action of Gravity Field, etching liquid corrosion strength bottom etching window is comparatively large, easily causes the critical size (CD) of bottom Al to shrink (shrink), has more residue simultaneously and be gathered in bottom.Obviously, the reliability of the layer that reroutes that above-mentioned dry etching or wet-etching technology are formed is lower, the performance of the chip of the final encapsulation of impact and yield.
Summary of the invention
One is the object of the present invention is to provide to reroute layer manufacturing method and MEMS manufacture method, can keep away dry etching is formed to the loss of top layer interconnecting metal layer and the problem of the defect of the layer that reroutes own when to reroute layer, and reroute when wet etching can also be avoided to be formed reroute layer layer critical size contraction and the more problem of etch residue simultaneously.
For solving the problem, the present invention proposes one and to reroute layer manufacturing method, comprising:
There is provided semi-conductive substrate, form the photoresist layer of etching barrier layer, conductive metal layer and patterning on the semiconductor substrate successively, the described conductive metal layer of the pattern definition of described photoresist layer forms the position of the layer that reroutes;
With described photoresist layer for mask, adopt conductive metal layer described in dry etch process partial etching, to reduce the thickness of the unlapped conductive metal layer of described photoresist layer, and make remaining conductive metal layer still can cover described etching barrier layer comprehensively;
Etch in processing procedure queue waiting time Q-time at the layer that reroutes of setting, continue with described photoresist layer as mask, adopt wet-etching technology to remove the residual thickness of the unlapped conductive metal layer of described photoresist layer completely, etching stopping, on described etching barrier layer surface, forms the layer that reroutes.
Further, in described Semiconductor substrate, be formed with MEMS circuit and electric connecting point, described in the layer that reroutes be electrically connected by electric connecting point with described MEMS circuit; Or be formed with the metal interconnect structure above MEMS circuit and MEMS circuit in described Semiconductor substrate, described MEMS circuit is electrically connected by metal interconnect structure and the described layer that reroutes.
Further, described etching barrier layer is titanium nitride or tantalum nitride.
Further, described conductive metal layer is aluminium or copper.
Further, the conducting metal layer thickness formed on a semiconductor substrate is 1 μm ~ 2 μm, and after described dry etching, the residual thickness of conductive metal layer is 0.15 μm ~ 1.25 μm.
Further, described queue waiting time Q-time is less than 12 hours, and the time of described wet-etching technology accounts for 30% ~ 70% of described queue waiting time Q-time.
Further, the technological parameter of described dry etching comprises: process gas comprises Cl
2, BCl
3and N
2, source radio-frequency power is 500W ~ 1500W, and biased radio-frequency power is 100W ~ 200W, and the process time is 40s ~ 100s; The technological parameter of described wet etching comprises: nitric acid 1% ~ 2% volume ratio, phosphoric acid 75% ~ 85% volume ratio, acetic acid 5% ~ 10% volume ratio, water 10% ~ 20% volume ratio, and technological temperature 25 DEG C ~ 50 DEG C, conductive metal layer etch rate is
The present invention also provides a kind of MEMS manufacture method, comprising:
The MEMS substrate that one has a MEMS circuit is provided, described MEMS substrate surface is formed with electric connecting point or metal interconnect structure;
On described MEMS substrate surface, form the layer that reroutes according to one of above-mentioned method, described in reroute layer and described electric connecting point or metal interconnect structure be electrically connected.
Further, plating backflow or laser ball implanting technique is adopted to form conductive salient point on described layer surface of rerouting.
Further, the step forming conductive salient point on described layer surface of rerouting comprises:
Interlayer dielectric layer is formed on the surface at the described layer that reroutes;
Photoetching also etches described interlayer dielectric layer, forms conductive trench;
Adopt conductive trench described in BGA process filling, form spherical conductive salient point.
Compared with prior art, layer manufacturing method and the MEMS manufacture method of rerouting provided by the invention, first dry etching is carried out to conductive metal layers such as the unlapped Al of photoresist, make it to reduce certain thickness, then within the Q-Time time of process set, transfer wet etching to, the residual thickness of the conductive metal layers such as the unlapped Al of photoresist is removed completely, etching can stop at etching barrier layer surface well, the fence defect of layer sidewall that reroute after this wet etching process eliminates dry etching, the over etching consumption of top layer interconnection structure can not be caused, simultaneously due to the thinner thickness of wet etching, so the critical size of the layer that reroutes after wet etching can be made to reach requirement completely, and avoid the accumulation of a large amount of etch residue, ensure that the quality of the layer that reroutes, finally improve device performance.
Accompanying drawing explanation
Figure 1A and Figure 1B is that the Al adopting dry etching and wet etching to be formed in prior art respectively reroutes the SEM figure of layer;
Fig. 2 is the layer manufacturing method flow chart that reroutes of the specific embodiment of the invention;
Fig. 3 is the MEMS manufacture method flow chart of the specific embodiment of the invention;
Fig. 4 A to 4E is the device architecture profile in manufacture method shown in Fig. 3.
Detailed description of the invention
The essential core thought of technical solution of the present invention the existing layer that reroutes (RDL) is etched processing procedure be divided into two sub-processing procedures: dry etching and wet etching, and ensure that two sub-processing time sums can be equal with the processing time of employing dry etching single in prior art or wet etching, the advantage when method of wet etching not only has single employing dry etching or wet etching in prior art concurrently after this first dry etching, and the defect under single lithographic method can also be eliminated.Dry etch step wherein can regard main etch step as, and wet etching step can regard over etching step as, and the process time of wet etching can not exceed the queue waiting time arranged in etching processing procedure, to ensure the etching effect with batch wafer.
For making object of the present invention, feature becomes apparent, and be further described, but the present invention can realize by different forms, should just not be confined to described embodiment below in conjunction with accompanying drawing to the specific embodiment of the present invention.
Please refer to Fig. 2, the invention provides one and to reroute layer manufacturing method, comprise the following steps:
S21, etching prepares: provide semi-conductive substrate, form the photoresist layer of etching barrier layer, conductive metal layer and patterning on the semiconductor substrate successively, and the described conductive metal layer of the pattern definition of described photoresist layer forms the position of the layer that reroutes;
S22, dry etching: with described photoresist layer for mask, adopt conductive metal layer described in dry etch process partial etching, to reduce the thickness of the unlapped conductive metal layer of described photoresist layer, and make remaining conductive metal layer still can cover described etching barrier layer comprehensively;
S23, wet etching: etch in processing procedure queue waiting time Q-time at the layer that reroutes of setting, continue with described photoresist layer as mask, wet-etching technology is adopted to remove the residual thickness of the unlapped conductive metal layer of described photoresist layer completely, etching stopping, on described etching barrier layer surface, forms the layer that reroutes.
Please refer to Fig. 3, the present invention also provides a kind of MEMS manufacture method, comprising:
S1, providing the MEMS substrate that has a MEMS circuit, described MEMS substrate surface being formed with the electric connecting point for being electrically connected MEMS circuit or metal interconnect structure;
S2, forms the layer that reroutes according to the method for S21 to S23 on described MEMS substrate surface, described in reroute layer and described electric connecting point or metal interconnect structure be electrically connected;
S3, removes described photoresist layer, forms conductive salient point on described layer surface of rerouting.
Please refer to Fig. 4 A, in step S1, provide a process with the MEMS substrate 40 of MEMS circuit specifically to comprise:
First semi-conductive substrate 400 is provided, this Semiconductor substrate 400 is formed each MEMS circuit 401; Then interlayer dielectric layer 402 on the device surface forming each MEMS circuit 401; Afterwards, metal interconnect structure 403 and electric connecting point 404 is formed in interlayer dielectric layer 402, or the one only formed in metal interconnect structure 403 and electric connecting point 404 (being such as conductive plunger, weld pad etc.), therefore top-level metallic TM comprises electric connecting point 404 tops such as the top layer interconnecting metal of metal interconnect structure and conductive plunger.
The detailed process that step S2 forms at described MEMS substrate 40 layer 41 that reroutes on the surface comprises:
S21, please refer to Fig. 4 B, the photoresist layer 413 of etching barrier layer 411, conductive metal layer 412 and patterning is formed on the surface successively, the pattern definition of described photoresist layer 413 position of described conductive metal layer 412 for the formation of the layer 41 that reroutes at the MEMS substrate 40 being formed with metal interconnect structure 403 or electric connecting point 404; Wherein, etching barrier layer 411 is titanium, tantalum, titanium nitride or tantalum nitride, and described conductive metal layer 412 is one or more in Al, Cu, Ag, Au, Pt, Ni, Ti or W, and be preferably aluminium, thickness is 1 μm ~ 2 μm.
S22, please refer to Fig. 4 C, with described photoresist layer 413 for mask, adopt conductive metal layer 412 described in dry etch process partial etching, to remove the certain thickness of the unlapped conductive metal layer 412 of described photoresist layer 413, but remaining conductive metal layer 412 still can cover described etching barrier layer 411 comprehensively.This dry etching process can regard the main etching process of conductive metal layer as, object removes the conductive metal layer 412 of the certain thickness (preferably over half) that photoresist layer exposes, reduce the conducting metal layer thickness of subsequent wet etching, the fence the defect simultaneously dry etching method settled at one go in prior art can being avoided to bring and the loss to top-level metallic, for subsequent wet etching provides good process window, reduce process time and the residue defect of subsequent wet corrosion.Wherein, the parameter that described dry etching can adopt industry conventional, such as, be: process pressure is 5mtorr ~ 15mtorr, chlorine Cl
2flow is 50sccm ~ 100sccm, BCl
3flow is 50sccm ~ 100sccm, nitrogen N
2flow is 3sccm ~ 10sccm, source radio-frequency power is 500W ~ 1500W, biased radio-frequency power is 100W ~ 200W, process time is 40s ~ 100s, the residual thickness of the unlapped conductive metal layer 412 of the photoresist layer 413 after dry etching is [0.2 μm +/-0.05 μm] ~ [1.2 μm +/-0.05 μm], namely 0.15 μm ~ 1.25 μm.According to different requirement on devices, the residual thickness of the unlapped conductive metal layer 412 of the photoresist layer 413 after dry etching can suitably change, and now the technological parameter of dry etching can require to carry out accommodation according to residual thickness.As follows according to the technological parameter of technological requirement selection in the present embodiment: process pressure is 10mtorr, chlorine Cl
2flow is 70sccm, BCl
3flow is 60sccm, nitrogen N
2flow is 5sccm source radio-frequency power is 900W, and biased radio-frequency power is 150W, and the process time is 60s, and the residual thickness of the unlapped conductive metal layer 412 of the photoresist layer 413 after dry etching is 0.2 μm.
S23, please refer to Fig. 4 D, with described photoresist layer 413 for mask, wet-etching technology is adopted to continue the remaining conductive metal layer 412 of etching, etching stopping is on described etching barrier layer 411 surface, to remove the unlapped conductive metal layer 412 of described photoresist layer 413 completely, formation is rerouted layer 41, wherein, described wet etching needs to carry out in the queue waiting time Q-time of the layer etching processing procedure that reroutes required and complete, can be understood as: on production line, the layer manufacture of rerouting of last wafer is carried out when wet etching process, the layer manufacture of rerouting of a rear wafer is carried out in dry etching process, therefore the wet etching time of last wafer can not exceed the dry etching time of a rear wafer, after ensureing thus, the dry etching process of a wafer there will not be over etching, be provided with queue waiting time Q-time for this reason, the process time of wet etching can not exceed the queue waiting time Q-time of setting, ensure the quality of the final layer that reroutes formed thus.In the present embodiment, the time of described wet-etching technology accounts for 30% ~ 70% of described queue waiting time Q-time.The technological parameter of described wet etching comprises: nitric acid 1% ~ 2% volume ratio, phosphoric acid 75% ~ 85% volume ratio, acetic acid 5% ~ 10% volume ratio, water 10% ~ 20% volume ratio, and technological temperature 25 DEG C ~ 50 DEG C, conductive metal layer etch rate is
because the conductive metal layer of wet etching is thinning, therefore the process time shortens, etching can stop at etching barrier layer surface well, after removing dry etching fast while remaining conductive metal layer, the critical size of conductive metal layer and top-level metallic not only can not be caused obviously to reduce, and the fence defect of dry etching formation can also be eliminated, avoid producing a large amount of wet etching residue, ensure that the quality of the layer that reroutes thus, finally improve device performance.
Please refer to Fig. 4 E, in step s3, adopt technological temperature, oxygen, fluorine hybrid technique gas higher than 200 DEG C to carry out ashing process, to remove photoresist layer 413.Further, to on the basis of the layer 41 that reroutes exposed, the MEMS manufactured is encapsulated, particularly, form the interlayer dielectric layer of the materials such as one deck polyimides (polyimide-PI) or epoxy resin (Epoxy) on layer 41 surface of rerouting, employing photoetching, etching technics form BGA conductive trench in interlayer dielectric layer; Adopt BGA process filling BGA conductive trench, form BGA tin ball as conductive salient point 42.In other embodiments of the invention, plating backflow or laser ball implanting technique can be adopted to form conductive salient point on described layer surface of rerouting.
In sum, layer manufacturing method and the MEMS chip method for packing of rerouting provided by the invention, first dry etching is carried out to conductive metal layers such as the unlapped Al of photoresist, make it to reduce certain thickness, then within the Q-Time time of process set, transfer wet etching to, the residual thickness of the conductive metal layers such as the unlapped Al of photoresist is removed completely, etching can stop at etching barrier layer surface well, the fence defect of layer sidewall that reroute after this wet etching process eliminates dry etching, the over etching consumption of top layer interconnection structure can not be caused, simultaneously due to the thinner thickness of wet etching, so the critical size of the layer that reroutes after wet etching can be made to reach requirement completely, and avoid the accumulation of a large amount of etch residue, ensure that the quality of the layer that reroutes, finally improve device performance.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. reroute a layer manufacturing method, it is characterized in that, comprising:
There is provided semi-conductive substrate, form the photoresist layer of etching barrier layer, conductive metal layer and patterning on the semiconductor substrate successively, the described conductive metal layer of the pattern definition of described photoresist layer forms the position of the layer that reroutes;
With described photoresist layer for mask, adopt conductive metal layer described in dry etch process partial etching, to reduce the thickness of the unlapped conductive metal layer of described photoresist layer, and make remaining conductive metal layer still can cover described etching barrier layer comprehensively;
Etch in processing procedure queue waiting time Q-time at the layer that reroutes of setting, continue with described photoresist layer as mask, adopt wet-etching technology to remove the residual thickness of the unlapped conductive metal layer of described photoresist layer completely, etching stopping, on described etching barrier layer surface, forms the layer that reroutes.
2. reroute layer manufacturing method as claimed in claim 1, it is characterized in that, be formed with MEMS circuit and electric connecting point in described Semiconductor substrate, described in the layer that reroutes be electrically connected by electric connecting point with described MEMS circuit; Or be formed with the metal interconnect structure above MEMS circuit and MEMS circuit in described Semiconductor substrate, described MEMS circuit is electrically connected by metal interconnect structure and the described layer that reroutes.
3. reroute layer manufacturing method as claimed in claim 1, it is characterized in that, described etching barrier layer is titanium nitride or tantalum nitride.
4. reroute layer manufacturing method as claimed in claim 1, it is characterized in that, described conductive metal layer is aluminium, aluminium alloy, copper or copper alloy.
5. reroute layer manufacturing method as claimed in claim 1, it is characterized in that, the conducting metal layer thickness formed on a semiconductor substrate is 1 μm ~ 2 μm, and after described dry etching, the residual thickness of conductive metal layer is 0.15 μm ~ 1.25 μm.
6. reroute layer manufacturing method as claimed in claim 1, it is characterized in that, described queue waiting time Q-time is less than 12 hours, and the time of described wet-etching technology accounts for 30% ~ 70% of described queue waiting time Q-time.
7. reroute layer manufacturing method as claimed in claim 1, and it is characterized in that, the technological parameter of described dry etching comprises: process gas comprises Cl
2, BCl
3and N
2, source radio-frequency power is 500W ~ 1500W, and biased radio-frequency power is 100W ~ 200W, and the process time is 40s ~ 80s; The technological parameter of described wet etching comprises: nitric acid 1% ~ 2% volume ratio, phosphoric acid 75% ~ 85% volume ratio, acetic acid 5% ~ 10% volume ratio, water 10% ~ 20% volume ratio, and technological temperature 25 DEG C ~ 50 DEG C, conductive metal layer etch rate is
8. a MEMS manufacture method, is characterized in that, comprising:
The MEMS substrate that one has a MEMS circuit is provided, described MEMS substrate surface is formed with electric connecting point or metal interconnect structure;
According to the manufacture method that reroutes according to any one of claim 1 to 7, described MEMS substrate surface is formed and to reroute layer, described in reroute layer and described electric connecting point or metal interconnect structure be electrically connected.
9. MEMS manufacture method as claimed in claim 8, is characterized in that, adopts plating backflow or laser ball implanting technique to form conductive salient point on described layer surface of rerouting.
10. MEMS manufacture method as claimed in claim 8, is characterized in that, the step forming conductive salient point on described layer surface of rerouting comprises:
Interlayer dielectric layer is formed on the surface at the described layer that reroutes;
Photoetching also etches described interlayer dielectric layer, forms conductive trench;
Adopt conductive trench described in BGA process filling, form spherical conductive salient point.
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| CN112259466A (en) * | 2019-07-22 | 2021-01-22 | 中芯长电半导体（江阴）有限公司 | Preparation method of rewiring layer |
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| US20120056320A1 (en) * | 2010-09-03 | 2012-03-08 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of semiconductor device |
| US20140076619A1 (en) * | 2012-09-20 | 2014-03-20 | Samsung Electro-Mechanics Co., Ltd. | Method for removing seed layer in manufacturing printed circuit board and printed circuit board manufactured by using the same |
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