CN104584431A - 调整时钟信号的系统和方法 - Google Patents
调整时钟信号的系统和方法 Download PDFInfo
- Publication number
- CN104584431A CN104584431A CN201380044715.0A CN201380044715A CN104584431A CN 104584431 A CN104584431 A CN 104584431A CN 201380044715 A CN201380044715 A CN 201380044715A CN 104584431 A CN104584431 A CN 104584431A
- Authority
- CN
- China
- Prior art keywords
- signal
- clock signal
- programmable
- duty cycle
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/598,513 US9143121B2 (en) | 2012-08-29 | 2012-08-29 | System and method of adjusting a clock signal |
| US13/598,513 | 2012-08-29 | ||
| PCT/US2013/056050 WO2014035771A2 (en) | 2012-08-29 | 2013-08-21 | System and method of adjusting a clock signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104584431A true CN104584431A (zh) | 2015-04-29 |
Family
ID=49083804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201380044715.0A Pending CN104584431A (zh) | 2012-08-29 | 2013-08-21 | 调整时钟信号的系统和方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9143121B2 (https=) |
| EP (1) | EP2891245A2 (https=) |
| JP (1) | JP5960362B2 (https=) |
| CN (1) | CN104584431A (https=) |
| WO (1) | WO2014035771A2 (https=) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106569162A (zh) * | 2016-10-17 | 2017-04-19 | 深圳市鼎阳科技有限公司 | 一种逻辑分析仪探头的模拟带宽测量方法与装置 |
| CN110855271A (zh) * | 2018-08-20 | 2020-02-28 | 台湾积体电路制造股份有限公司 | 时钟电路、时钟占空比调整和校准电路及其操作方法 |
| CN112636720A (zh) * | 2020-12-24 | 2021-04-09 | 海光信息技术股份有限公司 | 输入输出信号的占空比校准电路、高速接口电路及处理器 |
| CN112787633A (zh) * | 2020-12-24 | 2021-05-11 | 海光信息技术股份有限公司 | 占空比校准电路、高速接口电路、处理器及电子设备 |
| CN113484565A (zh) * | 2021-07-14 | 2021-10-08 | 国网新疆电力有限公司电力科学研究院 | 用于校准低频交流信号的直流信号生成装置及校准方法 |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011128984A1 (ja) * | 2010-04-13 | 2011-10-20 | 富士通株式会社 | 動作確認試験方法、動作確認試験プログラム、及びクロック分配回路 |
| US9419736B2 (en) * | 2013-03-15 | 2016-08-16 | Gigoptix-Terasquare Korea Co., Ltd. | Low-power CML-less transmitter architecture |
| US9825755B2 (en) | 2013-08-30 | 2017-11-21 | Qualcomm Incorporated | Configurable clock tree |
| US9419598B2 (en) * | 2013-11-26 | 2016-08-16 | Rambus Inc. | In-situ delay element calibration |
| US10097171B2 (en) * | 2014-07-25 | 2018-10-09 | Rfaxis, Inc. | Radio frequency switch with low oxide stress |
| US9263107B1 (en) * | 2014-11-06 | 2016-02-16 | Qualcomm Incorporated | Load isolation for pad signal monitoring |
| US10444778B2 (en) * | 2016-08-09 | 2019-10-15 | Nxp Usa, Inc. | Voltage regulator |
| US9740813B1 (en) * | 2016-10-13 | 2017-08-22 | International Business Machines Corporation | Layout effect characterization for integrated circuits |
| KR102407546B1 (ko) | 2017-12-04 | 2022-06-13 | 에스케이하이닉스 주식회사 | 스큐 검출 회로 및 이를 이용한 입력 회로 |
| JP7071621B2 (ja) * | 2018-01-22 | 2022-05-19 | 株式会社ソシオネクスト | 送信回路及び集積回路 |
| US11437992B2 (en) | 2020-07-30 | 2022-09-06 | Mobix Labs, Inc. | Low-loss mm-wave CMOS resonant switch |
| US12375089B2 (en) | 2022-06-30 | 2025-07-29 | Microchip Technology Incorporated | Reducing duty cycle mismatch of clock signals for clock tracking circuits |
| KR102722312B1 (ko) * | 2022-12-12 | 2024-10-25 | 주식회사 퀄리타스반도체 | 클럭 듀티 캘리브레이션 장치 및 방법 |
| KR20240131776A (ko) * | 2023-02-24 | 2024-09-02 | 삼성전자주식회사 | 플래시 메모리 및 그것의 읽기 리커버리 방법 |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4719369A (en) * | 1985-08-14 | 1988-01-12 | Hitachi, Ltd. | Output circuit having transistor monitor for matching output impedance to load impedance |
| CN1412947A (zh) * | 2002-10-30 | 2003-04-23 | 威盛电子股份有限公司 | 可调整工作周期的缓冲器及其操作方法 |
| US20030112045A1 (en) * | 2001-12-14 | 2003-06-19 | International Business Machines Corporation | Precision aligned multiple concurrent duty cycles from a programmable duty cycle generator |
| US20050253637A1 (en) * | 2004-05-17 | 2005-11-17 | Raj Mahadevan | Duty-cycle correction circuit |
| US20060006915A1 (en) * | 2004-07-12 | 2006-01-12 | Hai Yan | Signal slew rate control for image sensors |
| CN1988384A (zh) * | 2005-12-21 | 2007-06-27 | 国际商业机器公司 | 用于差分计时的占空比校正电路和方法 |
| US7423467B1 (en) * | 2006-05-30 | 2008-09-09 | National Semiconductor Corporation | Circuit for controlling duty cycle distortion |
| US20100188126A1 (en) * | 2009-01-26 | 2010-07-29 | International Business Machines Corporation | Voltage Controlled Duty Cycle and Non-Overlapping Clock Generation Implementation |
| US20100315119A1 (en) * | 2009-06-12 | 2010-12-16 | Freescale Semiconductor, Inc. | Memory controller calibration |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58159020A (ja) * | 1982-03-17 | 1983-09-21 | Hitachi Ltd | パルスデユ−テイ比安定回路 |
| FR2709217B1 (fr) * | 1993-08-19 | 1995-09-15 | Bull Sa | Procédé et dispositif d'adaptation d'impédance pour un émetteur et/ou récepteur, circuit intégré et système de transmission les mettant en Óoeuvre. |
| US5677639A (en) * | 1994-12-08 | 1997-10-14 | Seagate Technology, Inc. | Autonomous selection of output buffer characteristics as determined by load matching |
| US5621335A (en) * | 1995-04-03 | 1997-04-15 | Texas Instruments Incorporated | Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading |
| US5604450A (en) * | 1995-07-27 | 1997-02-18 | Intel Corporation | High speed bidirectional signaling scheme |
| US5963071A (en) * | 1998-01-22 | 1999-10-05 | Nanoamp Solutions, Inc. | Frequency doubler with adjustable duty cycle |
| JP4101973B2 (ja) * | 1999-05-21 | 2008-06-18 | 株式会社ルネサステクノロジ | 出力バッファ回路 |
| US6452428B1 (en) * | 1999-11-23 | 2002-09-17 | Intel Corporation | Slew rate control circuit |
| US7009435B2 (en) * | 2004-03-09 | 2006-03-07 | Nano Silicon Pte Ltd. | Output buffer with controlled slew rate for driving a range of capacitive loads |
| US7802212B2 (en) | 2005-04-15 | 2010-09-21 | Rambus Inc. | Processor controlled interface |
| US7386750B2 (en) * | 2005-07-15 | 2008-06-10 | Hewlett-Packard Development Company, L.P. | Reduced bus turnaround time in a multiprocessor architecture |
| US8067948B2 (en) | 2006-03-27 | 2011-11-29 | Cypress Semiconductor Corporation | Input/output multiplexer bus |
| US7809052B2 (en) | 2006-07-27 | 2010-10-05 | Cypress Semiconductor Corporation | Test circuit, system, and method for testing one or more circuit components arranged upon a common printed circuit board |
| JP2008160610A (ja) * | 2006-12-26 | 2008-07-10 | Nec Electronics Corp | クロックデューティ変更回路 |
| KR100945797B1 (ko) * | 2008-05-30 | 2010-03-08 | 주식회사 하이닉스반도체 | 듀티 사이클 보정 회로 및 방법 |
| KR100940836B1 (ko) * | 2008-06-04 | 2010-02-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 듀티 싸이클 보정 회로 |
| US8718574B2 (en) * | 2008-11-25 | 2014-05-06 | Qualcomm Incorporated | Duty cycle adjustment for a local oscillator signal |
| US7760124B2 (en) | 2008-12-02 | 2010-07-20 | Infineon Technologies Ag | System and method for A/D conversion |
| US8107913B1 (en) * | 2009-05-07 | 2012-01-31 | Qualcomm Atheros, Inc. | Method and apparatus for a digital regulated local oscillation (LO) buffer in radio frequency circuits |
| US8279688B2 (en) | 2010-07-26 | 2012-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sense amplifier enable signal generation |
| US8542046B2 (en) * | 2011-05-04 | 2013-09-24 | Intel Corporation | Apparatus, system, and method for voltage swing and duty cycle adjustment |
-
2012
- 2012-08-29 US US13/598,513 patent/US9143121B2/en not_active Expired - Fee Related
-
2013
- 2013-08-21 JP JP2015529866A patent/JP5960362B2/ja not_active Expired - Fee Related
- 2013-08-21 CN CN201380044715.0A patent/CN104584431A/zh active Pending
- 2013-08-21 WO PCT/US2013/056050 patent/WO2014035771A2/en not_active Ceased
- 2013-08-21 EP EP13753990.4A patent/EP2891245A2/en not_active Withdrawn
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4719369A (en) * | 1985-08-14 | 1988-01-12 | Hitachi, Ltd. | Output circuit having transistor monitor for matching output impedance to load impedance |
| US20030112045A1 (en) * | 2001-12-14 | 2003-06-19 | International Business Machines Corporation | Precision aligned multiple concurrent duty cycles from a programmable duty cycle generator |
| CN1412947A (zh) * | 2002-10-30 | 2003-04-23 | 威盛电子股份有限公司 | 可调整工作周期的缓冲器及其操作方法 |
| US20050253637A1 (en) * | 2004-05-17 | 2005-11-17 | Raj Mahadevan | Duty-cycle correction circuit |
| US20060006915A1 (en) * | 2004-07-12 | 2006-01-12 | Hai Yan | Signal slew rate control for image sensors |
| CN1988384A (zh) * | 2005-12-21 | 2007-06-27 | 国际商业机器公司 | 用于差分计时的占空比校正电路和方法 |
| US7423467B1 (en) * | 2006-05-30 | 2008-09-09 | National Semiconductor Corporation | Circuit for controlling duty cycle distortion |
| US20100188126A1 (en) * | 2009-01-26 | 2010-07-29 | International Business Machines Corporation | Voltage Controlled Duty Cycle and Non-Overlapping Clock Generation Implementation |
| US20100315119A1 (en) * | 2009-06-12 | 2010-12-16 | Freescale Semiconductor, Inc. | Memory controller calibration |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106569162A (zh) * | 2016-10-17 | 2017-04-19 | 深圳市鼎阳科技有限公司 | 一种逻辑分析仪探头的模拟带宽测量方法与装置 |
| CN106569162B (zh) * | 2016-10-17 | 2019-04-02 | 深圳市鼎阳科技有限公司 | 一种逻辑分析仪探头的模拟带宽测量方法与装置 |
| CN110855271A (zh) * | 2018-08-20 | 2020-02-28 | 台湾积体电路制造股份有限公司 | 时钟电路、时钟占空比调整和校准电路及其操作方法 |
| CN110855271B (zh) * | 2018-08-20 | 2023-08-08 | 台湾积体电路制造股份有限公司 | 时钟电路、时钟占空比调整和校准电路及其操作方法 |
| CN112636720A (zh) * | 2020-12-24 | 2021-04-09 | 海光信息技术股份有限公司 | 输入输出信号的占空比校准电路、高速接口电路及处理器 |
| CN112787633A (zh) * | 2020-12-24 | 2021-05-11 | 海光信息技术股份有限公司 | 占空比校准电路、高速接口电路、处理器及电子设备 |
| CN113484565A (zh) * | 2021-07-14 | 2021-10-08 | 国网新疆电力有限公司电力科学研究院 | 用于校准低频交流信号的直流信号生成装置及校准方法 |
| CN113484565B (zh) * | 2021-07-14 | 2024-02-13 | 国网新疆电力有限公司电力科学研究院 | 用于校准低频交流信号的直流信号生成装置及校准方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5960362B2 (ja) | 2016-08-02 |
| EP2891245A2 (en) | 2015-07-08 |
| WO2014035771A2 (en) | 2014-03-06 |
| JP2015530820A (ja) | 2015-10-15 |
| WO2014035771A3 (en) | 2014-07-03 |
| US20140062559A1 (en) | 2014-03-06 |
| US9143121B2 (en) | 2015-09-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150429 |