CN104488195B - 失真容限时钟和数据恢复系统 - Google Patents

失真容限时钟和数据恢复系统 Download PDF

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Publication number
CN104488195B
CN104488195B CN201380039014.8A CN201380039014A CN104488195B CN 104488195 B CN104488195 B CN 104488195B CN 201380039014 A CN201380039014 A CN 201380039014A CN 104488195 B CN104488195 B CN 104488195B
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China
Prior art keywords
signal
error
center frequency
controlled oscillator
control signal
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CN201380039014.8A
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English (en)
Chinese (zh)
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CN104488195A (zh
Inventor
吉欧梵尼·库亚斯提
帕欧罗·诺威利尼
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Xilinx Inc
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Xilinx Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CN201380039014.8A 2012-05-30 2013-01-30 失真容限时钟和数据恢复系统 Active CN104488195B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/484,236 US8724764B2 (en) 2012-05-30 2012-05-30 Distortion tolerant clock and data recovery
US13/484,236 2012-05-30
PCT/US2013/023926 WO2013180766A1 (en) 2012-05-30 2013-01-30 Distortion tolerant clock and data recovery system

Publications (2)

Publication Number Publication Date
CN104488195A CN104488195A (zh) 2015-04-01
CN104488195B true CN104488195B (zh) 2016-03-16

Family

ID=47710353

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380039014.8A Active CN104488195B (zh) 2012-05-30 2013-01-30 失真容限时钟和数据恢复系统

Country Status (6)

Country Link
US (1) US8724764B2 (enExample)
EP (1) EP2856648B1 (enExample)
JP (1) JP5937753B2 (enExample)
KR (1) KR102023796B1 (enExample)
CN (1) CN104488195B (enExample)
WO (1) WO2013180766A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9590567B2 (en) 2015-07-02 2017-03-07 Xilinx, Inc. Moving mean and magnitude dual path digital predistortion
US9992049B1 (en) * 2016-06-17 2018-06-05 Xilinx, Inc. Numerically controlled oscillator for fractional burst clock data recovery applications
US11129596B2 (en) * 2016-10-06 2021-09-28 General Electric Company Systems and methods for ultrasound multiplexing
US10348312B1 (en) 2018-05-30 2019-07-09 Xilinx, Inc. Circuit for and method of implementing a bursty clock and data recovery circuit using an eyescan detection circuit
US11705910B1 (en) 2022-01-05 2023-07-18 Xilinx, Inc. Fast line rate switching in peripheral component interconnect express (PCIe) analyzers

Citations (5)

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Publication number Priority date Publication date Assignee Title
US20070002993A1 (en) * 2005-06-29 2007-01-04 Altera Corporation, A Corporation Of Delaware Clock data recovery loop with separate proportional path
CN101176258A (zh) * 2005-06-17 2008-05-07 三星电子株式会社 锁相环、用于锁相环的相位检测方法及使用其的接收器
CN101515802A (zh) * 2007-09-14 2009-08-26 英特尔公司 用于无参考时钟和数据恢复应用的相位/频率检测器以及电荷泵构架
CN101777911A (zh) * 2010-01-08 2010-07-14 智原科技股份有限公司 时钟数据恢复器
US20110025913A1 (en) * 2009-07-28 2011-02-03 Nec Electronics Corporation Clock data recovery circuit and display device

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Publication number Priority date Publication date Assignee Title
US5301196A (en) 1992-03-16 1994-04-05 International Business Machines Corporation Half-speed clock recovery and demultiplexer circuit
EP0758171A3 (en) * 1995-08-09 1997-11-26 Symbios Logic Inc. Data sampling and recovery
US6531926B1 (en) * 2001-09-13 2003-03-11 Overture Networks, Inc. Dynamic control of phase-locked loop
US7049869B2 (en) * 2003-09-02 2006-05-23 Gennum Corporation Adaptive lock position circuit
US20060064725A1 (en) * 2004-09-22 2006-03-23 Rosum Corporation Pilot acquisition and local clock calibration with reduced MIPS
US7751521B2 (en) 2004-11-16 2010-07-06 Electronics And Telecommunications Research Institute Clock and data recovery apparatus
US7268633B2 (en) * 2005-09-12 2007-09-11 P.A. Semi, Inc. Voltage-controlled oscillator for low-voltage, wide frequency range operation
US7996749B2 (en) * 2007-07-03 2011-08-09 Altera Corporation Signal loss detector for high-speed serial interface of a programmable logic device
US20090154626A1 (en) * 2007-12-15 2009-06-18 Anderson Warren R Continuous receiver clock alignment and equalization optimization
WO2010039108A1 (en) 2008-10-02 2010-04-08 Zenko Technologies, Inc. Data sampling circuit and method for clock and data recovery

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101176258A (zh) * 2005-06-17 2008-05-07 三星电子株式会社 锁相环、用于锁相环的相位检测方法及使用其的接收器
US20070002993A1 (en) * 2005-06-29 2007-01-04 Altera Corporation, A Corporation Of Delaware Clock data recovery loop with separate proportional path
CN101515802A (zh) * 2007-09-14 2009-08-26 英特尔公司 用于无参考时钟和数据恢复应用的相位/频率检测器以及电荷泵构架
US20110025913A1 (en) * 2009-07-28 2011-02-03 Nec Electronics Corporation Clock data recovery circuit and display device
CN101777911A (zh) * 2010-01-08 2010-07-14 智原科技股份有限公司 时钟数据恢复器

Also Published As

Publication number Publication date
JP2015524203A (ja) 2015-08-20
JP5937753B2 (ja) 2016-06-22
CN104488195A (zh) 2015-04-01
KR102023796B1 (ko) 2019-09-20
EP2856648A1 (en) 2015-04-08
WO2013180766A1 (en) 2013-12-05
KR20150015017A (ko) 2015-02-09
US20130321047A1 (en) 2013-12-05
US8724764B2 (en) 2014-05-13
EP2856648B1 (en) 2016-03-30

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