KR102023796B1 - 왜곡 내성 클럭 및 데이터 복구 시스템 - Google Patents

왜곡 내성 클럭 및 데이터 복구 시스템 Download PDF

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Publication number
KR102023796B1
KR102023796B1 KR1020147036755A KR20147036755A KR102023796B1 KR 102023796 B1 KR102023796 B1 KR 102023796B1 KR 1020147036755 A KR1020147036755 A KR 1020147036755A KR 20147036755 A KR20147036755 A KR 20147036755A KR 102023796 B1 KR102023796 B1 KR 102023796B1
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South Korea
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signal
error
center frequency
generate
control signal
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Korean (ko)
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KR20150015017A (ko
Inventor
지오반니 구아스티
파올로 노벨리니
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자일링크스 인코포레이티드
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR1020147036755A 2012-05-30 2013-01-30 왜곡 내성 클럭 및 데이터 복구 시스템 Active KR102023796B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/484,236 2012-05-30
US13/484,236 US8724764B2 (en) 2012-05-30 2012-05-30 Distortion tolerant clock and data recovery
PCT/US2013/023926 WO2013180766A1 (en) 2012-05-30 2013-01-30 Distortion tolerant clock and data recovery system

Publications (2)

Publication Number Publication Date
KR20150015017A KR20150015017A (ko) 2015-02-09
KR102023796B1 true KR102023796B1 (ko) 2019-09-20

Family

ID=47710353

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Application Number Title Priority Date Filing Date
KR1020147036755A Active KR102023796B1 (ko) 2012-05-30 2013-01-30 왜곡 내성 클럭 및 데이터 복구 시스템

Country Status (6)

Country Link
US (1) US8724764B2 (enExample)
EP (1) EP2856648B1 (enExample)
JP (1) JP5937753B2 (enExample)
KR (1) KR102023796B1 (enExample)
CN (1) CN104488195B (enExample)
WO (1) WO2013180766A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9590567B2 (en) 2015-07-02 2017-03-07 Xilinx, Inc. Moving mean and magnitude dual path digital predistortion
US9992049B1 (en) * 2016-06-17 2018-06-05 Xilinx, Inc. Numerically controlled oscillator for fractional burst clock data recovery applications
US11129596B2 (en) * 2016-10-06 2021-09-28 General Electric Company Systems and methods for ultrasound multiplexing
US10348312B1 (en) 2018-05-30 2019-07-09 Xilinx, Inc. Circuit for and method of implementing a bursty clock and data recovery circuit using an eyescan detection circuit
US11705910B1 (en) 2022-01-05 2023-07-18 Xilinx, Inc. Fast line rate switching in peripheral component interconnect express (PCIe) analyzers

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US5301196A (en) 1992-03-16 1994-04-05 International Business Machines Corporation Half-speed clock recovery and demultiplexer circuit
EP0758171A3 (en) * 1995-08-09 1997-11-26 Symbios Logic Inc. Data sampling and recovery
US6531926B1 (en) * 2001-09-13 2003-03-11 Overture Networks, Inc. Dynamic control of phase-locked loop
US7049869B2 (en) * 2003-09-02 2006-05-23 Gennum Corporation Adaptive lock position circuit
US20060064725A1 (en) * 2004-09-22 2006-03-23 Rosum Corporation Pilot acquisition and local clock calibration with reduced MIPS
US7751521B2 (en) 2004-11-16 2010-07-06 Electronics And Telecommunications Research Institute Clock and data recovery apparatus
KR100724895B1 (ko) * 2005-06-17 2007-06-04 삼성전자주식회사 위상고정루프와 위상고정루프에서의 위상 검출방법 및 그를이용하는 수신기
US7580497B2 (en) * 2005-06-29 2009-08-25 Altera Corporation Clock data recovery loop with separate proportional path
US7268633B2 (en) * 2005-09-12 2007-09-11 P.A. Semi, Inc. Voltage-controlled oscillator for low-voltage, wide frequency range operation
US7996749B2 (en) * 2007-07-03 2011-08-09 Altera Corporation Signal loss detector for high-speed serial interface of a programmable logic device
US7692501B2 (en) * 2007-09-14 2010-04-06 Intel Corporation Phase/frequency detector and charge pump architecture for referenceless clock and data recovery (CDR) applications
US20090154626A1 (en) * 2007-12-15 2009-06-18 Anderson Warren R Continuous receiver clock alignment and equalization optimization
WO2010039108A1 (en) 2008-10-02 2010-04-08 Zenko Technologies, Inc. Data sampling circuit and method for clock and data recovery
JP5385718B2 (ja) * 2009-07-28 2014-01-08 ルネサスエレクトロニクス株式会社 クロックデータリカバリ回路
CN101777911A (zh) * 2010-01-08 2010-07-14 智原科技股份有限公司 时钟数据恢复器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
H. Noguchi 외, "A 40-Gb/s CDR CircuitWith Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback," IEEE Journal of Solid-State Circuits, vol. 43, no. 12, 2008. 12.*

Also Published As

Publication number Publication date
JP5937753B2 (ja) 2016-06-22
CN104488195A (zh) 2015-04-01
US8724764B2 (en) 2014-05-13
EP2856648B1 (en) 2016-03-30
EP2856648A1 (en) 2015-04-08
CN104488195B (zh) 2016-03-16
KR20150015017A (ko) 2015-02-09
US20130321047A1 (en) 2013-12-05
WO2013180766A1 (en) 2013-12-05
JP2015524203A (ja) 2015-08-20

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