CN104425427A - 器件 - Google Patents

器件 Download PDF

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Publication number
CN104425427A
CN104425427A CN201410427550.1A CN201410427550A CN104425427A CN 104425427 A CN104425427 A CN 104425427A CN 201410427550 A CN201410427550 A CN 201410427550A CN 104425427 A CN104425427 A CN 104425427A
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CN
China
Prior art keywords
carrier
carriers
solder ball
electrically connected
component
Prior art date
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Pending
Application number
CN201410427550.1A
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English (en)
Inventor
U·汉森
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Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
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Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of CN104425427A publication Critical patent/CN104425427A/zh
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/144—Stacked arrangements of planar printed circuit boards
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0264—Pressure sensors
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/10007—Types of components
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/10083—Electromechanical or electro-acoustic component, e.g. microphone
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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本发明涉及用于具有至少两个ASIC元件和/或MEMS元件的器件的封装方案，该方案可用标准工序并尤其用标准部件非常简单及成本上有利地转换应用。此外根据本发明的封装方案可实现具有相对小的“脚印”的封装壳体，它的元件在该器件结构中在很大程度上得到应力的脱耦。根据本发明将至少一个第一元件安装在一个扁平的第一载体上并与第一载体电连接。将至少一个第二元件安装在一个扁平的第二载体上并与第二载体电连接。然后将这两个载体这样相互叠置并通过侧壁相互连接，以致第一及第二元件被设置在两个载体之间的一个空腔中。侧壁至少部分地由多个焊料珠的一个相互紧靠着的排构成，通过这些焊料珠也使两个载体形成电连接。

Description

器件
技术领域
本发明涉及具有至少两个MEMS元件和/或ASIC元件的器件，这些元件被设置在一个共同的壳体中。
背景技术
对于用户的应用及在汽车技术中经常需要在一个封装壳体内组合不同的元件，例如MEMS元件及ASIC元件，这些元件在其功能上相互补充。为此将这些元件相互并列地或相互重叠地设置在一个共同的载体、例如一个引线框架(QFN)或一个叠层衬底(LGA)上并与该载体形成电连接，例如借助金属连接线来连接。以此方式使元件相互连接及通过载体也可形成外部电接触。在第一级安装的范围中载体上的元件仍还将封装。这使封装体的第二级安装简化并在第二级安装时保护元件以免损坏及在使用位置上抗外部干扰的影响。在许多应用中为此元件用模注材料注塑包封。根据另一封装方案将一个盖件放置在元件上面并与载体连接。基于载体的封装体在第二级安装的范围中通常用载体放置到一个印刷电路板上，以便然后用回流软熔焊接方法机械地固定及形成电接触。
在任何情况下在实现封装壳体时应考虑到元件的功能。这尤其适用于需要一个介质入口的传感器应用，例如压力传感器及微音器元件。
无论模制壳体还是具有盖件的壳体必需在一个单独的工序中制造，这就是说在一个适配于器件各个组成部分的个别尺寸及功能要求的工序中制造，这使成本相对地高。
器件结构中的或由器件的第二级安装引起的机械应力尤其在传感器器件的情况下将导致其性能受损。公知的器件方案对此特别无抵抗力，因为ASIC元件及MEMS元件在这里被固定在用于第二级安装的安装载体上。
发明内容
通过本发明提出了用于具有至少两个元件的器件的封装方案，该方案可用标准工序并尤其用标准部件非常简单及成本上有利地转换应用。这里两个元件既可均为MEMS元件也可均为ASIC元件或各为一个MEMS元件及一个ASIC元件。此外根据本发明的封装方案可实现具有相对小的“脚印”的封装壳体，它的元件在该器件结构中在很大程度上得到应力的脱耦。
根据本发明将这样来实现它，即将至少一个第一元件安装在一个扁平的第一载体上并与第一载体电连接；将至少一个第二元件安装在一个扁平的第二载体上并与第二载体电连接；将这两个载体这样相互叠置并通过侧壁相互连接，以致第一及第二元件被设置在两个载体之间的一个空腔中；及侧壁至少部分地由多个焊料珠的一个相互紧靠着的排构成，通过这些焊料珠也使两个载体形成电连接。
因此根据本发明的封装方案在于：器件以夹层形式装配。器件壳体基本上由两个扁平的载体组成，这两个载体相互独立地安装器件的元件及安装焊料珠或焊料球。然后通过这些焊料珠使两个载体侧面或多或少环绕地相互连接，以致载体的安装元件的面相互面对着。在此情况下也形成了两个载体之间的电连接，以致器件在第二级安装的范围中总地通过两个载体之一可形成电接触。作为载体可使用传统的引线框架或叠层衬底。载体的元件安装及焊料珠的放置借助微系统技术的标准方法来实现。器件的对应力特别敏感的元件被设置在不用作第二级安装的安装载体的那个载体上。由此可使安装引起的机械应力至少对于器件的一部分元件来说明显地减小。此外根据本发明的封装方案开辟了一个可能性，即将在两个载体上安装的元件重叠地布置。由此可使所谓“脚印”、即在第二级安装时器件所需的安装面积简易地减小，而无需大的制造成本。
鉴于器件EMV特性的改善证明了：使用具有至少一个接地面的层叠板作为用于元件的整体或壳体部分是有利的。
铜柱尤其适用来实现器件壳体的侧壁。但侧壁也可包括无源电元件，例如电阻和/或电容器，它们也可用标准的设备及用标准的工序放置到载体上。因为这些无源电元件不仅用作两个载体之间的距离保持，而且在相应连接的情况下也构成两个载体的触点之间一个横向电阻或横向电容，所以必需这样选择它们，即它们对器件的电路功能无不利影响或为电路的组成部分。
如果器件功能需要一个介质接口，例如在压力传感器或微音器器件的情况下，则该介质接口将有利地构成在侧壁的区域中。以此方式可放弃器件的一个或两个载体的专门的预批量生产。因为根据本发明的器件的第二级安装通过两个载体之一来进行，所以至少该载体应装备用于器件的外部电接触的连接焊点。
附图说明
如以上所讨论的，以有利的方式对本发明进行配置及进一步构型存在各种可能性。对此一方面可参阅从属于权利要求1的权利要求及另一方面可参阅以下关于根据本发明的封装方案的两个实施例的说明。
图1a-1e借助一个器件100在组建期间的各组成部分的概要截面图所表示的根据本发明的封装方案，及
图2a，2b借助一个器件200在制造期间的各组成部分的概要截面图所表示的壳体结构的一个变型。
具体实施形式
用于根据本发明的具有至少两个MEMS元件和/或ASIC元件的器件的组建的起始点是两个扁平的载体10，20，它们被表示在图1a中。这里这种载体例如可涉及引线框架(Leadframe)或涉及层叠板，如在现有技术中在MEMS元件和/或ASIC元件的第一级安装时所使用的。有利地使用具有至少一个接地面的层叠板作为载体10，20，以屏蔽器件中的元件免受电磁干扰的影响。在这里所示的实施例中载体10用作待制造的器件的第二级安装的安装载体。该载体在其载体下侧面上设置了连接焊点11及这里未示出的穿透触点。通过这些连接焊点11例如可使被制造的器件机械地固定在一个印刷电路板上并形成电接触。
这两个载体10及20将相互独立地被装配元件，如图1b中所示。在载体10安装一个ASIC元件1，而在载体20上安装一个微机械的压力传感器元件2。有利的是用于压力传感器元件2的求值电路的至少一部分集成在ASIC元件1上。
这两个元件1，2也可与相应的载体10或20进行电连接，这通过图1c来表明。这里在元件1，2固定在相应的载体10或20上后借助金属连接线3，4形成电连接。但元件1，2与相应的载体10或20之间的电连接也可在一个工序步骤中与机械连接一起形成，例如用倒装芯片技术或通过元件1，2中的穿透触点及元件背面的连接焊点。
在载体10及20的元件装配后在这两个载体至少之一上、这里是在载体10上施加焊料珠5，这些焊料珠将构成器件壳体的侧壁。与此相应地多个焊料珠5构成了一个闭合的相互紧靠的排。视器件功能而定，该焊料珠排也可具有一个或多个中断点–如果器件壳体应设有一个或多个介质通入口的话。器件壳体的净高将通过焊料珠5的厚度和/或叠放地施加的焊料珠的数目来确定，这些焊料珠5则构成由焊料材料组成的一个柱，如图1d中所示。在此处应指出，该侧壁也可两方面来放置，其方式是两个载体上均设置焊料珠的排列，它们仅构成壁区段。然后在下一安装步骤中使这些壁区段相互接合，然而这与附加的调准成本相关联。在本发明的一个优选实施形式中对于焊料珠使用铜。因此在下一安装步骤中可非常简单地在两个载体10与20之间建立电连接。
在该安装步骤中将两个载体10及20“面对面”地相互重叠地放置，以致这些载体与焊料珠5的相互紧靠着的排一起构成了用于元件1及2的壳体，如通过图1e所表明的。载体10及20装配了元件的侧彼此相向。在此情况下元件1及2至少部分地叠置、即横向上重叠地设置在载体10与20之间的一个空腔7中。而焊料珠柱5被这样地定尺寸，以致元件1及2在垂直方向上相互隔开。最后在一个焊接工序中在两个载体10与20之间不仅形成机械的连接而且也形成电连接，在该焊接工序中使焊料珠柱5熔化。在该结构中MEMS元件2与安装载体10在机械上得到很大程度的脱耦。
以上仅描述了根据本发明的单个器件100的结构。这些器件100能够非常简单地用载体联体大件数地制造。在实际制造中使用这样的载体衬底，该载体衬底将装配数百个或上千个元件。在两个被这样装配了元件及设置了焊料珠的载体衬底被相互连接后，才将器件分离。在此情况下例如通过“锯”由载体联体上锯下器件。
图2a及2b中所示的结构方案也是从两个扁平的载体10，20开始，这些载体如在现有技术中在MEMS元件及ASIC元件的第一级安装时所使用的。如在器件100的情况下这两个载体10及20相互独立地装配一个ASIC元件1及一个MEMS压力传感器元件2。这里元件1，2与相应的载体10或20之间的电连接也借助金属连接线3，4来形成。
与器件100不同地这里所述的器件200不仅仅通过闭合的或中断的焊料珠柱的相互紧靠着的排来构成，而此外还包括无源的电元件6，例如电阻或电容器。在这里所述的实施例中这些无源的电元件6在载体10及20装配元件后与这里未示出的焊料珠一起施加在安装载体10上，如图2a中所示。在此情况下无源电元件6的一个连接端子被放置在安装载体10的一个连接焊点上。在无源电元件6的仍自由的对立侧上具有另一连接端子。两个连接端子被全面地浸过锡。无源的电元件6可直接相互紧靠地排列或也可被布置在焊料珠柱5之间。图2a表明：无源的电元件6的几何尺寸确定了器件壳体的净高。
并且在器件200的情况下可在两方面放置侧壁，其方式是两个载体均设有无源的电元件6和/或焊料珠柱，然后在下一安装步骤中将它们接合成一个侧壁。
该安装步骤的结果表示在图2b中。两个载体10及20被“面对面”地相互重叠地放置，以致载体20用其相应的连接焊点紧贴在无源电元件6的自由连接端子上。最后在一个焊接工序中在无源电元件6及焊料珠柱与两个载体10与20之间不仅形成机械的连接而且也形成电连接，在此情况下除焊料珠柱5外无源电元件6的连接端子上的锡也被熔化。
元件1及2至少部分地叠置、即横向上重叠地布置。而无源电元件6及这里未示出的焊料珠柱被这样地定尺寸，以致元件1及2在垂直方向上相互隔开。以此方式使MEMS压力传感器元件2与用于第二级安装的安装载体10在机械上很大程度地脱耦。
如器件100的那样器件200也能够非常简单地用载体联体大件数地制造。在两个装配了元件及设置了无源电元件及焊料珠柱的载体衬底连接后才进行分离，例如通过锯开。

Claims (7)

1.具有至少两个ASIC元件和/或MEMS元件的器件，这些元件被设置在一个共同的壳体中，其特征在于：
·至少一个第一元件(1)安装在一个扁平的第一载体(10)上并与该第一载体(10)电连接，
·至少一个第二元件(2)安装在一个扁平的第二载体(20)上并与该第二载体(20)电连接，
·这两个载体(10，20)这样相互叠置并通过侧壁相互连接，以致第一及第二元件(1，2)被设置在所述两个载体(10，20)之间的一个空腔(7)中，及
·所述侧壁至少部分地由相互紧靠着排列的多个焊料珠(5)构成，通过这些焊料珠也使两个载体(10，20)形成电连接。
2.根据权利要求1的器件，其特征在于：使用具有至少一个接地面的层叠板作为第一和/或第二载体。
3.根据权利要求1或2的器件，其特征在于：环绕的所述侧壁至少部分地由铜柱构成。
4.根据权利要求1至3中任一项的器件，其特征在于：所述侧壁包括无源电元件(6)，尤其电阻和/或电容器。
5.根据权利要求1至4中任一项的器件，其特征在于：第一及第二元件(1，2)至少部分重叠地设置。
6.根据权利要求1至5中任一项的器件，其特征在于：在所述侧壁的区域中构有至少一个压力连接孔和/或声孔。
7.根据权利要求1至6中任一项的器件，其特征在于：至少一个载体(10)设有用于器件(100)的外部电接触的连接焊点。
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