CN104319262A - 一种多晶氧化物薄膜晶体管阵列基板及其制备方法 - Google Patents

一种多晶氧化物薄膜晶体管阵列基板及其制备方法 Download PDF

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CN104319262A
CN104319262A CN201410640940.7A CN201410640940A CN104319262A CN 104319262 A CN104319262 A CN 104319262A CN 201410640940 A CN201410640940 A CN 201410640940A CN 104319262 A CN104319262 A CN 104319262A
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film transistor
transistor array
array substrate
oxide film
polycrystalline oxide
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CN104319262B (zh
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胡合合
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BOE Technology Group Co Ltd
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Priority to EP15778180.8A priority patent/EP3220414B1/en
Priority to PCT/CN2015/076263 priority patent/WO2016074427A1/zh
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Abstract

本发明提供一种多晶氧化物薄膜晶体管阵列基板及其制备方法。本发明通过两步法形成多晶氧化物薄膜晶体管阵列基板的多晶氧化物薄膜层，克服了现有技术中需要在超高温退火，实现在现有的非晶氧化物薄膜晶体管阵列基板制备工艺制备多晶氧化物薄膜晶体管阵列基板，不需要增加特殊设备和特殊工艺易于实现；同时不需要高温退火，也节降低了能耗。

Description

一种多晶氧化物薄膜晶体管阵列基板及其制备方法
技术领域
本发明涉及显示产品制造技术领域，具体地，涉及一种多晶氧化物薄膜晶体管阵列基板及其制备方法。
背景技术
多晶氧化物沟道具有高迁移率、耐酸刻蚀和稳定性好等特点，其制备工艺受到显示面板行业的高度关注。
晶体生长方式有两种，一种是均相生长，一种是非均相生长。均相生长需要的过冷度大，生长比较困难；非均相生长是借助外来粒子或已有晶核进行生长，这种方式需要的能量小，生长快。此外，根据晶体生长理论，晶体生长时，平整界面上原子不易堆砌，生长速度慢；粗糙界面上原子易堆砌，生长速度快。
由于目前氧化物沟道所采用的In2O3,ZnO,Ga2O3和SnO2以及他们的复合物均有很高的熔点(大于1000℃)和结晶点，多晶氧化物沟道的成膜方法一般具有较高的成膜速率，且成膜衬底也多为非晶状态，因此常规工艺，例如，磁控溅射沉积、脉冲激光沉积、溶液法制备非晶膜，得到的氧化物薄膜一般为非晶状态，要使这样的非晶态薄膜转变多晶态需要很高的能量，例如，需要超高温退火(大于450℃)，能耗大。
现有的薄膜晶体管阵列基板的生产线上退火设备温度上限一般为450℃，温度超过450℃的退火设备在加热器和加热均一性上有很大的挑战，因此生产线较难实现成膜后超高温热处理工艺，并且高温退火处理对衬底玻璃性能要求高，能耗大等缺点。
因此，在现有的生产线上生产具有多晶氧化物沟道的薄膜晶体管阵列基板成为研究的重点。
发明内容
本发明针对现有薄膜晶体管阵列基板的生产线上存在不适合制作具有多晶氧化物沟道的薄膜晶体管阵列基板的问题，提供一种具有多晶氧化物沟道的薄膜晶体管阵列基板的制备方法。
本发明提供一种本发明还提供一种多晶氧化物薄膜晶体管阵列基板的制备方法，包括以下步骤：
1)在衬底上形成非晶态氧化物薄膜层的步骤；
2)将所述非晶态氧化物薄膜层进行选择性刻蚀的步骤；
3)对经过步骤2的非晶态氧化物薄膜层进行钝化和退火处
理；
4)在经过步骤3的氧化物薄膜层上第二次形成氧化物薄膜，通过构图工艺形成有源层沟道；
5)对经过步骤4的有源层沟道进行退火处理。
优选的是，在所述的步骤1中非晶态氧化物薄膜层的厚度为
优选的是，在所述的步骤1中采用磁控溅射法形成非晶态氧化物薄膜层；磁控溅射的条件为：功率为2-8Kw、压强为0.3-0.8Pa，氧气含量为5％-50％，温度为室温。
优选的是，在所述的步骤2中将非晶态氧化物薄膜层中堆砌不规则的原子刻蚀去除；保留堆砌规则的原子。
优选的是，在所述的步骤2中所述的选择性刻蚀为干法刻蚀；采用N2或Ar气体的等离子体对所述非晶态氧化物薄膜层进行轰击；干法刻蚀的条件为：功率为1200-1800W，压强为1500-2500mTorr，温度为120-180℃，处理时间为150-200s。
优选的是，在所述的步骤2中所述的选择性刻蚀为湿法刻蚀；采用能腐蚀非晶态氧化物薄膜层的酸性刻蚀溶液进行刻蚀，使得在刻蚀区域有10-50％非晶态氧化物薄膜层被保留。
优选的是，在所述的步骤3中所述的退火处理为在300℃-450℃下退火1-2h。
优选的是，在所述的步骤3中所述的钝化处理为等离子体钝化处理。
优选的是，所述的等离子体钝化处理为采用N2O等离子体对非晶态氧化物薄膜层进行钝化处理；所述钝化处理的条件为：功率为800-1200W，压强为1200-1800mTorr，温度为150-250℃，处理时间为50-100s。
优选的是，在所述的步骤4中采用磁控溅射法在经过步骤3的氧化物薄膜层上第二次形成氧化物薄膜；所述磁控溅射的条件为：功率为3-10Kw，压强为0.8-1.2Pa，氧气含量为5-50％，温度为室温，成膜速率小于
优选的是，在所述的步骤4中第二次形成的氧化物薄膜的厚度为
优选的是，在所述的步骤5中所述的退火处理条件为在300℃-450℃下，退火1-2h。
本发明的另一个目的是提供一种多晶氧化物薄膜晶体管阵列基板，所述的多晶氧化物薄膜晶体管阵列基板是采用上述的多晶氧化物薄膜晶体管阵列基板的制备方法制备的。
本发明的有益效果：本发明通过两步法形成多晶氧化物薄膜晶体管阵列基板的多晶氧化物薄膜层，克服了现有技术中需要在超高温退火，实现在现有的非晶氧化物薄膜晶体管阵列基板制备工艺制备多晶氧化物薄膜晶体管阵列基板，不需要增加特殊设备和特殊工艺易于实现；同时不需要高温退火，也节降低了能耗。
附图说明
图1为本发明实施例1中形成第一次形成氧化物薄膜层后的结构示意图；
图2为图1的非晶态氧化物薄膜层放大结构示意图；
图3为本发明实施例1中对氧化物薄膜层进行选择性刻蚀后的微观结构示意图；
图4为本发明实施例1中对氧化物薄膜层进行选择性刻蚀过程示意图；
图5为本发明实施例1中对氧化物薄膜层进行选择性刻蚀后的微观结构示意图；
图6为本发明实施例1中对氧化物薄膜层钝化和退火处理后的微观结构示意图；
图7为本发明实施例1中对氧化物薄膜层进行第二次成膜后的结构示意图；
图8为本发明实施例1中形成多晶氧化物有源层后的结构示意图；
附图标记说明：
1.衬底基板；2.栅极；3.绝缘层；4.氧化物薄膜层；5.光刻胶。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
如图1-4所示，本实施例提供一种多晶氧化物薄膜晶体管阵列基板的制备方法，包括以下步骤：
1)在衬底上形成非晶态氧化物薄膜层的步骤；
2)将所述非晶态氧化物薄膜层进行选择性刻蚀的步骤；
3)对经过步骤2的非晶态氧化物薄膜层进行钝化和退火处理；
4)在经过步骤3的氧化物薄膜层上第二次形成氧化物薄膜，通过构图工艺形成有源层沟道；
5)对经过步骤4的有源层沟道进行退火处理，以形成多晶态氧化物沟道。
本实施中通过两步法形成多晶氧化物薄膜晶体管阵列基板的非晶态氧化物薄膜层，克服了现有技术中需要在超高温退火，实现在现有的非晶氧化物薄膜晶体管阵列基板制备工艺制备多晶氧化物薄膜晶体管阵列基板，不需要增加特殊设备和特殊工艺易于实现；同时不需要高温退火，也节降低了能耗。
该非晶态结构中，堆砌不规则的原子会在刻蚀的过程中优先被刻蚀掉，堆砌规则的原子结合能较大，在刻蚀不完全的时候容易残留在生长面，并且刻蚀后原子表面由于氧化还原作用形成大量的悬挂键，处于亚稳定状态。这些密集的规则堆砌的原子堆将生长面分割成无数个规则的堆砌框架，可以使与其结构和大小相匹配的原子在其间进行规整排列，长大成为晶粒。晶体学中把这些晶体的生长中心称之为晶核。
具体地，采用以下步骤在薄膜晶体管阵列基板上形成多晶氧化物薄膜层；
1)在衬底上形成非晶态氧化物薄膜层的步骤；
如图1所示，在衬底基板1上通过构图工艺形成栅极2，在栅极2上形成栅绝缘层3；
接着采用磁控溅射法形成非晶态氧化物薄膜层4；磁控溅射的条件为：功率为5Kw、压强为0.5Pa，氧气含量为30％，温度为室温。应当理解的是，磁控溅射的工艺条件可以在功率为2-8Kw、压强为0.3-0.8Pa，氧气含量为5％-50％的范围内选择。
通过磁控溅射法形成的非晶态氧化物薄膜层的厚度为应当理解的是，通过磁控溅射法形成的非晶态氧化物薄膜层的厚度范围为
2)将所述非晶态氧化物薄膜层进行选择性刻蚀的步骤；
步骤1中形成的氧化物薄膜层为非晶态的，其放大示意图见图2，在非晶态结构中，存在间隔布置的堆砌不规则的原子堆和堆砌规则的原子堆。
由于堆砌不规则的原子堆结合能较小，堆砌规则的原子堆结合能较大；因此，通过选择性的刻蚀可以将堆砌不规则的原子堆刻蚀掉，保留堆砌规则的原子堆；由于堆砌规则的原子堆结合能较大残留在生长面，并且刻蚀后堆砌规则的原子堆的表面由于氧化还原作用形成大量的悬挂键，处于亚稳定状态，更利于再次成膜。
这些密集的规则堆砌的原子堆将生长面分割成无数个规则的堆砌框架，在再次溅射时，可以使与其结构和大小相匹配的原子在其间进行规整排列，长大成为晶粒。
如图3所示，选择性刻蚀的方法可以采用干法刻蚀或湿法刻蚀；通过控制相应的工艺条件将上述的堆砌不规则的原子堆刻蚀掉，保留堆砌规则的原子堆。
具体步骤如图4所示，在氧化物薄膜层上涂覆光刻胶5，通过曝光，显影将栅极4上方的对应的氧化物薄膜层进行选择性刻蚀，图4中黑色圆点部分所代表的不规则的堆砌被刻蚀，白色圆点部分所代表的规则的堆砌被保留。
如图5所示，选择性刻蚀后，在氧化物薄膜层上形成无数个规则的堆砌框架(晶核)，有利于再次成膜。
本实施例以干法刻蚀为例介绍，例如，采用N2(也可以为Ar)气体的等离子体对所述非晶态氧化物薄膜层进行轰击；干法刻蚀的条件为：功率为1500W，压强为2000mTorr，温度为150℃，处理时间为180s。应当理解的是，干法刻蚀的参数范围可以在以下范围中选择：功率为1200-1800W，压强为1500-2500mTorr，温度为120-180℃，处理时间为150s-200s。
应当理解的是，也可以采用湿法刻蚀，例如，采用稀释100倍的酸系刻蚀液，采用刻蚀完全时间(非晶态氧化物薄膜层全部刻蚀掉需要的时间)的50％-90％进行刻蚀(约为10s)，使得10-50％厚度的薄膜层被保留下来。刻蚀中刻蚀液中的强酸(硝酸、硫酸)含量<1％，控制刻蚀速率小于
3)对经过步骤2的非晶态氧化物薄膜层进行钝化和退火处
理；
如图6所示，对选择性刻蚀后形成堆砌规则的原子堆进行钝化和退火处理，增加原子堆表面原子的悬挂键并消除原子堆原子的表面少量的缺陷(部分不规则排布)，形成完全规则堆砌的原子堆(晶核)，这些原子堆在生长面上形成无数个规则的堆砌框架，成为第二次成膜的晶体生长的中心。
钝化处理可以采用等离子体钝化处理；例如，采用N2O等离子体对非晶态氧化物薄膜层进行钝化处理；钝化处理的条件为：功率为1000W，压强为1500mTorr，温度为200℃，处理时间为80s。
应当理解的是，钝化处理参数可以在以下范围选择：功率为800-1200W，压强为1200-1800mTorr，温度为150-250℃，处理时间为50-100s。
经过钝化后进行退火处理，退火处理工艺为在350℃下退火1h。应当理解的是，退火处理工艺可以在以下范围选择300℃-450℃下退火1-2h。
经过钝化和退火处理增加了原子堆表面原子的悬挂键并消除原子堆原子的表面少量的缺陷，有利于第二次成膜。
4)对经过步骤3的非晶态氧化物薄膜层进行第二次成膜；
如图7所示，第二次成膜可以采用磁控溅射法进行；磁控溅射的条件为：功率为8Kw，压强为1.0Pa，氧气含量为40％，温度为室温，成膜速率为(每扫描一次膜层沉积的厚度为)。
应当理解的是，磁控溅射的条件可以在以下范围选择：功率为3-10Kw，压强为0.8-1.2Pa，氧气含量为5-50％，温度为室温，成膜速率小于
控制上述的第二次成膜的工艺条件形成厚度为的非晶态氧化物薄膜层。应当理解的是，非晶态氧化物薄膜层厚度可以为
5)对经过步骤4的非晶态氧化物薄膜层进行退火处理。
在所述的步骤4中所述的退火处理条件为在350℃下，退火2h。通过退火将非晶态氧化物薄膜层形成多晶氧化物薄膜层。
应当理解的是，退火处理工艺可以在以下范围选择300℃-450℃下退火1-2h。
上述通过两步方法形成多晶氧化物薄膜层，两次退火的温度都控制在450℃以下，能够适合现有的薄膜晶体管阵列基板生产工艺，不需要增加设备和工艺步骤。
可选的，图8所示，通过构图工艺在形成多晶氧化物的有源层如。
实施例2
本实施例提供一种多晶氧化物薄膜晶体管阵列基板，所述的多晶氧化物薄膜晶体管阵列基板是采用上述的多晶氧化物薄膜晶体管阵列基板的制备方法制备的。
本实施例提供一种多晶氧化物薄膜晶体管阵列基板能采用常规的薄膜晶体管阵列基板的生产工艺进行生产，不需要增加设备和工艺步骤。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (13)

1.一种多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，包括以下步骤：
1)在衬底上形成非晶态氧化物薄膜层的步骤；
2)将所述非晶态氧化物薄膜层进行选择性刻蚀的步骤；
3)对经过步骤2的非晶态氧化物薄膜层进行钝化和退火处理；
4)在经过步骤3的氧化物薄膜层上第二次形成氧化物薄膜，通过构图工艺形成有源层沟道；
5)对经过步骤4的有源层沟道进行退火处理。
2.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤1中非晶态氧化物薄膜层的厚度为
3.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤1中采用磁控溅射法形成非晶态氧化物薄膜层；磁控溅射的条件为：功率为2-8Kw、压强为0.3-0.8Pa，氧气含量为5％-50％，温度为室温。
4.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤2中将非晶态氧化物薄膜层中堆砌不规则的原子刻蚀去除；保留堆砌规则的原子。
5.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤2中所述的选择性刻蚀为干法刻蚀；采用N2或Ar气体的等离子体对所述非晶态氧化物薄膜层进行轰击；干法刻蚀的条件为：功率为1200-1800W，压强为1500-2500mTorr，温度为120-180℃，处理时间为150-200s。
6.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤2中所述的选择性刻蚀为湿法刻蚀；采用能腐蚀非晶态氧化物薄膜层的酸性刻蚀溶液进行刻蚀，使得在刻蚀区域有10-50％非晶态氧化物薄膜层被保留。
7.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤3中所述的退火处理为在300-450℃下退火1-2h。
8.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤3中所述的钝化处理为等离子体钝化处理。
9.根据权利要求8所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，所述的等离子体钝化处理为采用N2O等离子体对非晶态氧化物薄膜层进行钝化处理；所述钝化处理的条件为：功率为800-1200W，压强为1200-1800mTorr，温度为150-250℃，处理时间为50-100s。
10.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤4中采用磁控溅射法在经过步骤3的氧化物薄膜层上第二次形成氧化物薄膜；所述磁控溅射的条件为：功率为3-10Kw，压强为0.8-1.2Pa，氧气含量为5-50％，温度为室温，成膜速率小于
11.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤4中第二次形成的氧化物薄膜的厚度为
12.根据权利要求1所述的多晶氧化物薄膜晶体管阵列基板的制备方法，其特征在于，在所述的步骤5中所述的退火处理条件为在300-450℃下，退火1-2h。
13.一种多晶氧化物薄膜晶体管阵列基板，其特征在于，所述的多晶氧化物薄膜晶体管阵列基板是采用如权利要求1-12任意一项所述的多晶氧化物薄膜晶体管阵列基板的制备方法制备的。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016074427A1 (zh) * 2014-11-13 2016-05-19 京东方科技集团股份有限公司 一种多晶氧化物薄膜晶体管阵列基板及其制备方法
CN107557745A (zh) * 2017-10-31 2018-01-09 君泰创新（北京）科技有限公司 非晶透明导电氧化物薄膜的制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100140609A1 (en) * 2007-03-23 2010-06-10 Koki Yano Semiconductor device, polycrystalline semiconductor thin film, process for producing polycrystalline semiconductor thin film, field effect transistor, and process for producing field effect transistor
US20120205648A1 (en) * 2011-02-10 2012-08-16 Sony Corporation Thin-film transistor, display apparatus and electronic apparatus
CN103700665A (zh) * 2013-12-13 2014-04-02 京东方科技集团股份有限公司 金属氧化物薄膜晶体管阵列基板及其制作方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1998375A3 (en) * 2005-09-29 2012-01-18 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device having oxide semiconductor layer and manufacturing method
SG168450A1 (en) * 2009-08-05 2011-02-28 Sony Corp Thin film transistor
KR101768433B1 (ko) * 2009-12-18 2017-08-16 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 제작 방법
JP6107085B2 (ja) * 2012-11-22 2017-04-05 住友金属鉱山株式会社 酸化物半導体薄膜および薄膜トランジスタ
CN104319262B (zh) * 2014-11-13 2017-02-01 京东方科技集团股份有限公司 一种多晶氧化物薄膜晶体管阵列基板及其制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100140609A1 (en) * 2007-03-23 2010-06-10 Koki Yano Semiconductor device, polycrystalline semiconductor thin film, process for producing polycrystalline semiconductor thin film, field effect transistor, and process for producing field effect transistor
US20120205648A1 (en) * 2011-02-10 2012-08-16 Sony Corporation Thin-film transistor, display apparatus and electronic apparatus
CN103700665A (zh) * 2013-12-13 2014-04-02 京东方科技集团股份有限公司 金属氧化物薄膜晶体管阵列基板及其制作方法、显示装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016074427A1 (zh) * 2014-11-13 2016-05-19 京东方科技集团股份有限公司 一种多晶氧化物薄膜晶体管阵列基板及其制备方法
US9583517B2 (en) 2014-11-13 2017-02-28 Boe Technology Group Co., Ltd. Polycrystalline oxide thin-film transistor array substrate and method of manufacturing same
CN107557745A (zh) * 2017-10-31 2018-01-09 君泰创新（北京）科技有限公司 非晶透明导电氧化物薄膜的制备方法

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