CN104241275A - High-voltage electrostatic discharge (ESD) protection circuit of self-triggering piled substrate-trigger silicon controlled rectifier (STSCR)-laterally diffused metal oxide semiconductors (LDMOS) - Google Patents
High-voltage electrostatic discharge (ESD) protection circuit of self-triggering piled substrate-trigger silicon controlled rectifier (STSCR)-laterally diffused metal oxide semiconductors (LDMOS) Download PDFInfo
- Publication number
- CN104241275A CN104241275A CN201410449412.3A CN201410449412A CN104241275A CN 104241275 A CN104241275 A CN 104241275A CN 201410449412 A CN201410449412 A CN 201410449412A CN 104241275 A CN104241275 A CN 104241275A
- Authority
- CN
- China
- Prior art keywords
- heavily doped
- doped region
- type heavily
- stscr
- ldmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a high-voltage electrostatic discharge (ESD) protection circuit of self-triggering piled substrate-trigger silicon controlled rectifier (STSCR)-laterally diffused metal oxide semiconductors (LDMOS) and belongs to the field of electronic technologies. The protection circuit comprises N STSCR-LDMOS piled units, and each STSCR-LDMOS piled unit comprises an STSCR-LDMOS component and a resistor, wherein N>=2, and N+1 P-type heavily doped regions are further arranged on a substrate to serve as protection rings to be grounded. According to the protection circuit, the piled STSCR-LDMOSs are broken down and triggered through the first STSCR-LDMOS, and maintaining voltage is effectively increased without increasing triggering voltage.
Description
Technical field
The invention belongs to electronic technology field; be specifically related to Electro-static Driven Comb (the ElectroStatic Discharge of semiconductor integrated circuit chip; referred to as ESD) protecting circuit designed technology; espespecially a kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS (be embedded with the Substrate-Trigger Silicon Controlled Rectifier of transverse diffusion metal oxide semiconductor field effect transistor LDMOS, be called for short STSCR-LDMOS).
Background technology
Chip production, encapsulation, test, deposit, in handling process, static discharge (ElectroStatic Discharge, referred to as ESD) is ubiquity as a kind of inevitably natural phenomena.Along with the reduction of integrated circuit technology characteristic size and the development of various advanced technologies, the situation that chip is damaged by ESD phenomenon is more and more general, and relevant research shows, ic failure product 30% all owing to suffering caused by static discharge phenomenon.Therefore, high performance ESD protective device is used to be seemed very important to chip internal circuits protect.
STSCR (Substrate-Trigger Silicon Controlled Rectifier) is one of common ESD protective device, the same with common SCR, has the advantages such as against esd ability is strong.Fig. 1 is the profile of traditional STSCR ESD protective device; as shown in Figure 1, traditional STSCR ESD protective device comprises: P type substrate 101, N-type well region 102, a N-type heavily doped region 106, N-type heavily doped region 103, second, P type heavily doped region 107, first, P type heavily doped region the 105, the 3rd, P type heavily doped region the 104, the 2nd.N-type well region 102, the 2nd N-type heavily doped region 106, P type heavily doped region 105, second and the 3rd P type heavily doped region 107 are positioned on P type substrate 101, and the 2nd P type heavily doped region 105 is between N-type well region 102 and the second N-type heavily doped region 106, second N-type heavily doped region 106 is between the second P type heavily doped region 105 and the 3rd P type heavily doped region 107, first N-type heavily doped region 103 and a P type heavily doped region 104 are positioned on N-type well region 102, and a P type heavily doped region 104 is between the first N-type heavily doped region 103 and the 2nd P type heavily doped region 105.Its endophyte structure comprises a parasitic PNP triode Q
1(being made up of a P type heavily doped region 104, N-type well region 102 and P type substrate 101), a parasitic NPN triode Q
2(being made up of the second N-type heavily doped region 106, P type substrate 101 and N-type well region 102) and the equivalent resistance substrate R between the 2nd P type heavily doped region 105 and the 3rd P type heavily doped region 107 in P type substrate 101.One P type heavily doped region 103 and the first N-type heavily doped region 104 connect anode, and the 2nd P type heavily doped region 105 connects the current potential of P-trig, and the second N-type heavily doped region 106 and the 3rd P type heavily doped region 107 connect negative electrode.When esd pulse appears in anode, if now P-rig end has pulse current injectingt, electric current will through resistance substrate R, and flow to a P type heavily doped region of negative electrode, when electric current is enough large, the pressure drop be added on resistance R makes equivalent triode Q
2emitter junction positively biased, thus open triode Q
2, and Q
2collector current will be Q
1base stage provide electric current, Q
1after conducting, its collector current will be Q
2there is provided base current, final Q
1, Q
2form positive feedback, SCR structure conducting is with ESD electric current of releasing.
STSCR, as the one of SCR, not only has the advantage of SCR heavy current relieving capacity, also has the advantage that trigger voltage is low, is therefore suitable as very much low pressure ESD protective device.But if STSCR is as high-voltage ESD protective device, the low-down ME for maintenance of STSCR can cause it when being used as power clamp, latch-up (breech lock) effect easily to occur, and after ESD has released, power supply continuous discharge, finally burns out device.Therefore, the ME for maintenance how improving STSCR structure becomes the difficult point of STSCR device as high-voltage ESD protective device research.
Summary of the invention
The present invention is directed to the defect that background technology exists; propose a kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS; this circuit is punctured by first STSCR-LDMOS and triggers stacking STSCR-LDMOS, not increasing on the basis of trigger voltage, effectively improves ME for maintenance.
Technical scheme of the present invention is as follows:
A kind of STSCR-LDMOS device, as Fig. 2, comprise P type substrate 201, high-pressure N-shaped well region 202, P type trap zone 203, a N-type heavily doped region 207, N-type heavily doped region 204, second, P type heavily doped region 208, first, P type heavily doped region the 206, the 3rd, P type heavily doped region the 205, the 2nd, polysilicon 209, field oxygen 211 and grid oxygen 212;
Described high-pressure N-shaped well region 202 is positioned on P type substrate 201, first N-type heavily doped region 204, a P type heavily doped region 205 and P type trap zone 203 are positioned on high-pressure N-shaped well region 202, and the 2nd N-type heavily doped region 207, P type heavily doped region 206, second and the 3rd P type heavily doped region 208 are positioned on P type trap zone 203; Polysilicon 209 is on high-pressure N-shaped well region 202 and P type trap zone 203 intersection and between the first P type heavily doped region 205 and the 2nd P type heavily doped region 206, one P type heavily doped region 205 is between the first N-type heavily doped region 204 and the 2nd P type heavily doped region 206, and the second N-type heavily doped region 207 is between the second P type heavily doped region 206 and the 3rd P type heavily doped region 208;
First N-type heavily doped region 204 and a P type heavily doped region 205 are as anode; Second N-type heavily doped region 207 and the 3rd P type heavily doped region 208 are as negative electrode; 2nd P type heavily doped region 206 connects P-trig end; Polysilicon 209, field oxygen 211 and grid oxygen 212 constitute grid.
Adopt the high-voltage ESD protective circuit structure of above-mentioned STSCR-LDMOS device stack as follows:
A kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS, comprise N number of STSCR-LDMOS stackable unit, described STSCR-LDMOS stackable unit comprises an above-mentioned STSCR-LDMOS device and a resistance, wherein N >=2, substrate also have N+1 P type heavily doped region as guard ring ground connection, in described STSCR-LDMOS stackable unit, the anode of first STSCR-LDMOS meets VDD, in described STSCR-LDMOS stackable unit, the negative electrode of (n-1)th STSCR-LDMOS connects the anode of the n-th STSCR-LDMOS, wherein, n=2, 3, N, resistance in described STSCR-LDMOS stackable unit is connected between the P-trig end of two adjacent STSCR-LDMOS, in STSCR-LDMOS stackable unit, the grid of each STSCR-LDMOS is connected with P-trig end, in described STSCR-LDMOS stackable unit, first resistance one end connects P-trig end and the grid of first STSCR-LDMOS, in described STSCR-LDMOS stackable unit, N number of resistance one end connects N-1 resistance, the P-trig end of N number of STSCR-LDMOS and grid, the other end connects negative electrode and the ground of N number of STSCR-LDMOS.
Further, in described STSCR-LDMOS stackable unit, N number of resistance can remove.
When the number N of described STSCR-LDMOS stackable unit is 2, technical scheme of the present invention is as follows:
A kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS, as shown in Figure 3, comprise P type substrate 301, first high-pressure N-shaped well region 302, second high-pressure N-shaped well region 303, one P type heavily doped region 306, 2nd P type heavily doped region 308, 3rd P type heavily doped region 310, 4th P type heavily doped region 313, 5th P type heavily doped region 314, 6th P type heavily doped region 316, 7th P type heavily doped region 318, 8th P type heavily doped region 321, 9th P type heavily doped region 322, first N-type heavily doped region 307, second N-type heavily doped region 311, 3rd N-type heavily doped region 315, 4th N-type heavily doped region 320, first resistance 312, second resistance 319, first oxygen 323, second oxygen 324, first grid oxygen 325, second gate oxygen 326, first polysilicon 309, second polysilicon 317,
The one high-pressure N-shaped well region 302 in P type heavily doped region, P type heavily doped region the 314, the 9th, P type heavily doped region the 306, the 5th 322, first and the second high-pressure N-shaped well region 303 are positioned on P type substrate 201, wherein the first high-pressure N-shaped well region 302 is between the first P type heavily doped region 306 and the 5th P type heavily doped region 314, and the second high-pressure N-shaped well region 303 is between the 5th P type heavily doped region 314 and the 9th P type heavily doped region 322;
First N-type heavily doped region 307, the 2nd P type heavily doped region 308 and the first P type trap zone 304 are positioned on the first high-pressure N-shaped well region 302,3rd N-type heavily doped region 311, P type heavily doped region 310, second and the 4th P type heavily doped region 313 are positioned on the first P type trap zone 304,2nd P type heavily doped region 308 is between the first N-type heavily doped region 307 and the 3rd P type heavily doped region 310, and the second N-type heavily doped region 311 is between the 3rd P type heavily doped region 310 and the 4th P type heavily doped region 313;
3rd N-type heavily doped region 315, the 6th P type heavily doped region 316 and the second P type trap zone 305 are positioned on the second high-pressure N-shaped well region 303,7th N-type heavily doped region 320, P type heavily doped region the 318, the 4th and the 8th P type heavily doped region 321 are positioned on the second P type trap zone 305,6th P type heavily doped region 316 is between the 3rd N-type heavily doped region 315 and the 7th P type heavily doped region 318, and the 4th N-type heavily doped region 320 is between the 7th P type heavily doped region 318 and the 8th P type heavily doped region 321;
Wherein the first high-pressure N-shaped well region 302 and on structure jointly constitute STSCR-LDMOS1, first N-type heavily doped region 307 and the 2nd P type heavily doped region 308 form anode, negative electrode is made in second N-type heavily doped region 311 and the 4th P type heavily doped region 313,3rd P type heavily doped region 310 is P-trig end, and the first polysilicon 309, first oxygen 323 and first grid oxygen 325 form grid;
Second high-pressure N-shaped well region 303 and on structure jointly constitute STSCR-LDMOS2,3rd N-type heavily doped region 315 and the 6th P type heavily doped region 316 form anode, 4th N-type heavily doped region 320 and the 8th P type heavily doped region 321 form negative electrode, 7th P type heavily doped region 318 is P-trig end, and the second polysilicon 317, second oxygen 324 and second gate oxygen 326 form grid;
The anode of STSCR-LDMOS1 meets VDD, and the negative electrode of STSCR-LDMOS1 connects the anode of STSCR-LDMOS2, the minus earth of STSCR-LDMOS2; The P-trig end of the first resistance 312 1 termination STSCR-LDMOS1 and grid, the P-trig end of another termination second resistance 319, STSCR-LDMOS2 and grid; The P-trig end of the second resistance 319 1 termination first resistance 312, STSCR-LDMOS2 and grid, the other end connects negative electrode and the ground of STSCR-LDMOS2; One P type heavily doped region 322, P type heavily doped region the 314, the 9th, P type heavily doped region the 306, the 5th is as guard ring ground connection.
Further, described second resistance 319 can remove.
Beneficial effect of the present invention is: the trigger voltage of described esd protection circuit depends primarily on the puncture voltage of first STSCR-LDMOS device of stacked structure; and ME for maintenance increases exponentially along with the stacking number of STSCR-LDMOS; thus while available protecting internal circuit, again reduce the risk of esd protection circuit generation latch-up.
Accompanying drawing explanation
Fig. 1 is existing STSCR ESD protective device generalized section;
Fig. 2 is the generalized section of STSCR ESD protective device provided by the invention;
Fig. 3 is the stacking electrical block diagrams of the embodiment of the present invention 1 two STSCR-LDMOS;
Fig. 4 is the stacking equivalent circuit diagrams of the embodiment of the present invention 1 two STSCR-LDMOS;
Fig. 5 is the equivalent circuit diagram of the high-voltage ESD protective circuit from the stacking STSCR-LDMOS of triggering provided by the invention;
Fig. 6 is the I-V curvilinear mold graphoid of the STSCR-LDMOS of the stacking number of difference provided by the invention;
Fig. 7 is the equivalent circuit diagram of the embodiment of the present invention 2.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
The invention provides a kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS.This circuit is punctured by first STSCR-LDMOS and triggers stacking STSCR-LDMOS, not increasing on the basis of trigger voltage, is effectively increased exponentially by ME for maintenance.
Embodiment 1:
The structural representation of the high-voltage ESD protective circuit from the stacking STSCR-LDMOS of triggering that Fig. 3 provides for the present embodiment.A kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS, as shown in Figure 3, comprise P type substrate 301, first high-pressure N-shaped well region 302, second high-pressure N-shaped well region 303, one P type heavily doped region 306, 2nd P type heavily doped region 308, 3rd P type heavily doped region 310, 4th P type heavily doped region 313, 5th P type heavily doped region 314, 6th P type heavily doped region 316, 7th P type heavily doped region 318, 8th P type heavily doped region 321, 9th P type heavily doped region 322, first N-type heavily doped region 307, second N-type heavily doped region 311, 3rd N-type heavily doped region 315, 4th N-type heavily doped region 320, first resistance 312, second resistance 319, first oxygen 323, second oxygen 324, first grid oxygen 325, second gate oxygen 326, first polysilicon 309, second polysilicon 317,
The one high-pressure N-shaped well region 302 in P type heavily doped region, P type heavily doped region the 314, the 9th, P type heavily doped region the 306, the 5th 322, first and the second high-pressure N-shaped well region 303 are positioned on P type substrate 201, wherein the first high-pressure N-shaped well region 302 is between the first P type heavily doped region 306 and the 5th P type heavily doped region 314, and the second high-pressure N-shaped well region 303 is between the 5th P type heavily doped region 314 and the 9th P type heavily doped region 322;
First N-type heavily doped region 307, the 2nd P type heavily doped region 308 and the first P type trap zone 304 are positioned on the first high-pressure N-shaped well region 302,3rd N-type heavily doped region 311, P type heavily doped region 310, second and the 4th P type heavily doped region 313 are positioned on the first P type trap zone 304,2nd P type heavily doped region 308 is between the first N-type heavily doped region 307 and the 3rd P type heavily doped region 310, and the second N-type heavily doped region 311 is between the 3rd P type heavily doped region 310 and the 4th P type heavily doped region 313;
3rd N-type heavily doped region 315, the 6th P type heavily doped region 316 and the second P type trap zone 305 are positioned on the second high-pressure N-shaped well region 303,7th N-type heavily doped region 320, P type heavily doped region the 318, the 4th and the 8th P type heavily doped region 321 are positioned on the second P type trap zone 305,6th P type heavily doped region 316 is between the 3rd N-type heavily doped region 315 and the 7th P type heavily doped region 318, and the 4th N-type heavily doped region 320 is between the 7th P type heavily doped region 318 and the 8th P type heavily doped region 321;
Wherein the first high-pressure N-shaped well region 302 and on structure jointly constitute STSCR-LDMOS1, first N-type heavily doped region 307 and the 2nd P type heavily doped region 308 form anode, negative electrode is made in second N-type heavily doped region 311 and the 4th P type heavily doped region 313,3rd P type heavily doped region 310 is P-trig end, and the first polysilicon 309, first oxygen 323 and first grid oxygen 325 form grid;
Second high-pressure N-shaped well region 303 and on structure jointly constitute STSCR-LDMOS2,3rd N-type heavily doped region 315 and the 6th P type heavily doped region 316 form anode, 4th N-type heavily doped region 320 and the 8th P type heavily doped region 321 form negative electrode, 7th P type heavily doped region 318 is P-trig end, and the second polysilicon 317, second oxygen 324 and second gate oxygen 326 form grid;
The anode of STSCR-LDMOS1 meets VDD, and the negative electrode of STSCR-LDMOS1 connects the anode of STSCR-LDMOS2, the minus earth of STSCR-LDMOS2; The P-trig end of the first resistance 312 1 termination STSCR-LDMOS1 and grid, the P-trig end of another termination second resistance 319, STSCR-LDMOS2 and grid; The P-trig end of the second resistance 319 1 terminating resistor 312, STSCR-LDMOS2 and grid, the other end connects negative electrode and the ground of STSCR-LDMOS2; One P type heavily doped region 322, P type heavily doped region the 314, the 9th, P type heavily doped region the 306, the 5th is as guard ring ground connection.
What embodiment 1 provided from the operation principle of the high-voltage ESD protective circuit triggering stacking STSCR-LDMOS is:
Fig. 4 is the stacking equivalent circuit diagram of two STSCR-LDMOS: comprise resistance 312 and 319, dead resistance 401,402,403 and 404, parasitic transistor Q
3, Q
4, Q
5and Q
6.Wherein, dead resistance 401 is the first P type trap zone 304 equivalent resistance, and dead resistance 402 is the first high-pressure N-shaped well region 302 equivalent resistance, and dead resistance 403 is the second high-pressure N-shaped well region 303 equivalent resistance, and dead resistance 404 is the second P type trap zone 305 equivalent resistance; Parasitic-PNP transistor Q
3be made up of the 2nd high-pressure N-shaped well region 302 in P type heavily doped region 308, first and the first P type trap zone 304, parasitic NPN transistor Q
4be made up of the second N-type heavily doped region 311, first P type trap zone 304 and the first high-pressure N-shaped well region 302, parasitic-PNP transistor Q
5be made up of the 6th high-pressure N-shaped well region 303 in P type heavily doped region 316, second and the second P type trap zone 305, NPN Q
6transistor is made up of the 4th N-type heavily doped region 320, second P type trap zone 305 and the second high-pressure N-shaped well region 303.
As can be seen from Figure 4, first P-trig end is connected, so the take-off potential of first P-trig point is zero with ground by resistance 312 and 319.So when anode has esd pulse, parasitic transistor Q
3collector junction first puncture, Q
3open, will there is less snapback phenomenon in I-V curve, Q
3electric current will flow through resistance 312,319 and dead resistance 404, therefore resistance 319 will produce pressure drop, when voltage is more than Q
6during the voltage of emitter junction positively biased, Q
6open, Q
6electronic current will from anode through transistor Q
3, resistance 401,403 and transistor Q
6flow to ground.When the pressure drop on resistance 403 is more than Q
5during the voltage of emitter junction positively biased, Q
5open, Q
5and Q
6form positive feedback, second endoparasitic SCR of STSCR-LDMOS opens; When the pressure drop on resistance 401 is more than Q
4during the voltage of emitter junction positively biased, Q
4open, Q
3and Q
4form positive feedback, first endoparasitic SCR of STSCR-LDMOS opens.After two endoparasitic SCR open, will there is the larger snapback phenomenon of second time in I-V curve, reach the object of ESD electric current of releasing.And the ME for maintenance of protective circuit is the ME for maintenance sum of the STSCR-LDMOS of two series connection, thus improve ME for maintenance, the effective risk reducing generation latch-up.
Embodiment 2:
As shown in Figure 7, the present embodiment, on the basis of embodiment 1, eliminates the second resistance 319.The present embodiment is identical with the operation principle of embodiment 1.
Embodiment 2 removes resistance 319, makes Q
3circuit current after puncturing all flows through resistance 404, can increase the opening speed of STSCR-LDMOS.
Fig. 5 is the equivalent circuit diagram of the high-voltage ESD protective circuit from the stacking STSCR-LDMOS of triggering provided by the invention.The present invention can, by stacking more STSCR-LDMOS stackable unit 501, make ME for maintenance increase considerably, the more effective generation preventing latch-up.
Fig. 6 gives the I-V curvilinear mold graphoid of the stacking number of different STSCR-LDMOS, and as can be seen from the figure, along with the increase of stacking number, puncture voltage increases 80V from 70V, and ME for maintenance increases 25V from 6.5V, and ME for maintenance adds about four times.Therefore the high-voltage ESD protective circuit from the stacking STSCR-LDMOS of triggering provided by the invention is not significantly increasing on the basis of trigger voltage, effectively increased exponentially by ME for maintenance, thus the effective risk reducing generation latch-up.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and replacement, these improve and replace and also should be considered as protection scope of the present invention.
Claims (3)
1. a STSCR-LDMOS device, comprises P type substrate (201), high-pressure N-shaped well region (202), P type trap zone (203), a P type heavily doped region (205), the 2nd P type heavily doped region (206), the 3rd P type heavily doped region (208), the first N-type heavily doped region (204), the second N-type heavily doped region (207), polysilicon (209), field oxygen (211) and grid oxygen (212);
Described high-pressure N-shaped well region (202) is positioned on P type substrate (201), first N-type heavily doped region (204), a P type heavily doped region (205) and P type trap zone (203) are positioned on high-pressure N-shaped well region (202), and the 2nd P type heavily doped region (206), the second N-type heavily doped region (207) and the 3rd P type heavily doped region (208) are positioned on P type trap zone (203); Polysilicon (209) to be positioned on high-pressure N-shaped well region (202) and P type trap zone (203) intersection and to be positioned between a P type heavily doped region (205) and the 2nd P type heavily doped region (206), one P type heavily doped region (205) is positioned between the first N-type heavily doped region (204) and the 2nd P type heavily doped region (206), and the second N-type heavily doped region (207) is positioned between the 2nd P type heavily doped region (206) and the 3rd P type heavily doped region (208);
First N-type heavily doped region (204) and a P type heavily doped region (205) are as anode; Second N-type heavily doped region (207) and the 3rd P type heavily doped region (208) are as negative electrode; 2nd P type heavily doped region (206) connects P-trig end; Polysilicon (209), field oxygen (211) and grid oxygen (212) constitute grid.
2. one kind comprises the high-voltage ESD protective circuit from the stacking STSCR-LDMOS of triggering of the STSCR-LDMOS device of claim 1, comprise N number of STSCR-LDMOS stackable unit, described STSCR-LDMOS stackable unit comprises a STSCR-LDMOS device as claimed in claim 1 and a resistance, wherein N >=2, substrate also have N+1 P type heavily doped region as guard ring ground connection, in described STSCR-LDMOS stackable unit, the anode of first STSCR-LDMOS meets VDD, in described STSCR-LDMOS stackable unit, the negative electrode of (n-1)th STSCR-LDMOS connects the anode of the n-th STSCR-LDMOS, wherein, n=2, 3, N, resistance in described STSCR-LDMOS stackable unit is connected between the P-trig end of two adjacent STSCR-LDMOS, in STSCR-LDMOS stackable unit, the grid of each STSCR-LDMOS is connected with P-trig end, in described STSCR-LDMOS stackable unit, first resistance one end connects P-trig end and the grid of first STSCR-LDMOS, in described STSCR-LDMOS stackable unit, N number of resistance one end connects N-1 resistance, the P-trig end of N number of STSCR-LDMOS and grid, the other end connects negative electrode and the ground of N number of STSCR-LDMOS.
3. the high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS according to claim 2, it is characterized in that, as N=2, the described high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS comprises P type substrate (301), the first high-pressure N-shaped well region (302), second high-pressure N-shaped well region (303), one P type heavily doped region (306), 2nd P type heavily doped region (308), 3rd P type heavily doped region (310), 4th P type heavily doped region (313), 5th P type heavily doped region (314), 6th P type heavily doped region (316), 7th P type heavily doped region (318), 8th P type heavily doped region (321), 9th P type heavily doped region (322), first N-type heavily doped region (307), second N-type heavily doped region (311), 3rd N-type heavily doped region (315), 4th N-type heavily doped region (320), first resistance (312), second resistance (319), first oxygen (323), second oxygen (324), first grid oxygen (325), second gate oxygen (326), first polysilicon (309), second polysilicon (317),
One P type heavily doped region (306), the 5th P type heavily doped region (314), the 9th P type heavily doped region (322), the first high-pressure N-shaped well region (302) and the second high-pressure N-shaped well region (303) are positioned on P type substrate (201), wherein the first high-pressure N-shaped well region (302) is positioned between a P type heavily doped region (306) and the 5th P type heavily doped region (314), and the second high-pressure N-shaped well region (303) is positioned between the 5th P type heavily doped region (314) and the 9th P type heavily doped region (322);
First N-type heavily doped region (307), 2nd P type heavily doped region (308) and the first P type trap zone (304) are positioned on the first high-pressure N-shaped well region (302), 3rd P type heavily doped region (310), second N-type heavily doped region (311) and the 4th P type heavily doped region (313) are positioned on the first P type trap zone (304), 2nd P type heavily doped region (308) is positioned between the first N-type heavily doped region (307) and the 3rd P type heavily doped region (310), second N-type heavily doped region (311) is positioned between the 3rd P type heavily doped region (310) and the 4th P type heavily doped region (313),
3rd N-type heavily doped region (315), 6th P type heavily doped region (316) and the second P type trap zone (305) are positioned on the second high-pressure N-shaped well region (303), 7th P type heavily doped region (318), 4th N-type heavily doped region (320) and the 8th P type heavily doped region (321) are positioned on the second P type trap zone (305), 6th P type heavily doped region (316) is positioned between the 3rd N-type heavily doped region (315) and the 7th P type heavily doped region (318), 4th N-type heavily doped region (320) is positioned between the 7th P type heavily doped region (318) and the 8th P type heavily doped region (321),
Wherein the first high-pressure N-shaped well region (302) and on structure jointly constitute STSCR-LDMOS1, first N-type heavily doped region (307) and the 2nd P type heavily doped region (308) composition anode, negative electrode is made in second N-type heavily doped region (311) and the 4th P type heavily doped region (313), 3rd P type heavily doped region (310) is P-trig end, the first polysilicon (309), first oxygen (323) and first grid oxygen (325) composition grid;
Second high-pressure N-shaped well region (303) and on structure jointly constitute STSCR-LDMOS2,3rd N-type heavily doped region (315) and the 6th P type heavily doped region (316) composition anode, 4th N-type heavily doped region (320) and the 8th P type heavily doped region (321) composition negative electrode, 7th P type heavily doped region (318) is P-trig end, the second polysilicon (317), second oxygen (324) and second gate oxygen (326) composition grid;
The anode of STSCR-LDMOS1 meets VDD, and the negative electrode of STSCR-LDMOS1 connects the anode of STSCR-LDMOS2, the minus earth of STSCR-LDMOS2; The P-trig end of the first resistance (312) one termination STSCR-LDMOS1 and grid, the P-trig end of another termination second resistance (319), STSCR-LDMOS2 and grid; The P-trig end of the second resistance (319) one termination first resistance (312), STSCR-LDMOS2 and grid, the other end connects negative electrode and the ground of STSCR-LDMOS2; One P type heavily doped region (306), the 5th P type heavily doped region (314), the 9th P type heavily doped region (322) are as guard ring ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410449412.3A CN104241275B (en) | 2014-09-04 | 2014-09-04 | From triggering stacking STSCR LDMOS high-voltage ESD protective circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410449412.3A CN104241275B (en) | 2014-09-04 | 2014-09-04 | From triggering stacking STSCR LDMOS high-voltage ESD protective circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104241275A true CN104241275A (en) | 2014-12-24 |
| CN104241275B CN104241275B (en) | 2017-04-05 |
Family
ID=52229073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410449412.3A Active CN104241275B (en) | 2014-09-04 | 2014-09-04 | From triggering stacking STSCR LDMOS high-voltage ESD protective circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104241275B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241276A (en) * | 2014-09-04 | 2014-12-24 | 电子科技大学 | High-voltage electrostatic discharge(ESD) protection circuit for stacked substrate-trigger silicon controlled rectier (STSCR) and laterally diffused metal oxide semiconductors (LDMOSs) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258814B (en) * | 2013-05-15 | 2015-07-29 | 电子科技大学 | LDMOS SCR device is used in a kind of integrated circuit (IC) chip ESD protection |
| CN103730462B (en) * | 2014-01-20 | 2016-03-02 | 江南大学 | A kind of ESD self-protection device with the LDMOS-SCR structure of high maintenance electric current strong robustness |
| CN104241276B (en) * | 2014-09-04 | 2017-05-10 | 电子科技大学 | High-voltage electrostatic discharge(ESD) protection circuit for stacked substrate-trigger silicon controlled rectier (STSCR) and laterally diffused metal oxide semiconductors (LDMOSs) |
-
2014
- 2014-09-04 CN CN201410449412.3A patent/CN104241275B/en active Active
Non-Patent Citations (1)
| Title |
|---|
| FEI MA: "High Holding Voltage SCR-LDMOS Stacking", 《IEEE ELECTRON DEVICE LETTERS》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241276A (en) * | 2014-09-04 | 2014-12-24 | 电子科技大学 | High-voltage electrostatic discharge(ESD) protection circuit for stacked substrate-trigger silicon controlled rectier (STSCR) and laterally diffused metal oxide semiconductors (LDMOSs) |
| CN104241276B (en) * | 2014-09-04 | 2017-05-10 | 电子科技大学 | High-voltage electrostatic discharge(ESD) protection circuit for stacked substrate-trigger silicon controlled rectier (STSCR) and laterally diffused metal oxide semiconductors (LDMOSs) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104241275B (en) | 2017-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104269402A (en) | High-voltage ESD protective circuit with stacked SCR-LDMOS | |
| CN103633087B (en) | A kind of strong anti-breech lock controlled LIGBT device with ESD defencive function | |
| CN102142440B (en) | Thyristor device | |
| CN102569360A (en) | Bidirectional triode thyristor based on diode auxiliary triggering | |
| CN102263102A (en) | Backward diode-triggered thyristor for electrostatic protection | |
| CN103354236A (en) | Silicon-controlled transient voltage inhibitor with embedded Zener diode structure | |
| CN104269401A (en) | Novel ESD protection device based on SCR structure | |
| CN103165600B (en) | A kind of esd protection circuit | |
| CN104241274A (en) | Both-way ESD protection device based on transverse PNP structure | |
| CN104241276B (en) | High-voltage electrostatic discharge(ESD) protection circuit for stacked substrate-trigger silicon controlled rectier (STSCR) and laterally diffused metal oxide semiconductors (LDMOSs) | |
| CN103390618B (en) | The controllable silicon Transient Voltage Suppressor that embedded gate grounding NMOS triggers | |
| CN102034814B (en) | Electrostatic discharge protective device | |
| CN102544068B (en) | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes | |
| CN102693980B (en) | A kind of controllable silicon ESD-protection structure of low trigger voltage | |
| CN105895631B (en) | A kind of high-voltage LDMOS electrostatic protection circuit structure | |
| CN105428353A (en) | High-voltage ESD protective device provided with fin type LDMOS structure | |
| CN104241275A (en) | High-voltage electrostatic discharge (ESD) protection circuit of self-triggering piled substrate-trigger silicon controlled rectifier (STSCR)-laterally diffused metal oxide semiconductors (LDMOS) | |
| CN102244076B (en) | Electrostatic discharge protective device for radio frequency integrated circuit | |
| CN102569295B (en) | Bidirectional thyristor device based on capacitor-assisted trigger | |
| CN102544066B (en) | Bidirectional controllable silicon device based on assistant triggering of NPN-type triodes | |
| CN103972233B (en) | A kind of turned off SCR device with latch-up immunity | |
| CN103545310A (en) | PNPN type ESD protective device and ESD protective circuit | |
| CN107579065A (en) | A kind of high maintenance voltage thyristor electrostatic protection device | |
| CN106876388A (en) | A kind of ghyristor circuit for prevention at radio-frequency port electrostatic discharge protective | |
| CN103730458A (en) | Silicon controlled rectifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |