CN104241275B - From triggering stacking STSCR LDMOS high-voltage ESD protective circuits - Google Patents
From triggering stacking STSCR LDMOS high-voltage ESD protective circuits Download PDFInfo
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Abstract
The invention provides a kind of high-voltage ESD protective circuit from triggering stacking STSCR LDMOS, belongs to electronic technology field.Including N number of STSCR LDMOS stackable units, the STSCR LDMOS stackable units include a STSCR LDMOS device and a resistance, wherein N >=2, and on substrate, also N+1 p-type heavily doped region is grounded as protection ring.The circuit punctures and triggers stacking STSCR LDMOS by first STSCR LDMOS, on the basis of trigger voltage is not increased, effectively increases maintenance voltage.
Description
Technical field
The invention belongs to electronic technology field, and in particular to the Electro-static Driven Comb of semiconductor integrated circuit chip
(ElectroStatic Discharge, referred to as ESD) protecting circuit designed technology, it is espespecially a kind of from triggering stacking STSCR-
LDMOS (is embedded with the Substrate-Trigger of transverse diffusion metal oxide semiconductor field effect transistor LDMOS
Silicon Controlled Rectifier, abbreviation STSCR-LDMOS) high-voltage ESD protective circuit.
Background technology
Chip production, encapsulation, test, storage, in handling process, static discharge (ElectroStatic Discharge,
Referred to as ESD) generally existing as a kind of inevitable natural phenomena.With the reduction of integrated circuit technology characteristic size
With the development of various advanced technologies, the situation that chip is damaged by ESD event is more and more universal, and relevant research shows, integrated
The 30% of circuit malfunction product is all due to being subjected to caused by static discharge phenomenon.Therefore, using high performance ESD protection device
Part is protected by seeming particularly significant to chip internal circuits.
STSCR (Substrate-Trigger Silicon Controlled Rectifier) is common ESD protections
One of device, as common SCR, has the advantages that anti-ESD abilities are strong.Fig. 1 is cuing open for traditional STSCR ESD protective devices
Face figure, as shown in figure 1, traditional STSCR ESD protective devices include：P type substrate 101, N-type well region 102, the first p-type are heavily doped
Miscellaneous area 104, the second p-type heavily doped region 105, the 3rd p-type heavily doped region 107, the first N-type heavily doped region 103, the second N-type are heavily doped
Miscellaneous area 106.N-type well region 102, the second p-type heavily doped region 105, the second N-type heavily doped region 106 and the 3rd p-type heavily doped region 107
On P type substrate 101, and the second p-type heavily doped region 105 be located at N-type well region 102 and the second N-type heavily doped region 106 it
Between, the second N-type heavily doped region 106 is located between the second p-type heavily doped region 105 and the 3rd p-type heavily doped region 107, the first N-type weight
Doped region 103 and the first p-type heavily doped region 104 are located on N-type well region 102, and the first p-type heavily doped region 104 is located at the first N-type
Between heavily doped region 103 and the second p-type heavily doped region 105.Its endophyte structure includes parasitic PNP triode Q1(by
First p-type heavily doped region 104, N-type well region 102 and P type substrate 101 are constituted), a parasitic NPN audion Q2(by the second N-type
Heavily doped region 106, P type substrate 101 and N-type well region 102 are constituted) and the second p-type heavily doped region 105 and the 3rd p-type heavy doping
Equivalent substrate resistance R between area 107 in P type substrate 101.First p-type heavily doped region 103 and the first N-type heavily doped region 104 connect
Anode, the second p-type heavily doped region 105 connect the current potential of P-trig, the second N-type heavily doped region 106 and the 3rd p-type heavily doped region 107
Connect negative electrode.When esd pulse occurs in anode, if now P-rig ends have electric current to inject, electric current will be flowed through resistance substrate R
To the first p-type heavily doped region of negative electrode, when electric current is sufficiently large, the pressure drop being added on resistance R causes equivalent audion Q2Send out
Knot positively biased is penetrated, so as to open audion Q2, and Q2Collector current will be Q1Base stage provide electric current, Q1Its current collection after conducting
Electrode current will be Q2Base current, final Q are provided1、Q2Positive feedback is formed, SCR structure is turned on ESD electric currents of releasing.
The one kind of STSCR as SCR, not only has the advantages that SCR heavy current relieving capacities, also low with trigger voltage
Advantage, therefore it is highly suitable as low pressure ESD protective device.If however, STSCR is used as high-voltage ESD protective device, STSCR
Low-down maintenance voltage can cause which to be susceptible to latch-up (breech lock) effect when as power clamp, release in ESD
After the completion of, power supply continuous discharge finally burns out device.Therefore, the maintenance voltage for how improving STSCR structures becomes STSCR
Difficult point of the device as high-voltage ESD protective device research.
The content of the invention
A kind of defect that the present invention is present for background technology, it is proposed that high pressure ESD from triggering stacking STSCR-LDMOS
Protection circuit, the circuit puncture and trigger stacking STSCR-LDMOS by first STSCR-LDMOS, are not increasing triggering electricity
On the basis of pressure, maintenance voltage is effectively increased.
Technical scheme is as follows：
A kind of STSCR-LDMOS devices, such as Fig. 2, including P type substrate 201, high-pressure N-shaped well region 202, P type trap zone 203,
One p-type heavily doped region 205, the second p-type heavily doped region 206, the 3rd p-type heavily doped region 208, the first N-type heavily doped region 204,
Two N-type heavily doped regions 207, polysilicon 209, field oxygen 211 and grid oxygen 212；
The high-pressure N-shaped well region 202 is located on P type substrate 201, the first N-type heavily doped region 204, the first p-type heavy doping
Area 205 and P type trap zone 203 are located on high-pressure N-shaped well region 202, the second p-type heavily doped region 206, the second N-type heavily doped region 207
It is located on P type trap zone 203 with the 3rd p-type heavily doped region 208；Polysilicon 209 is located at high-pressure N-shaped well region 202 and P type trap zone
On 203 intersections and be located between the first p-type heavily doped region 205 and the second p-type heavily doped region 206, the first p-type heavily doped region
205 are located between the first N-type heavily doped region 204 and the second p-type heavily doped region 206, and the second N-type heavily doped region 207 is located at the 2nd P
Between type heavily doped region 206 and the 3rd p-type heavily doped region 208；
First N-type heavily doped region 204 and the first p-type heavily doped region 205 are used as anode；Second N-type heavily doped region 207 and
Three p-type heavily doped regions 208 are used as negative electrode；Second p-type heavily doped region 206 connects P-trig ends；Polysilicon 209, field oxygen 211 and grid oxygen
212 constitute grid.
High-voltage ESD protective circuit structure using above-mentioned STSCR-LDMOS device stacks is as follows：
A kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS, including N number of STSCR-LDMOS stacking lists
Unit, the STSCR-LDMOS stackable units include an above-mentioned STSCR-LDMOS device and a resistance, wherein N >=2, substrate
It is upper to also have N+1 p-type heavily doped region to be grounded as protection ring, first STSCR- in the STSCR-LDMOS stackable units
The anode of LDMOS meets VDD, and in the STSCR-LDMOS stackable units, the negative electrode of (n-1)th STSCR-LDMOS connects n-th
The anode of STSCR-LDMOS, wherein, n=2,3 ..., N, the resistance in the STSCR-LDMOS stackable units are connected to two
Between the P-trig ends of adjacent STSCR-LDMOS, in STSCR-LDMOS stackable units the grid of each STSCR-LDMOS and
P-trig ends are connected, the P- of first resistance one end connection, first STSCR-LDMOS in the STSCR-LDMOS stackable units
Trig ends and grid, in the STSCR-LDMOS stackable units, n-th resistance one end connects the N-1 resistance, n-th
The P-trig ends of STSCR-LDMOS and grid, the negative electrode and ground of other end connection n-th STSCR-LDMOS.
Further, in the STSCR-LDMOS stackable units, n-th resistance can remove.
When number N of the STSCR-LDMOS stackable units is 2, technical scheme is as follows：
A kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS, as shown in figure 3, including P type substrate 301,
First high-pressure N-shaped well region 302, the second high-pressure N-shaped well region 303, the first p-type heavily doped region 306, the second p-type heavily doped region 308,
3rd p-type heavily doped region 310, the 4th p-type heavily doped region 313, the 5th p-type heavily doped region 314, the 6th p-type heavily doped region 316,
7th p-type heavily doped region 318, the 8th p-type heavily doped region 321, the 9th p-type heavily doped region 322, the first N-type heavily doped region 307,
Second N-type heavily doped region 311, the 3rd N-type heavily doped region 315, the 4th N-type heavily doped region 320, first resistor 312, second resistance
319th, first oxygen, 323, second oxygen 324, the first grid oxygen 325, the second grid oxygen 326, the first polysilicon 309, the second polysilicon
317；
First p-type heavily doped region 306, the 5th p-type heavily doped region 314, the 9th p-type heavily doped region 322, first are high-pressure N-shaped
Well region 302 and the second high-pressure N-shaped well region 303 are located on P type substrate 201, wherein the first high-pressure N-shaped well region 302 is located at a P
Between type heavily doped region 306 and the 5th p-type heavily doped region 314, the second high-pressure N-shaped well region 303 is located at the 5th p-type heavily doped region
314 and the 9th between p-type heavily doped region 322；
First N-type heavily doped region 307, the second p-type heavily doped region 308 and the first P type trap zone 304 are high-pressure N-shaped positioned at first
On well region 302, the 3rd p-type heavily doped region 310, the second N-type heavily doped region 311 and the 4th p-type heavily doped region 313 are located at first
On P type trap zone 304, the second p-type heavily doped region 308 be located at the first N-type heavily doped region 307 and the 3rd p-type heavily doped region 310 it
Between, the second N-type heavily doped region 311 is located between the 3rd p-type heavily doped region 310 and the 4th p-type heavily doped region 313；
3rd N-type heavily doped region 315, the 6th p-type heavily doped region 316 and the second P type trap zone 305 are high-pressure N-shaped positioned at second
On well region 303, the 7th p-type heavily doped region 318, the 4th N-type heavily doped region 320 and the 8th p-type heavily doped region 321 are located at second
On P type trap zone 305, the 6th p-type heavily doped region 316 be located at the 3rd N-type heavily doped region 315 and the 7th p-type heavily doped region 318 it
Between, the 4th N-type heavily doped region 320 is located between the 7th p-type heavily doped region 318 and the 8th p-type heavily doped region 321；
Wherein first high-pressure N-shaped well region 302 and its on structure collectively constituted STSCR-LDMOS1, the first N-type is heavily doped
Miscellaneous area 307 and the composition anode of the second p-type heavily doped region 308, the second N-type heavily doped region 311 and the 4th p-type heavily doped region 313 do
Into negative electrode, the 3rd p-type heavily doped region 310 is 325 groups of P-trig ends, the first oxygen 323 of polysilicon 309, first and the first grid oxygen
Into grid；
Second high-pressure N-shaped well region 303 and its on structure collectively constituted STSCR-LDMOS2, the 3rd N-type heavily doped region
315 and the composition anode of the 6th p-type heavily doped region 316, the 4th N-type heavily doped region 320 and the 8th p-type heavily doped region 321 constitute the moon
Pole, the 7th p-type heavily doped region 318 are P-trig ends, the second oxygen 324 of polysilicon 317, second and the composition grid of the second grid oxygen 326
Pole；
The anode of STSCR-LDMOS1 meets VDD, and the negative electrode of STSCR-LDMOS1 meets the anode of STSCR-LDMOS2, STSCR-
The minus earth of LDMOS2；The P-trig ends of the termination STSCR-LDMOS1 of first resistor 312 1 and grid, another termination second are electric
Resistance 319, the P-trig ends of STSCR-LDMOS2 and grid；Second resistance 319 1 terminates first resistor 312, STSCR-LDMOS2
P-trig ends and grid, the other end connection STSCR-LDMOS2 negative electrode and ground；First p-type heavily doped region 306, the 5th p-type
Heavily doped region 314, the 9th p-type heavily doped region 322 are grounded as protection ring.
Further, the second resistance 319 can be removed.
Beneficial effects of the present invention are：The trigger voltage of the esd protection circuit depends primarily on the first of stacked structure
The breakdown voltage of individual STSCR-LDMOS devices, and maintenance voltage is increased exponentially with the stacking number of STSCR-LDMOS, from
And while effective protection internal circuit, the risk that esd protection circuit occurs latch-up is reduced again.
Description of the drawings
Fig. 1 is existing STSCR ESD protective devices generalized section；
The generalized section of the STSCR ESD protective devices that Fig. 2 is provided for the present invention；
Fig. 3 is the electrical block diagram of 1 two STSCR-LDMOS stackings of the embodiment of the present invention；
Fig. 4 is the equivalent circuit diagram of 1 two STSCR-LDMOS stackings of the embodiment of the present invention；
The equivalent circuit diagram of the high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS that Fig. 5 is provided for the present invention；
The I-V curve simulation drawing of the STSCR-LDMOS of the different stacking numbers that Fig. 6 is provided for the present invention；
Equivalent circuit diagrams of the Fig. 7 for the embodiment of the present invention 2.
Specific embodiment
With reference to the accompanying drawings and examples, describe technical scheme in detail：
The invention provides a kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS.The circuit passes through first
Individual STSCR-LDMOS punctures and triggers stacking STSCR-LDMOS, on the basis of trigger voltage is not increased, will effectively maintain
Voltage is increased exponentially.
Embodiment 1：
The structural representation of the high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS that Fig. 3 is provided for the present embodiment
Figure.A kind of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS, as shown in figure 3, including P type substrate 301, first is high
Pressure N-type well region 302, the second high-pressure N-shaped well region 303, the first p-type heavily doped region 306, the second p-type heavily doped region 308, the 3rd p-type
Heavily doped region 310, the 4th p-type heavily doped region 313, the 5th p-type heavily doped region 314, the 6th p-type heavily doped region 316, the 7th p-type
Heavily doped region 318, the 8th p-type heavily doped region 321, the 9th p-type heavily doped region 322, the first N-type heavily doped region 307, the second N-type
Heavily doped region 311, the 3rd N-type heavily doped region 315, the 4th N-type heavily doped region 320, first resistor 312, second resistance 319,
One oxygen, 323, second oxygen 324, the first grid oxygen 325, the second grid oxygen 326, the first polysilicon 309, the second polysilicon 317；
First p-type heavily doped region 306, the 5th p-type heavily doped region 314, the 9th p-type heavily doped region 322, first are high-pressure N-shaped
Well region 302 and the second high-pressure N-shaped well region 303 are located on P type substrate 201, wherein the first high-pressure N-shaped well region 302 is located at a P
Between type heavily doped region 306 and the 5th p-type heavily doped region 314, the second high-pressure N-shaped well region 303 is located at the 5th p-type heavily doped region
314 and the 9th between p-type heavily doped region 322；
First N-type heavily doped region 307, the second p-type heavily doped region 308 and the first P type trap zone 304 are high-pressure N-shaped positioned at first
On well region 302, the 3rd p-type heavily doped region 310, the second N-type heavily doped region 311 and the 4th p-type heavily doped region 313 are located at first
On P type trap zone 304, the second p-type heavily doped region 308 be located at the first N-type heavily doped region 307 and the 3rd p-type heavily doped region 310 it
Between, the second N-type heavily doped region 311 is located between the 3rd p-type heavily doped region 310 and the 4th p-type heavily doped region 313；
3rd N-type heavily doped region 315, the 6th p-type heavily doped region 316 and the second P type trap zone 305 are high-pressure N-shaped positioned at second
On well region 303, the 7th p-type heavily doped region 318, the 4th N-type heavily doped region 320 and the 8th p-type heavily doped region 321 are located at second
On P type trap zone 305, the 6th p-type heavily doped region 316 be located at the 3rd N-type heavily doped region 315 and the 7th p-type heavily doped region 318 it
Between, the 4th N-type heavily doped region 320 is located between the 7th p-type heavily doped region 318 and the 8th p-type heavily doped region 321；
Wherein first high-pressure N-shaped well region 302 and its on structure collectively constituted STSCR-LDMOS1, the first N-type is heavily doped
Miscellaneous area 307 and the composition anode of the second p-type heavily doped region 308, the second N-type heavily doped region 311 and the 4th p-type heavily doped region 313 do
Into negative electrode, the 3rd p-type heavily doped region 310 is 325 groups of P-trig ends, the first oxygen 323 of polysilicon 309, first and the first grid oxygen
Into grid；
Second high-pressure N-shaped well region 303 and its on structure collectively constituted STSCR-LDMOS2, the 3rd N-type heavily doped region
315 and the composition anode of the 6th p-type heavily doped region 316, the 4th N-type heavily doped region 320 and the 8th p-type heavily doped region 321 constitute the moon
Pole, the 7th p-type heavily doped region 318 are P-trig ends, the second oxygen 324 of polysilicon 317, second and the composition grid of the second grid oxygen 326
Pole；
The anode of STSCR-LDMOS1 meets VDD, and the negative electrode of STSCR-LDMOS1 meets the anode of STSCR-LDMOS2, STSCR-
The minus earth of LDMOS2；The P-trig ends of the termination STSCR-LDMOS1 of first resistor 312 1 and grid, another termination second are electric
Resistance 319, the P-trig ends of STSCR-LDMOS2 and grid；The P- of 319 1 terminating resistor 312, STSCR-LDMOS2 of second resistance
Trig ends and grid, the negative electrode and ground of other end connection STSCR-LDMOS2；First p-type heavily doped region 306, the 5th p-type are heavily doped
Miscellaneous area 314, the 9th p-type heavily doped region 322 are grounded as protection ring.
The operation principle of high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS that embodiment 1 is provided is：
Fig. 4 is the equivalent circuit diagram of two STSCR-LDMOS stackings：Including resistance 312 and 319, dead resistance 401,
402nd, 403 and 404, parasitic transistor Q3、Q4、Q5And Q6.Wherein, dead resistance 401 is 304 equivalent resistance of the first P type trap zone,
Dead resistance 402 is 302 equivalent resistance of the first high-pressure N-shaped well region, and dead resistance 403 is 303 equivalent electric of the second high-pressure N-shaped well region
Resistance, dead resistance 404 are 305 equivalent resistance of the second P type trap zone；Parasitic-PNP transistor Q3By the second p-type heavily doped region 308,
One high-pressure N-shaped well region 302 and the first P type trap zone 304 are constituted, parasitic NPN transistor Q4By the second N-type heavily doped region 311, first
P type trap zone 304 and the first high-pressure N-shaped well region 302 are constituted, parasitic-PNP transistor Q5It is high by the 6th p-type heavily doped region 316, second
Pressure N-type well region 303 and the second P type trap zone 305 are constituted, NPN Q6Transistor is by the 4th N-type heavily doped region 320, the second P type trap zone
305 and second high-pressure N-shaped well region 303 constitute.
Figure 4, it is seen that first P-trig end is connected with ground by resistance 312 and 319, so first P-
The take-off potential of trig points is zero.So when anode has esd pulse, parasitic transistor Q3Collector junction puncture first, Q3Open
Open, I-V curve will occur less snapback phenomenons, Q3Electric current will flow through resistance 312,319 and dead resistance 404, because
Pressure drop will be produced on this resistance 319, when voltage is more than Q6During the voltage of emitter junction positively biased, Q6Open, Q6Electronic current will be from
Anode Jing transistor Q3, resistance 401,403 and transistor Q6Flow direction ground.When the pressure drop on resistance 403 is more than Q5Emitter junction positively biased
During voltage, Q5Open, Q5And Q6Positive feedback is formed, the endoparasitic SCR of second STSCR-LDMOS is opened；When on resistance 401
Pressure drop more than Q4During the voltage of emitter junction positively biased, Q4Open, Q3And Q4Positive feedback is formed, is posted inside first STSCR-LDMOS
Raw SCR is opened.After two endoparasitic SCR are opened, I-V curve will occur second larger snapback phenomenon,
Reach the purpose of ESD electric currents of releasing.And the maintenance voltage of protection circuit be two series connection STSCR-LDMOS maintenance voltage it
With so as to improve maintenance voltage, there is the risk of latch-up in effectively reduction.
Embodiment 2：
As shown in fig. 7, the present embodiment is on the basis of embodiment 1, second resistance 319 is eliminated.The present embodiment and enforcement
The operation principle of example 1 is identical.
Embodiment 2 removes resistance 319 so that Q3Circuit current after puncturing all flows through resistance 404, can increase
The opening speed of STSCR-LDMOS.
The equivalent circuit diagram of the high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS that Fig. 5 is provided for the present invention.
The present invention can increase considerably maintenance voltage, more effectively by stacking more STSCR-LDMOS stackable units 501
Prevent the generation of latch-up.
Fig. 6 gives the I-V curve simulation drawing that different STSCR-LDMOS stack number, it can be seen that with heap
The increase of folded number, breakdown voltage increase 80V from 70V, and maintenance voltage increases 25V from 6.5V, and maintenance voltage increases
About four times are added.Therefore the high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS that the present invention is provided significantly is not increasing
Plus on the basis of trigger voltage, effectively maintenance voltage is increased exponentially, so as to effectively reduce the wind that latch-up occurs
Danger.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, on the premise of without departing from the technology of the present invention principle, some improvement and replacement can also be made, these improve and replace
Also should be regarded as protection scope of the present invention.
Claims (3)
1. a kind of STSCR-LDMOS devices, including P type substrate (201), high-pressure N-shaped well region (202), P type trap zone (203), first
P-type heavily doped region (205), the second p-type heavily doped region (206), the 3rd p-type heavily doped region (208), the first N-type heavily doped region
(204), the second N-type heavily doped region (207), polysilicon (209), field oxygen (211) and grid oxygen (212)；
, on P type substrate (201), the first N-type heavily doped region (204), the first p-type are heavily doped for the high-pressure N-shaped well region (202)
Miscellaneous area (205) and P type trap zone (203) on high-pressure N-shaped well region (202), the second p-type heavily doped region (206), the second N-type
Heavily doped region (207) and the 3rd p-type heavily doped region (208) are on P type trap zone (203)；Polysilicon (209) is positioned at high pressure N
On type well region (202) and P type trap zone (203) intersection and positioned at the first p-type heavily doped region (205) and the second p-type heavy doping
Between area (206), the first p-type heavily doped region (205) is positioned at the first N-type heavily doped region (204) and the second p-type heavily doped region
(206), between, the second N-type heavily doped region (207) is positioned at the second p-type heavily doped region (206) and the 3rd p-type heavily doped region (208)
Between；
First N-type heavily doped region (204) and the first p-type heavily doped region (205) are used as anode；Second N-type heavily doped region (207) and
3rd p-type heavily doped region (208) is used as negative electrode；Second p-type heavily doped region (206) connects P-trig ends；Polysilicon (209), field oxygen
And grid oxygen (212) constitutes grid (211).
2. the high pressure ESD protections from triggering stacking STSCR-LDMOS of a kind of STSCR-LDMOS devices comprising claim 1
Circuit, including N number of STSCR-LDMOS stackable units, the STSCR-LDMOS stackable units include such as claim 1 institute
The STSCR-LDMOS devices stated and a resistance, wherein N >=2, also have N+1 p-type heavily doped region to connect as protection ring on substrate
Ground, in the STSCR-LDMOS stackable units, the anode of first STSCR-LDMOS connects VDD, the STSCR-LDMOS stackings
In unit, the negative electrode of (n-1)th STSCR-LDMOS connects the anode of n-th STSCR-LDMOS, wherein, n=2,3 ..., N, institute
State the resistance in STSCR-LDMOS stackable units to be connected between the P-trig ends of two adjacent STSCR-LDMOS, STSCR-
In LDMOS stackable units, the grid of each STSCR-LDMOS is connected with P-trig ends, in the STSCR-LDMOS stackable units
First resistance one end connects P-trig ends and the grid of first STSCR-LDMOS, in the STSCR-LDMOS stackable units
N-th resistance one end connects the N-1 resistance, the P-trig ends of n-th STSCR-LDMOS and grid, other end connection n-th
The negative electrode and ground of STSCR-LDMOS.
3. according to claim 2 from the high-voltage ESD protective circuit for triggering stacking STSCR-LDMOS, it is characterised in that when
During N=2, the high-voltage ESD protective circuit from triggering stacking STSCR-LDMOS includes P type substrate (301), and first is high-pressure N-shaped
Well region (302), the second high-pressure N-shaped well region (303), the first p-type heavily doped region (306), the second p-type heavily doped region (308), the 3rd
P-type heavily doped region (310), the 4th p-type heavily doped region (313), the 5th p-type heavily doped region (314), the 6th p-type heavily doped region
(316), the 7th p-type heavily doped region (318), the 8th p-type heavily doped region (321), the 9th p-type heavily doped region (322), the first N-type
Heavily doped region (307), the second N-type heavily doped region (311), the 3rd N-type heavily doped region (315), the 4th N-type heavily doped region (320),
First resistor (312), second resistance (319), first oxygen (323), second oxygen (324), the first grid oxygen (325), second gate
Oxygen (326), the first polysilicon (309), the second polysilicon (317)；
First p-type heavily doped region (306), the 5th p-type heavily doped region (314), the 9th p-type heavily doped region (322), the first high pressure N
Type well region (302) and the second high-pressure N-shaped well region (303) on P type substrate (201), wherein the first high-pressure N-shaped well region
(302) between the first p-type heavily doped region (306) and the 5th p-type heavily doped region (314), the second high-pressure N-shaped well region (303)
Between the 5th p-type heavily doped region (314) and the 9th p-type heavily doped region (322)；
First N-type heavily doped region (307), the second p-type heavily doped region (308) and the first P type trap zone (304) are positioned at the first high pressure N
On type well region (302), the 3rd p-type heavily doped region (310), the second N-type heavily doped region (311) and the 4th p-type heavily doped region
(313) on the first P type trap zone (304), the second p-type heavily doped region (308) positioned at the first N-type heavily doped region (307) and
Between 3rd p-type heavily doped region (310), the second N-type heavily doped region (311) is positioned at the 3rd p-type heavily doped region (310) and the 4th P
Between type heavily doped region (313)；
3rd N-type heavily doped region (315), the 6th p-type heavily doped region (316) and the second P type trap zone (305) are positioned at the second high pressure N
On type well region (303), the 7th p-type heavily doped region (318), the 4th N-type heavily doped region (320) and the 8th p-type heavily doped region
(321) on the second P type trap zone (305), the 6th p-type heavily doped region (316) positioned at the 3rd N-type heavily doped region (315) and
Between 7th p-type heavily doped region (318), the 4th N-type heavily doped region (320) is positioned at the 7th p-type heavily doped region (318) and the 8th P
Between type heavily doped region (321)；
Wherein first high-pressure N-shaped well region (302) and its on structure collectively constituted STSCR-LDMOS1, the first N-type heavy doping
Area (307) and the second p-type heavily doped region (308) composition anode, the second N-type heavily doped region (311) and the 4th p-type heavily doped region
(313) make negative electrode, the 3rd p-type heavily doped region (310) is P-trig ends, the first polysilicon (309), first oxygen (323) and
First grid oxygen (325) constitutes grid；
Second high-pressure N-shaped well region (303) and its on structure collectively constituted STSCR-LDMOS2, the 3rd N-type heavily doped region
(315) and the 6th p-type heavily doped region (316) composition anode, the 4th N-type heavily doped region (320) and the 8th p-type heavily doped region
(321) constitute negative electrode, the 7th p-type heavily doped region (318) is P-trig ends, the second polysilicon (317), second oxygen (324) and
Second grid oxygen (326) constitutes grid；
The anode of STSCR-LDMOS1 meets VDD, and the negative electrode of STSCR-LDMOS1 meets the anode of STSCR-LDMOS2, STSCR-
The minus earth of LDMOS2；The P-trig ends of the termination STSCR-LDMOS1 of first resistor (312) one and grid, another termination second
Resistance (319), the P-trig ends of STSCR-LDMOS2 and grid；Termination first resistor of second resistance (319) (312),
The P-trig ends of STSCR-LDMOS2 and grid, the negative electrode and ground of other end connection STSCR-LDMOS2；First p-type heavily doped region
(306), the 5th p-type heavily doped region (314), the 9th p-type heavily doped region (322) are grounded as protection ring.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258814A (en) * | 2013-05-15 | 2013-08-21 | 电子科技大学 | LDMOS SCR for protection against integrated circuit chip ESD |
| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN104241276A (en) * | 2014-09-04 | 2014-12-24 | 电子科技大学 | High-voltage electrostatic discharge(ESD) protection circuit for stacked substrate-trigger silicon controlled rectier (STSCR) and laterally diffused metal oxide semiconductors (LDMOSs) |
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| CN103258814A (en) * | 2013-05-15 | 2013-08-21 | 电子科技大学 | LDMOS SCR for protection against integrated circuit chip ESD |
| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN104241276A (en) * | 2014-09-04 | 2014-12-24 | 电子科技大学 | High-voltage electrostatic discharge(ESD) protection circuit for stacked substrate-trigger silicon controlled rectier (STSCR) and laterally diffused metal oxide semiconductors (LDMOSs) |
Non-Patent Citations (1)
| Title |
|---|
| High Holding Voltage SCR-LDMOS Stacking;Fei Ma;《IEEE ELECTRON DEVICE LETTERS》;20130930;第34卷(第9期);第1178-1180页 * |
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