CN104220365A - 腔封装设计 - Google Patents

腔封装设计 Download PDF

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CN104220365A
CN104220365A CN201380018033.2A CN201380018033A CN104220365A CN 104220365 A CN104220365 A CN 104220365A CN 201380018033 A CN201380018033 A CN 201380018033A CN 104220365 A CN104220365 A CN 104220365A
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distance piece
semiconductor devices
mems
substrate
crystalline substance
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E·奥克斯
J·S·萨尔蒙
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Robert Bosch GmbH
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0074—3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0077—Other packages not provided for in groups B81B7/0035 - B81B7/0074
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00309—Processes for packaging MEMS devices suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
    • B81C1/0065—Mechanical properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0257—Microphones or microspeakers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0315—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/015—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being integrated on the same substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/07—Interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Micromachines (AREA)
  • Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
  • Pressure Sensors (AREA)

Abstract

一种半导体器件。所述器件包括具有电气轨迹的基底、安装到所述基底上的MEMS裸晶和半导体芯片中的至少一个和间隔件。所述间隔件具有连接到所述基底的第一端并且包括耦合至所述电气轨迹的电气互连。所述至少一个MEMS裸晶和半导体芯片包含在所述间隔件中。所述间隔件和基底形成包含所述至少一个MEMS裸晶和半导体芯片的腔。当半导体器件经由间隔件的第二端安装到电路板时，所述腔形成声学容积。

Description

腔封装设计
相关申请
本发明要求2012年3月29日提交的共同待决美国临时专利申请61/617,519号的权益，该申请的整个内容在本文中通过引用合并。
技术领域
本发明的实施例涉及用于MEMS麦克风、压力传感器应用和类似的应用的半导体封装。更特别地，本发明的一个实施例涉及用于产生适合于与MEMS麦克风一起使用的超低高度半导体器件封装的方法。
发明内容
在一个实施例中，本发明提供一种半导体器件。该器件包括具有电气轨迹的基底、安装到所述基底上的MEMS裸晶和半导体芯片中的至少一个和间隔件。所述间隔件具有连接到所述基底的第一端并且包括耦合到电气轨迹的电气互连。所述至少一个MEMS裸晶和半导体芯片包含在所述间隔件内。间隔件和基底形成包含所述至少一个MEMS裸晶和半导体芯片的腔。当半导体器件经由间隔件的第二端安装到电路板时，所述腔形成声学容积。
在另一实施例中，本发明提供一种制造半导体器件的方法。该方法包括：产生具有多个电气轨迹的基底；将MEMS裸晶和半导体芯片中的至少一个安装到基底上，所述MEMS裸晶和半导体芯片中的至少一个电耦合至所述多个电气轨迹；和将间隔件的第一端安装到基底，所述间隔件包括多个电气互连，所述多个电气互连电耦合至所述多个电气轨迹。所述基底和所述间隔件形成腔，并且所述MEMS裸晶和半导体芯片中的至少一个定位在所述腔内。
通过考虑具体说明和附图，本发明的各方面将变得明显。
附图说明
图1a是超低高度半导体器件封装的第一实施例的俯视图。
图lb是超低高度半导体器件封装的第一实施例的侧视图。
图lc是超低高度半导体器件封装的第一实施例的仰视图。
图2是超低高度半导体器件封装的第一实施例的剖视图。
图3是超低高度半导体器件封装的第一实施例的平面图。
图4a是超低高度半导体器件封装的第二实施例的俯视图。
图4b是超低高度半导体器件封装的第二实施例的侧视图。
图4c是超低高度半导体器件封装的第二实施例的仰视图。
图5是超低高度半导体器件封装的第二实施例的剖视图。
图6是超低高度半导体器件封装的第二实施例的平面图。
具体实施方式
在详细描述本发明的任何实施例之前，需要理解的是，本发明不局限于应用到在下面的说明中陈述的或者在下面的附图中示出的部件的具体构造和布置。本发明能够实现其他实施例并且能够以各种方式实践或执行。
图la、图lb、图lc、图2和图3示出具有开口腔构造的半导体器件100的封装设计，所述封装设计产生用于一个或多个半导体芯片102和/或MEMS裸晶105和相关的电气互连110(例如，通过引线接合或倒装芯片)的穴。组件的顶部基底115用作用于半导体芯片102和MEMS裸晶105的安装面以及用于电气信号的路由表面。在一个实施例中，顶部基底115是印刷电路板(PCB)。间隔件环120被接合到封装100的顶部基底115以形成提高半导体裸晶100和如果可适用在最终的PCB组件的表面上方的相关引线接合的壁，对在裸晶的顶面上的引线接合和/或电路提供间隙。除了形成封装壁以外，间隔件120提供用于向封装底部路由电气信号的媒介(也就是电气互连110)和在裸晶与最终的装配车辆(也就是用户PCB)之间的应变消除。在一个实施例中，间隔件120由PCB材料制成。间隔件环120的底面具有提供封装与最终组件之间电气互连的导电表面。
在一些实施例中，间隔件120围绕电气互连110形成。在顶部基底115上的电气路径(例如，轨迹)被电耦合至在间隔件120中的电气互连110。当半导体器件100被安装到制造商的电路板上时，在制造商的电路板上的电气连接经由电气互连110电耦合至半导体芯片102和MEMS裸晶105。在其他实施例中，电气互连110被在间隔件120的表面上路由。
如图3所示，半导体器件100包括间隔件/互连130。腔135通过间隔件120在器件100中形成。在半导体器件100的一些实施例中，端口140(例如，MEMS麦克风的声音端口)被穿过顶部基底115形成。
半导体器件100直接安装到制造商的电路板上并且省去对第二基底(也就是，在腔135之上)的需要。当半导体器件100被安装到制造商的电路板时，半导体器件100形成用于MEMS麦克风的必要的声学容积并且半导体器件100提供比前述可利用的封装更薄的封装。
在需要被密封的腔的应用中，密封剂(例如，倒装芯片底部填充材料、裸晶附接环氧树脂等)可以被围绕封装的周边分配或者在封装壁之下分配以在周围环境与封装的内部腔之间产生气密密封。密封的替代实施例还可以包括与焊料附接工艺兼容的围绕周边的有图案的金属环。在这种情况下，为了屏蔽的目的，环还可以被用来构成法拉第笼。这样的笼需要在封装的顶部表面上增加铜板或有图案的金属同时需要顶侧铜与在封装底部上的密封环之间的适当连接。在需要腔暴露到空气压力的情况下(诸如，压力传感器)，能够部分地移除密封环，这允许在封装与PCB(封装安装在所述PCB上)之间形成空气通道。可以通过使用在封装壁内的切口或在封装的顶面内的孔产生更大的空气通道。
在图4a、图4b、图4c、图5和图6中示出的封装的替代实施例包括接合在腔135之上的盖145以形成气密密封。盖145利用薄膜(例如，聚酰亚胺胶带、聚酰亚胺)形成，所述薄膜被图案化具有开口从而露出嵌入间隔件环中的电气焊盘110。所述实施例改进需要限定的后部容积或密封的腔135的器件的可测试性，允许半导体器件100与MEMS麦克风一起被测试而无需安装到电路板上。仍然，所示的实施例保持前述的薄的轮廓。
因此，除其他事项以外，本发明提供一种具有超薄轮廓的用于承载一个或多个芯片和/或MEMS裸晶的半导体器件。

Claims (15)

1.一种半导体器件，包括：
具有电气轨迹的基底；
安装到所述基底上的MEMS裸晶和半导体芯片中的至少一个；和
具有连接到所述基底的第一端并且包括耦合到所述电气轨迹的电气互连的间隔件，并且所述MEMS裸晶和半导体芯片中的所述至少一个包含在所述间隔件内；
其中所述间隔件和基底形成包含所述MEMS裸晶和半导体芯片中的所述至少一个的腔，当所述半导体器件经由所述间隔件的第二端安装到电路板时，所述腔形成声学容积，所述第二端与所述第一端相反。
2.根据权利要求1所述的半导体器件，其中所述电气互连被嵌入所述间隔件中。
3.根据权利要求1所述的半导体器件，还包括安装到所述间隔件的所述第二端上的盖。
4.根据权利要求3所述的半导体器件，其中所述基底、所述间隔件和所述盖形成声学容积。
5.根据权利要求4所述的半导体器件，其中当MEMS麦克风被安装在所述腔内时，所述半导体器件能够被测试而不需要将所述半导体器件安装到电路板。
6.根据权利要求1所述的半导体器件，其中所述间隔件的高度仅仅是覆盖MEMS裸晶和半导体芯片中的所述至少一个所需的那么大。
7.根据权利要求1所述的半导体器件，其中所述间隔件的高度仅仅是形成适当声学容积所需的那么大。
8.一种制造半导体器件的方法，所述方法包括：
产生具有多个电气轨迹的基底；
将MEMS裸晶和半导体芯片中的至少一个安装到基底上，所述MEMS裸晶和半导体芯片中的所述至少一个电耦合至所述多个电气轨迹；和
将间隔件的第一端安装到基底，所述间隔件包括多个电气互连，所述多个电气互连电耦合至所述多个电气轨迹；
其中所述基底和所述间隔件形成腔，所述MEMS裸晶和半导体芯片中的所述至少一个定位在所述腔内。
9.根据权利要求8所述的方法，其中所述电气互连被嵌入所述间隔件中。
10.根据权利要求8所述的方法，还包括将盖安装到间隔件的与所述第一端相反的第二端上。
11.根据权利要求10所述的方法，其中所述基底、所述间隔件和所述盖形成声学容积。
12.根据权利要求11所述的方法，其中当MEMS麦克风被安装在所述腔内时，所述半导体器件能够被测试而不需要将所述半导体器件安装到电路板。
13.根据权利要求8所述的方法，其中所述间隔件的高度仅仅是覆盖MEMS裸晶与半导体芯片中的所述至少一个所需的那么大。
14.根据权利要求8所述的方法，其中所述间隔件的高度仅仅是形成适当声学容积所需的那么大。
15.根据权利要求8所述的方法，其中当所述半导体器件经由所述间隔件的与所述第一端相反的第二端安装到电路板时，MEMS裸晶和半导体芯片中的所述至少一个通过所述多个电气互连电耦合至电路板。
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US20130256815A1 (en) 2013-10-03
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