CN104158500A - Radio frequency power amplifier - Google Patents
Radio frequency power amplifier Download PDFInfo
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- CN104158500A CN104158500A CN201310175719.4A CN201310175719A CN104158500A CN 104158500 A CN104158500 A CN 104158500A CN 201310175719 A CN201310175719 A CN 201310175719A CN 104158500 A CN104158500 A CN 104158500A
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Abstract
The invention discloses a radio frequency power amplifier integrated on a same chip. The radio frequency power amplifier comprises two stages of amplifying circuits. An automatic biasing cascode CMOS amplifier is adopted in the first-stage amplifying circuit, and a SiGe HBT connected through a common emitter is adopted in the second-stage amplifying circuit. According to the radio frequency power amplifier, the withstand voltage, the isolation and the bandwidth of the circuits can be improved, the voltage swing and working current of the circuits can be improved, the gain and the maximum output power of the circuits can be improved, the frequency performance of the power amplifier can be improved, full-chip integration can be achieved, and accordingly, the integration degree is improved, cost is reduced, and the application is simplified.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of radio-frequency power amplifier.
Background technology
In wireless telecommunication system, need to use radio-frequency power amplifier and wireless signal is received and carry out power amplification.As shown in Figure 1, be existing two-stage radio-frequency power amplifier, comprising:
First order amplifier, by NMOS pipe, M101 forms, the source ground of NMOS pipe M101, radio-frequency input signals RFIN is input to the grid of NMOS pipe M101 by capacitance C101, bias voltage AVDDVB1 is added to the grid of NMOS pipe M101 by inductance L 1, the drain electrode of NMOS pipe M101 connects supply voltage by choke induction L2.
Second level amplifier, by NMOS pipe, M102 forms, the source ground of NMOS pipe M102, the grid of NMOS pipe M102 is connected with the drain electrode of NMOS pipe M101 by isolation capacitance C2, bias voltage AVDDVB2 is added to the grid of NMOS pipe M102 by inductance L 3, the drain electrode of NMOS pipe M102 connects supply voltage by choke induction L4, and the drain electrode of NMOS pipe M102 is exported radio frequency output signal RFOUT after by capacitance C103.
The dual-stage amplifier of existing two-stage radio-frequency power amplifier as shown in Figure 1 all adopts nmos device to realize, and adopts CMOS technique just can realize.Along with the progress of CMOS technique, the high frequency performance of cmos device is improved, and this also makes to adopt the high frequency performance of the existing two-stage radio-frequency power amplifier that CMOS technique realizes to be improved.In field of wireless communication, 2.4GHz frequency range is the common ISM in various countries (Industrial Scientific Medical) frequency range, so the wireless network such as WLAN (wireless local area network), bluetooth, ZigBee all can be operated in 2.4GHz frequency range.So also requirement can keep good service behaviour in 2.4GHz frequency range when radio-frequency power amplifier is applied in above-mentioned wireless network.
Although adopt the high frequency performance of the existing two-stage radio-frequency power amplifier of CMOS technique realization to be improved, but also to radio-frequency power amplifier, some difficulties have been brought simultaneously, as the oxide layer breakdown brownout of cmos device, current driving ability is poor, and substrate coupling is serious etc.In addition, passive device poor performance on sheet, especially the Q value of on-chip inductor is too low, had a strong impact on power amplifier properties, therefore the element such as inductance often adopts sheet external square type, the passive device that is the radio-frequency power amplifier realized of existing CMOS technique often can not be formed on same chip as cmos device as inductance and active device, and the full sheet that can not realize whole radio-frequency power amplifier is integrated.Because inductance need to adopt sheet, manufacture outward, therefore be all integrated in the integrated radio-frequency power amplifier of full sheet on same chip with respect to all building blocks, the cost of existing radio-frequency power amplifier can be very high, and application is also inconvenient.
Except the radio-frequency power amplifier that existing CMOS technique as shown in Figure 1 realizes, existing radio-frequency power amplifier adopts GaAs (GaAs) heterojunction bipolar transistor (HBT) to realize in addition, although GaAs HBT better performances, cannot be integrated with silicon (Si) technique; In field of semiconductor manufacture, only have silicon-based devices could realize large-scale manufacture, and GaAs HBT is owing to cannot realizing the integrated of also silicon technology, therefore cost is very high.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of radio-frequency power amplifier, can improve withstand voltage, isolation and the bandwidth of circuit, can improve voltage swing and the operating current size of circuit, can improve gain and the peak power output of circuit, the frequency performance of device can be improved, thereby the integrated raising of full sheet integrated level can be realized, reduce costs and make application to simplify.
For solving the problems of the technologies described above, radio-frequency power amplifier provided by the invention is integrated on same chip, and described radio-frequency power amplifier comprises: input matching network, first order amplifying circuit, inter-stage matching network, second level amplifying circuit, output matching network, second level biasing circuit.
Described input matching network is connected between radio-frequency (RF) signal input end and the input of described first order amplifying circuit; Described inter-stage matching network is connected between the output of described first order amplifying circuit and the input of described second level amplifying circuit; Described output matching network is connected between the output and radiofrequency signal output of described second level amplifying circuit.
Described first order amplifying circuit comprises the cascade cmos amplifier of automatic biasing, between the output of described cascade cmos amplifier and supply voltage, be connected with first order choke induction, the common grid cmos amplifier that the auto bias circuit of described cascade cmos amplifier is described cascade cmos amplifier provides the first bias voltage.
Described second level amplifying circuit comprises the first germanium silicon (SiGe) heterojunction bipolar transistor that common emitter connects, the grounded emitter of described the first SiGe heterojunction bipolar transistor, between the collector electrode of described the first SiGe heterojunction bipolar transistor and supply voltage, be connected with second level choke induction, the base stage of described the first SiGe heterojunction bipolar transistor is as the input of described second level amplifying circuit, and the collector electrode of described the first SiGe heterojunction bipolar transistor is as the output of described second level amplifying circuit.
Described second level biasing circuit provides the second bias voltage for described second level amplifying circuit.
Further improve and be, the cascade cmos amplifier of described first order amplifying circuit comprises a NMOS pipe and the 2nd NMOS pipe, the source ground of a described NMOS pipe, the grid of a described NMOS pipe is as the input of described first order amplifying circuit, and the drain electrode of a described NMOS pipe connects the source electrode of described the 2nd NMOS pipe; The grid of a described NMOS pipe is connected with bias voltage source by the first resistance.The drain electrode of described the 2nd NMOS pipe is as the output of described first order amplifying circuit, and described first order choke induction is connected between the drain electrode and supply voltage of described the 2nd NMOS pipe; Between the drain and gate of described the 2nd NMOS pipe, be connected with the second resistance, be connected with the 3rd electric capacity between the grid of described the 2nd NMOS pipe and ground, described supply voltage provides described the first bias voltage by described the second resistance.
Further improving is that described second level biasing circuit comprises: the second SiGe heterojunction bipolar transistor, the 3rd SiGe heterojunction bipolar transistor, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th electric capacity.The collector electrode of described the second SiGe heterojunction bipolar transistor connects supply voltage, described the 3rd resistance is connected between the collector electrode and base stage of described the second SiGe heterojunction bipolar transistor, described the 4th resistance is connected between the emitter of described the second SiGe heterojunction bipolar transistor and the base stage of described the 3rd SiGe heterojunction bipolar transistor, and described the 5th resistance is connected between the emitter of described the second SiGe heterojunction bipolar transistor and the base stage of described the first SiGe heterojunction bipolar transistor.Described the 6th electric capacity is connected between the collector and emitter of described the 3rd SiGe heterojunction bipolar transistor, the base stage of the collector electrode of described the 3rd SiGe heterojunction bipolar transistor and described the second SiGe heterojunction bipolar transistor, the grounded emitter of described the 3rd SiGe heterojunction bipolar transistor.
Further improving is that described input matching network is L-type matching network.
Further improving is that described output matching network is T-shaped matching network.
Further improving is that described inter-stage matching network is T-shaped matching network.
Further improving is to be provided with capacitance between described radio-frequency (RF) signal input end and described input matching network.
Further improving is to be provided with capacitance between described output matching network and described radiofrequency signal output.
Further improving is that described the first SiGe heterojunction bipolar transistor works in AB class state.
The first order of radio-frequency power amplifier of the present invention adopts cascade cmos amplifier, the second level to adopt SiGe HBT amplifier, be that radio-frequency power amplifier of the present invention can adopt SiGe BiCMOS technique to realize, can overcome in prior art the deficiency that adopts separately CMOS technique or adopt separately bipolar approach, make radio-frequency power amplifier of the present invention can be simultaneously in conjunction with the advantage of two kinds of techniques:
1, the amplifier architecture of realizing with respect to MOS transistor of available technology adopting, the cascade cmos amplifier that the first order of the present invention adopts can improve withstand voltage, isolation and the broadband of circuit.
2, the second level of the present invention amplifying circuit adopts the amplifier that SiGe HBT forms, because SiGe HBT has good frequency performance, so can greatly improve the frequency characteristic of circuit; SiGe HBT can also realize large voltage swing and large operating current size simultaneously, can improve gain, current driving ability and the peak power output of circuit.
3, two-stage amplifying circuit of the present invention can be realized and being integrated in same chip by SiGe BiCMOS technique, biasing circuit in circuit, matching network and choke induction can be by realizing at sheet, thereby the full sheet that can realize circuit is integrated, can greatly improve circuit integrated level, reduce costs and make application to simplify.
4, first order amplifying circuit of the present invention adopts the cascade cmos amplifier of automatic biasing, can save a bias voltage, can further reduce inductance use, be conducive to reduce circuit area, cost-saving.
5, the second level biasing circuit of the second level of the present invention amplifying circuit has the feature of self adaptation adjustment and temperature stability, can improve second level amplifying circuit bias voltage stability and improve the performance of circuit.
6, in the wireless telecommunication system that is applied to 2.4GHz that circuit of the present invention can be good.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing two-stage radio-frequency power amplifier;
Fig. 2 is embodiment of the present invention radio-frequency power amplifier.
Embodiment
As shown in Figure 2, be embodiment of the present invention radio-frequency power amplifier.Embodiment of the present invention radio-frequency power amplifier is integrated on same chip, and described radio-frequency power amplifier comprises: input matching network, first order amplifying circuit, inter-stage matching network, second level amplifying circuit, output matching network, second level biasing circuit.
Described input matching network is connected between radio-frequency (RF) signal input end RFIN and the input of described first order amplifying circuit.In the embodiment of the present invention, described input matching network is the L-type matching network being comprised of the first inductance L 1 and the second capacitor C 2, is provided with i.e. the first capacitor C 1 of capacitance between described radio-frequency (RF) signal input end RFIN and described input matching network.In other embodiments, described input matching network can be also T-shaped or π type matching network.
Described inter-stage matching network is connected between the output of described first order amplifying circuit and the input of described second level amplifying circuit.In the embodiment of the present invention, described inter-stage matching network is the T-shaped matching network being comprised of the 4th capacitor C 4, the 5th capacitor C 5 and the 3rd inductance L 3.In other embodiments, described inter-stage matching network can be also L-type or π type matching network.
Described output matching network is connected between the output and radiofrequency signal output RFOUT of described second level amplifying circuit.In the embodiment of the present invention, described output matching network is the T-shaped matching network being comprised of the 5th inductance L 5 and the 7th capacitor C 7, is provided with i.e. the 8th capacitor C 8 of capacitance between described radiofrequency signal output RFOUT and described input matching network.In other embodiments, described input matching network can be also L-type or π type matching network.
Described first order amplifying circuit comprises the cascade cmos amplifier of automatic biasing, between the output of described cascade cmos amplifier and supply voltage AVDD, be connected with first order choke induction L2, the common grid cmos amplifier that the auto bias circuit of described cascade cmos amplifier is described cascade cmos amplifier provides the first bias voltage.Described cascade cmos amplifier can improve withstand voltage, isolation and the broadband of circuit.
In embodiments of the present invention, the cascade cmos amplifier of described first order amplifying circuit comprises a NMOS pipe M1 and the 2nd NMOS pipe M2, a described NMOS pipe M1 is connected to form common-source amplifier structure, and described the 2nd NMOS pipe M2 is connected to form cathode-input amplifier structure.
The source ground AVSS of a described NMOS pipe M1, the grid of a described NMOS pipe M1 is as the input of described first order amplifying circuit, and the drain electrode of a described NMOS pipe M1 connects the source electrode of described the 2nd NMOS pipe M2; The grid of a described NMOS pipe M1 is connected with bias voltage source AVDDVB by the first resistance R 1, this bias voltage source AVDDVB provides the 3rd bias voltage for a described NMOS manages M1, and described bias voltage source AVDDVB need to provide separately to adjust the grid bias of a described NMOS pipe M1.
The drain electrode of described the 2nd NMOS pipe M2 is as the output of described first order amplifying circuit, and described first order choke induction L2 is connected between the drain electrode and supply voltage AVDD of described the 2nd NMOS pipe M2; Between the drain and gate of described the 2nd NMOS pipe M2, be connected with the second resistance R 2, between the grid of described the 2nd NMOS pipe M2 and ground AVSS, be connected with the 3rd capacitor C 3, described supply voltage AVDD provides described the first bias voltage by described the second resistance R 2.As seen from Figure 2, described in the embodiment of the present invention, the 2nd NMOS pipe grid of M2 is identical with the direct voltage of drain electrode, described the first bias voltage is directly provided by described the second resistance R 2 by described supply voltage AVDD, also be that described the first bias voltage provides by the auto bias circuit being comprised of described the second resistance R 2 and described the 3rd capacitor C 3, do not need extra bias voltage, so can save a bias voltage, can further reduce inductance use, be conducive to reduce circuit area, cost-saving.By the effect of described the second resistance R 2 and described the 3rd capacitor C 3, can adjust between the grid leak of a described NMOS pipe M1 and the signal swing between described the 2nd NMOS pipe M2 grid leak both are equated, simultaneously can also optimized circuit performance.Described cascade cmos amplifier is except saving a bias voltage, simultaneously cascodes can improve withstand voltage, with respect to common source structure for amplifying, reduced Miller capacitance, bandwidth is approximately equal to the bandwidth of cathode-input amplifier, than common source amplifying circuit, is greatly improved; The common gate structure of described cascade cmos amplifier has also improved input and output isolation, has reduced the interference between input and output; This cascodes can be amplified voltage and electric current simultaneously simultaneously, and voltage and power can be amplified like this, meets the needs that radio-frequency power amplifies.
Described second level amplifying circuit comprises the first germanium silicon (SiGe) heterojunction bipolar transistor Q1 that common emitter connects, the grounded emitter AVSS of described the first SiGe heterojunction bipolar transistor Q1, between the collector electrode of described the first SiGe heterojunction bipolar transistor Q1 and supply voltage AVDD, be connected with second level choke induction L4, the base stage of described the first SiGe heterojunction bipolar transistor Q1 is as the input of described second level amplifying circuit, and the collector electrode of described the first SiGe heterojunction bipolar transistor Q1 is as the output of described second level amplifying circuit.Described the first SiGe heterojunction bipolar transistor Q1 works in AB class state.Described the first SiGe heterojunction bipolar transistor Q1 is NPN pipe.The second level amplifying circuit that described the first SiGe heterojunction bipolar transistor Q1 forms can make full use of supply voltage AVDD, improves output voltage swing, can have larger electric current amplifying power simultaneously, improves power output.Meanwhile, described the first SiGe heterojunction bipolar transistor Q1 has good frequency performance, thus can greatly improve the frequency characteristic of circuit, and make in the wireless telecommunication system that is applied to 2.4GHz that embodiment of the present invention circuit can be good.
Described second level biasing circuit provides the second bias voltage for described second level amplifying circuit.Described second level biasing circuit comprises: the second SiGe heterojunction bipolar transistor Q2, the 3rd SiGe heterojunction bipolar transistor Q3, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5 and the 6th capacitor C 6.Described the second SiGe heterojunction bipolar transistor Q2 and described the 3rd SiGe heterojunction bipolar transistor Q3 are NPN pipe, the collector electrode of described the second SiGe heterojunction bipolar transistor Q2 connects supply voltage AVDD, described the 3rd resistance R 3 is connected between the collector electrode and base stage of described the second SiGe heterojunction bipolar transistor Q2, described the 4th resistance R 4 is connected between the emitter of described the second SiGe heterojunction bipolar transistor Q2 and the base stage of described the 3rd SiGe heterojunction bipolar transistor Q3, described the 5th resistance R 5 is connected between the emitter of described the second SiGe heterojunction bipolar transistor Q2 and the base stage of described the first SiGe heterojunction bipolar transistor Q1.Described the 6th capacitor C 6 is connected between the collector and emitter of described the 3rd SiGe heterojunction bipolar transistor Q3, the base stage of the collector electrode of described the 3rd SiGe heterojunction bipolar transistor Q3 and described the second SiGe heterojunction bipolar transistor Q2, the grounded emitter AVSS of described the 3rd SiGe heterojunction bipolar transistor Q3.
In the biasing circuit of the described second level, described the 3rd SiGe heterojunction bipolar transistor Q3 and described the first SiGe heterojunction bipolar transistor Q1 are image current source circuit, for described the first SiGe heterojunction bipolar transistor Q1 provides base bias, this biasing makes described the first SiGe heterojunction bipolar transistor Q1 work in AB class state.
Described the second SiGe heterojunction bipolar transistor Q2, described the 3rd SiGe heterojunction bipolar transistor Q3 and described the 5th resistance R 5 can improve temperature stability: when the base current of described the second SiGe heterojunction bipolar transistor Q2 increases because temperature raises, its emitting stage electric current increases, cause the pressure drop of described the 5th resistance R 5 to increase, between the base stage of described the 3rd SiGe heterojunction bipolar transistor Q3 and emitter, voltage Vbe3 increases, the collector current of described the 3rd SiGe heterojunction bipolar transistor Q3 increases, pressure drop in described the 3rd resistance R 3 increases, Vbe2 declines, thereby the base current of described the second SiGe heterojunction bipolar transistor Q2 is reduced, compensated because temperature increases the base current causing and increased.
Described the 6th capacitor C 6 can improve the stability of Vbe1 for shunt capacitance.When input radio frequency large-signal increases, Vbe1 declines to some extent, now has part rf large-signal to be penetrated into biasing circuit, and penetrates PN junction and C6 is coupled to ground by the base of described the second SiGe heterojunction bipolar transistor Q2.Therefore, the base current of described the second SiGe heterojunction bipolar transistor Q2 can increase, thereby causes Vbe2 to decline, and has compensated the decline of Vbe1, makes the base bias voltage of described the first SiGe heterojunction bipolar transistor Q1 keep constant.Described the 4th resistance R 4 can improve the stability of Vbe1 as balance resistance.
The embodiment of the present invention can be good work in 2.4GHz radio band, by to embodiment of the present invention circuit, the simulation result when the 2.4GHz can obtain, its gain reaches 22dB, the about 24dBm of peak power output, power added efficiency now surpasses 35%, S parameter also in good scope.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. a radio-frequency power amplifier, it is characterized in that: radio-frequency power amplifier is integrated on same chip, described radio-frequency power amplifier comprises: input matching network, first order amplifying circuit, inter-stage matching network, second level amplifying circuit, output matching network, second level biasing circuit;
Described input matching network is connected between radio-frequency (RF) signal input end and the input of described first order amplifying circuit; Described inter-stage matching network is connected between the output of described first order amplifying circuit and the input of described second level amplifying circuit; Described output matching network is connected between the output and radiofrequency signal output of described second level amplifying circuit;
Described first order amplifying circuit comprises the cascade cmos amplifier of automatic biasing, between the output of described cascade cmos amplifier and supply voltage, be connected with first order choke induction, the common grid cmos amplifier that the auto bias circuit of described cascade cmos amplifier is described cascade cmos amplifier provides the first bias voltage;
Described second level amplifying circuit comprises the first SiGe heterojunction bipolar transistor that common emitter connects, the grounded emitter of described the first SiGe heterojunction bipolar transistor, between the collector electrode of described the first SiGe heterojunction bipolar transistor and supply voltage, be connected with second level choke induction, the base stage of described the first SiGe heterojunction bipolar transistor is as the input of described second level amplifying circuit, and the collector electrode of described the first SiGe heterojunction bipolar transistor is as the output of described second level amplifying circuit;
Described second level biasing circuit provides the second bias voltage for described second level amplifying circuit.
2. radio-frequency power amplifier as claimed in claim 1, is characterized in that:
The cascade cmos amplifier of described first order amplifying circuit comprises a NMOS pipe and the 2nd NMOS pipe, the source ground of a described NMOS pipe, the grid of a described NMOS pipe is as the input of described first order amplifying circuit, and the drain electrode of a described NMOS pipe connects the source electrode of described the 2nd NMOS pipe; The grid of a described NMOS pipe is connected with bias voltage source by the first resistance;
The drain electrode of described the 2nd NMOS pipe is as the output of described first order amplifying circuit, and described first order choke induction is connected between the drain electrode and supply voltage of described the 2nd NMOS pipe; Between the drain and gate of described the 2nd NMOS pipe, be connected with the second resistance, be connected with the 3rd electric capacity between the grid of described the 2nd NMOS pipe and ground, described supply voltage provides described the first bias voltage by described the second resistance.
3. radio-frequency power amplifier as claimed in claim 1, is characterized in that: described second level biasing circuit comprises: the second SiGe heterojunction bipolar transistor, the 3rd SiGe heterojunction bipolar transistor, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th electric capacity;
The collector electrode of described the second SiGe heterojunction bipolar transistor connects supply voltage, described the 3rd resistance is connected between the collector electrode and base stage of described the second SiGe heterojunction bipolar transistor, described the 4th resistance is connected between the emitter of described the second SiGe heterojunction bipolar transistor and the base stage of described the 3rd SiGe heterojunction bipolar transistor, and described the 5th resistance is connected between the emitter of described the second SiGe heterojunction bipolar transistor and the base stage of described the first SiGe heterojunction bipolar transistor;
Described the 6th electric capacity is connected between the collector and emitter of described the 3rd SiGe heterojunction bipolar transistor, the base stage of the collector electrode of described the 3rd SiGe heterojunction bipolar transistor and described the second SiGe heterojunction bipolar transistor, the grounded emitter of described the 3rd SiGe heterojunction bipolar transistor.
4. radio-frequency power amplifier as claimed in claim 1, is characterized in that: described input matching network is L-type matching network.
5. radio-frequency power amplifier as claimed in claim 1, is characterized in that: described output matching network is T-shaped matching network.
6. radio-frequency power amplifier as claimed in claim 1, is characterized in that: described inter-stage matching network is T-shaped matching network.
7. the radio-frequency power amplifier as described in claim 1 or 4, is characterized in that: between described radio-frequency (RF) signal input end and described input matching network, be provided with capacitance.
8. the radio-frequency power amplifier as described in claim 1 or 5, is characterized in that: between described output matching network and described radiofrequency signal output, be provided with capacitance.
9. the radio-frequency power amplifier as described in claim 1 or 3, is characterized in that: described the first SiGe heterojunction bipolar transistor works in AB class state.
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