CN104103645A - 一种基板及其制作方法、显示装置 - Google Patents

一种基板及其制作方法、显示装置 Download PDF

Info

Publication number
CN104103645A
CN104103645A CN201410268289.5A CN201410268289A CN104103645A CN 104103645 A CN104103645 A CN 104103645A CN 201410268289 A CN201410268289 A CN 201410268289A CN 104103645 A CN104103645 A CN 104103645A
Authority
CN
China
Prior art keywords
layer
electrode
aluminium
substrate
aluminium electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410268289.5A
Other languages
English (en)
Other versions
CN104103645B (zh
Inventor
孔祥永
刘凤娟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201410268289.5A priority Critical patent/CN104103645B/zh
Priority to US14/654,329 priority patent/US9960185B2/en
Priority to PCT/CN2014/087894 priority patent/WO2015192538A1/zh
Publication of CN104103645A publication Critical patent/CN104103645A/zh
Application granted granted Critical
Publication of CN104103645B publication Critical patent/CN104103645B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种基板及其制作方法、显示装置，用以解决在衬底的铝电极上形成绝缘层时绝缘层存在断层的问题。所述基板包括：位于衬底上具有第一设定图形的铝电极，还包括与所述铝电极同层设置的具有第二设定图形的氧化铝层或氮化铝层；所述第一设定图形和所述第二设定图形互补。

Description

一种基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种基板及其制作方法、显示装置。
背景技术
在显示技术领域，大尺寸、高分辨率以及高画质的显示装置，如液晶显示器和有机发光显示器，在当前的平板显示器市场已经占据了主导地位。
显示面板中包括各种各样的电极，例如在显示面板中包括薄膜晶体管(Thin Film Transistor，TFT)的栅电极、源电极、漏电极、与栅电极相连的栅线，与源电极相连的数据线，与漏电极相连的像素电极等。
目前的显示面板，如液晶显示面板(Liquid Crystal Display，LCD)和有机发光显示面板(Organic Light Emitting Diode，OLED)，一般采用成本较低、导电性较好、金属离子扩散性较小的铝(Al)制作电极形成铝电极。并且通常在铝电极与其他电极之间制作绝缘层以保证相互绝缘。
一般地，通过降低铝电极的方块电阻提高铝电极的导电率，方块电阻与电极的厚度成反比，通过提高铝电极的厚度提高铝电极的导电率。为了提高电极所在器件的电学性能，例如提高TFT的开关电流，需要尽可能降低电极之间绝缘层的厚度。在较厚的铝电极上制作较薄的绝缘层，绝缘层容易在铝电极的边缘台阶处出现断层不良，绝缘层一旦存在断层，铝电极就会存在裸露在外的区域，铝电极会与绝缘层上的其他电极之间电相连，引起不良后果。
发明内容
本发明实施例提供一种基板及其制作方法、显示装置，用以解决在衬底的铝电极上形成绝缘层时绝缘层存在断层的问题。
为解决上述问题，本发明实施例提供的基板包括：位于衬底上具有第一设定图形的铝电极，还包括与所述铝电极同层设置的具有第二设定图形的氧化铝层或氮化铝层；所述第一设定图形和所述第二设定图形互补。
较佳地，所述铝电极与所述氧化铝层或氮化铝层的高度差为0～700nm。
较佳地，所述氧化铝层或氮化铝层的厚度为100～300nm，所述铝电极的厚度为300～800nm。
较佳地，所述基板还包括：位于所述铝电极和所述氧化铝层或氮化铝层上的绝缘层。
较佳地，所述铝电极包括由铝材料制作而成的栅电极、源电极、漏电极、栅线、数据线、阴极、阳极和电极引线至少之一。
本发明实施例提供一种基板的制作方法，包括：在衬底上形成具有第一设定图形的铝电极的过程，在所述衬底上形成与所述铝电极同层设置的具有第二设定图形的氧化铝层或氮化铝层的过程；所述第一设定图形和所述第二设定图形互补。
较佳地，形成所述铝电极和所述氧化铝层或氮化铝层的过程，具体为：
在衬底上形成第一设定厚度的铝层；
在所述铝层上待形成所述铝电极的区域形成保护层，露出所述保护层对应区域之外的铝层；
将形成有所述保护层的衬底置于通有氧气或氮气的退火设备进行退火，所述露出的铝层形成所述氧化铝层或氮化铝层，保护层正下方的铝层形成所述铝电极。
较佳地，该方法还包括：去除所述铝电极上的保护层。
较佳地，在形成保护层之后，退火之前，对所述露出的铝层进行刻蚀工艺，将第一设定厚度的铝层刻蚀为第二设定厚度的铝层。
较佳地，所述第一设定厚度的铝层和第二设定厚度的铝层的高度差为0～700nm。
较佳地，所述第一设定厚度为300～800nm，所述第二设定厚度为100～300nm。
较佳地，所述退火过程的条件包括：退火温度为150～450℃、退火时间为30～180min。
较佳地，在所述铝层上形成保护层，露出所述保护层对应区域之外的铝层，具体为：
通过成膜工艺在所述铝层上形成钼层，对所述钼层进行构图工艺，保留与所述待形成的铝电极对应区域的钼层作为所述保护层，去除其余区域的钼层，露出所述保护层对应区域之外的铝层。
较佳地，在形成所述铝电极和氧化铝层或氮化铝层之后还包括形成位于所述铝电极和所述氧化铝层或氮化铝层上的绝缘层。
较佳地，所述第一设定图形为栅电极图形、源电极图形、漏电极图形、栅线图形、数据线图形、阴极图形、阳极图形和电极引线图形中的至少之一。
本发明实施例提供一种显示装置，包括上述任一方式提供的基板。
综上所述，本发明提供的基板，包括位于衬底上具有第一设定图形的铝电极，还包括与所述铝电极同层设置的具有第二设定图形的氧化铝层或氮化铝层；所述第一设定图形和所述第二设定图形互补。当在铝电极上形成面积大于所述铝电极的绝缘层时，绝缘层同时形成在所述氧化铝层或氮化铝层上，降低了绝缘层与衬底之间的高度差(也称为梯度差)，绝缘层在所述铝电极的边缘对应的区域弯曲度较低，避免了在铝电极上形成绝缘层时，绝缘层因与衬底之间的高度差较高导致断层的问题。
附图说明
图1为本发明实施例提供的基板截面示意图；
图2为本发明实施例提供的基板俯视示意图；
图3为本发明实施例提供的设置有绝缘层的基板截面示意图；
图4为现有技术设置有绝缘层的基板截面示意图；
图5为图4所示的基板局部放大示意图；
图6为本发明实施例提供的基板制作方法流程示意图；
图7为本发明实施例提供的具有第一区域和第二区域的铝层结构示意图；
图8为本发明实施例提供的形成有铝层和钼层的基板截面示意图；
图9为本发明实施例提供的第一区域保留钼层，第二区域露出铝层的基板俯视示意图。
具体实施方式
本发明实施例提供一种基板及其制作方法、显示装置，用以解决在衬底的铝电极上形成绝缘层时绝缘层存在断层的问题。
所述绝缘层为面积大于所述铝电极且将所述铝电极完全遮盖的绝缘层。
衬底上的铝电极为具有一定厚度的图形结构，铝电极边缘与衬底之间形成台阶，绝缘层为能够起到绝缘作用的厚度较薄的膜层。绝缘层依照衬底和铝电极的表面形状形成于其上，形成局部具有弯曲状结构的膜层，在所述台阶处的弯曲程度较大。当衬底和铝电极之间的高度差较大时，绝缘层在衬底和铝电极之间的台阶处的弯曲度较大，容易形成断层。尤其是绝缘层的厚度较薄时，断层发生的几率更大。
针对上述技术问题，本发明提供下述技术方案，以解决铝电极上的绝缘层断层的问题。
以下将结合附图具体说明本发明实施例提供的基板及其制作方法、显示装置。本发明提供的下述有限个较佳的实施例，仅是用于解释说明本发明，并不用于限制本发明。
图2为本发明实施例提供的基板的俯视图，图1为图2所示的基板在A-A向的截面图，包括：
位于衬底1上具有第一设定图形的铝电极2；
与铝电极2同层设置的具有第二设定图形的氧化铝层或氮化铝层3；所述第一设定图形和所述第二设定图形互补。
第一设定图形的铝电极2可以包括由铝材料制作而成的栅电极、源电极、漏电极、与栅电极相连的栅线、与源电极相连的数据线、有机发光器件中的阳极、阴极和显示领域中常用的电极引线等至少之一。所述衬底可以为任何用于形成所述铝电极的衬底，该衬底为包括其他功能膜层的衬底，也可以为无任何功能膜层的衬底，如玻璃基板等。以铝电极为栅极为例说明，若TFT为底栅型TFT，则栅极可以直接制作在玻璃基板上或设置在具有缓冲层的玻璃基板上，当TFT为顶栅型TFT，则栅极制作在已经形成有源极、漏极、有源层等膜层的玻璃基板上。衬底相对于栅极而言，除栅极之外的结构均可以理解为衬底。
所述基板可以为显示用基板中的任一种，例如可以为形成有铝电极的彩膜基板、阵列基板或触摸屏等。
本发明上述实施例，铝电极2的图形与氧化铝层或氮化铝层3的图形互补，保证了铝电极2与氧化铝层或氮化铝层3之间无狭缝，铝电极2上的绝缘层不会因为所述狭缝发生断层的危险。与铝电极2同层设置的膜层为氧化铝层或氮化铝层3，氧化铝层或氮化铝层3为绝缘层，保证了铝电极2的第一设定图形结构。
本发明实施例提供的上述基板，与铝电极2同层设置的膜层为氧化铝层或氮化铝层3，这样的设置方式可以实现在制作铝电极2的同时将氧化铝层或氮化铝层3制作出来，避免了在铝电极2上单独制作绝缘层引起刻蚀(干法刻蚀)上的困难，工艺难度较大。
参见图3，在图1所示的基板的基础上，在铝电极2和氧化铝层或氮化铝层3上设置有绝缘层4；
绝缘层4设置在铝电极2上延伸至氧化铝层或氮化铝层3的区域，以保证完全覆盖铝电极2；绝缘层4依照铝电极2和氧化铝层或氮化铝层3的表面形状形成在其上，形成表面平整或凹凸不平的膜层，当铝电极2与氧化铝层或氮化铝层3高度不等时，绝缘层4在铝电极2的边缘具有弯折区域；当铝电极2与氧化铝层或氮化铝层3高度相等时，绝缘层4的表面平整。
作为上述实施例的对比例，参见图4，现有技术在衬底1上形成铝电极2，在铝电极2上形成绝缘层4，绝缘层4覆盖铝电极2以及衬底1。
图3所示的基板，铝电极2与氧化铝层或氮化铝层3的高度差为h1，绝缘层4在铝电极2边缘的台阶高度为h1；图4所示的基板，铝电极2与衬底1的高度差为h2，绝缘层4在铝电极2边缘的台阶高度为h2；很显然，h1<h2，h2与h1的差值为图3所示的氧化铝层或氮化铝层3的厚度值。图3所示的绝缘层4形成在铝电极2与氧化铝层或氮化铝层3上，在与铝电极2的边缘对应的区域弯曲度较小，在铝电极2的边缘对应的区域断层的几率较小，或者不会产生断层的风险。图4所示的绝缘层4形成在铝电极2与衬底1上，在与铝电极2的边缘对应的区域台阶弯曲度较大，在铝电极2的边缘对应的区域断层的几率较大，尤其是当绝缘层4较薄时，绝缘层4很容易发生断层不良。图5为图4所示的包括断层区域的局部放大结构示意图。由图5可知，绝缘层4发生断层时，绝缘层4覆盖的铝电极2的B区域露出，当在绝缘层4上制作其他导电膜层时，会通过露出部分的铝电极2电相连，产生不良后果。
也就是说，相比较在衬底和铝电极上形成绝缘层的实施例，本发明提高了绝缘层的平坦化程度，降低了绝缘层局部弯曲时的台阶，降低了断层发生的几率，甚至避免了断层的发生。
优选地，所述铝电极与所述氧化铝层或氮化铝层的高度差在0～700nm范围内，可以保证任何厚度的绝缘层均不发生断层不良，也就是说，避免了较薄的绝缘层形成于铝电极上导致断层的问题。
一般地，较薄绝缘层的厚度在100～500nm范围内。绝缘层较薄时，一方面可以提高所在器件的电学性能，另一方面还可以降低基板的厚度。例如当在TFT的栅极上制作栅极绝缘层时，可以避免栅极绝缘层较薄时存在断层不良，同时栅极绝缘层较薄时可以提高TFT的开关电流，提高TFT的电学特性。
本发明图1所示的基板，衬底1上的铝电极2可以高于、等于或低于衬底1上的氧化铝层或氮化铝层3。
其中一种较佳的实施方式为：衬底1上的铝电极2高于衬底1上的氧化铝层或氮化铝层3。
基于上述实施例，所述氧化铝层或氮化铝层的厚度为100～300nm，所述铝电极的厚度为300～800nm时，一方面可以避免绝缘层断层的问题，另一方面形成的电极电阻率较低，可以满足实际应用需求。
根据对铝电极的方块电阻的不同要求以及基板上空间位置的不同，铝电极2的厚度根据实际需求而定，一般地，方块电阻越小越好，方块电阻与电极厚度成反比，为了降低电极的方块电阻，提高电极的电导率，往往通过提高铝电极的厚度减小电极的方块电阻。
另一种较佳的实施方式为，氧化铝层或氮化铝层3的厚度等于或约等于铝电极2的厚度时，氧化铝层或氮化铝层3和铝电极2形成的表面几乎平坦，绝缘层4的厚度可以做到尽可能薄而无需考虑断层的风险。
本发明实施例还提供一种显示装置，包括上述实施例提供的任一方式的基板。所述显示装置为液晶显示面板、液晶显示器、液晶电视、有机发光显示面板、有机柔性显示器件、手机等任何具有显示功能的产品或部件。
以下将具体说明上述任一实施例提供的基板的制作方法。
所述制作方法主要包括以下步骤：
在衬底上形成具有第一设定图形的铝电极的过程，以及在所述衬底上形成与所述铝电极同层设置的具有第二设定图形的氧化铝层或氮化铝层的过程；所述第一设定图形和所述第二设定图形互补。
参见图6，上述基板的制作方法，具体包括以下步骤：
S11、在衬底上形成第一设定厚度的铝层；
S12、在所述铝层上待形成所述铝电极的区域形成与所述第一设定图形对应的保护层，露出所述保护层对应区域之外的铝层；
S13、将形成有所述保护层的衬底置于通有氧气或氮气的退火设备进行退火，所述露出的铝层形成具有所述第二设定图形的氧化铝层或氮化铝层，保护层正下方的铝层形成所述铝电极。
当所述保护层较薄时，且氧化铝层或氮化铝层和铝电极的厚度相等，则在铝电极上制作绝缘层时，绝缘层表面的弯折区域对应保护层的边缘区域，保护层的厚度小于铝电极的厚度时，可以避免绝缘层断层的问题。
优选地，所述方法还包括：去除所述铝电极上的保护层。当去除所述铝电极上的保护层后，绝缘层设置于所述铝电极和氧化铝层或氮化铝层上，当所述氧化铝层或氮化铝层和铝电极的厚度相等时，二者的顶部在同一水平面，则绝缘层为平坦的膜层，不会引起断层的问题。
优选地，为了保证露出的铝层完全被氧化或氮化，保证与铝电极完全绝缘，则在形成保护层之后，退火之前，对所述露出的铝层进行刻蚀工艺，将第一设定厚度的铝层刻蚀为第二设定厚度的铝层。第二设定厚度的铝层厚度低于第一设定厚度的铝层，在相同的退火条件下，氧化或氮化更加彻底，在保证铝层被完全氧化或氮化的前提下还可以缩短退火时间，提高生成效率。
优选地，所述第一设定厚度的铝层和第二设定厚度的铝层的高度差为0～700nm，则可以保证绝缘层不会或者几乎不会发生断层不良。
保证第一设定厚度的铝层和第二设定厚度的铝层的高度差为0～700nm的其中一种实施方式为：所述第一设定厚度为300～800nm，所述第二设定厚度为100～300nm。
较佳地，所述退火过程的条件包括：退火温度为150～450℃、退火时间为30～180min。
上述步骤S12，在所述铝层上形成保护层，露出所述保护层对应区域之外的铝层，具体为：
通过成膜工艺在所述铝层上形成一层钼层，对所述钼层进行构图工艺，保留与所述待形成的铝电极对应区域的钼层作为所述保护层，去除其余区域的钼层，露出所述保护层对应区域之外的铝层。
进一步地，在形成所述铝电极和所述氧化铝层或氮化铝层之后还包括形成位于所述铝电极和所述氧化铝层或氮化铝层上的绝缘层。
较佳地，所述第一设定图形为栅电极图形、源电极图形、漏电极图形、栅线图形、数据线图形、阴极图形、阳极图形和电极引线图形中的至少之一。
以下以电极图形为栅极图形、绝缘层为栅极绝缘层为例说明上述基板的制作方法。
步骤一：参见图7，采用沉积法或离子溅射法在衬底上形成一层第一设定厚度的铝层，该铝层的厚度约300～800nm；设铝层包括待形成栅极的第一区域(C区域)，以及第一区域之外的第二区域(D区域)。
步骤二：参见图8，在衬底1的铝层6上面形成一层钼层7，形成钼层7的方法与形成铝层的方法类似，这里不再赘述。
步骤三：先后对图8所示的铝层6和钼层7进行构图工艺，即掩膜、曝光、显影、刻蚀等过程；参见图9，保留第一区域对应的钼层7，去除第二区域的钼层7。
为了既能够达到避免栅极绝缘层断层的目的，又能够使得待氧化或氮化的铝层不至于过厚导致氧化或氮化不彻底引起与栅极导电的问题，第二区域的铝层不宜过厚，否则难以彻底氧化或氮化为绝缘层。
因此，步骤三中去除第二区域的钼层之后还包括对第二区域的铝层进行刻蚀的过程，将第一设定厚度的铝层刻蚀为第二设定厚度的铝层，第二设定厚度小于第一设定厚度，刻蚀可以采用干法刻蚀也可采用湿法刻蚀，保证局部区域刻蚀厚度一致。较佳地，第二设定厚度为100～300nm。
步骤四：将构图工艺后的衬底置于通有氧气或氮气的退火设备，在退火温度为150～450℃、退火时间为30～180min的条件下进行退火，第二区域的铝层由于露在氧气或氮气环境中，并且厚度在100～300nm范围内，可以在上述退火条件下彻底形成氧化铝层或氮化铝层，氧化铝层或氮化铝层为绝缘层，第一区域的铝层在钼层的保护下未被氧化或氮化，形成可导电的栅极图形。
步骤五：去除第一区域的钼层，露出的电极图形为栅极图形。
步骤六：还包括在栅极上形成一层栅极绝缘层，栅极绝缘层可以覆盖整个衬底。
栅极绝缘层与栅极之间的高度差较小，可以避免栅极绝缘层断层不良。并且，上述制作栅极的过程中，仅需要将形成铝层的基板置于退火设备就可以形成氮化铝或氧化铝层，无需增加额外的工艺在栅极周围形成的氮化铝或氧化铝层，栅极的制作过程简单。
上述栅极制作过程仅是举例说明，制作其他电极的过程与栅极类似，这里不再赘述。
综上所述，本发明提供的基板，当铝电极上设置有覆盖铝电极的绝缘层时，绝缘层覆盖铝电极的同时覆盖与铝电极同层设置的氧化铝层或氮化铝层；提高了绝缘层整体和局部的平坦化程度，避免了绝缘层因局部区域弯曲程度较大产生断层的问题。形成所述基板的过程中，铝电极和氧化铝层或氮化铝层在同一次退火工艺中形成，工艺流程简单。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (16)

1.一种基板，包括：位于衬底上具有第一设定图形的铝电极，其特征在于，还包括与所述铝电极同层设置的具有第二设定图形的氧化铝层或氮化铝层；所述第一设定图形和所述第二设定图形互补。
2.根据权利要求1所述的基板，其特征在于，所述铝电极与所述氧化铝层或氮化铝层的高度差为0～700nm。
3.根据权利要求2所述的基板，其特征在于，所述氧化铝层或氮化铝层的厚度为100～300nm，所述铝电极的厚度为300～800nm。
4.根据权利要求1所述的基板，其特征在于，所述基板还包括：位于所述铝电极和所述氧化铝层或氮化铝层上的绝缘层。
5.根据权利要求1所述的基板，其特征在于，所述铝电极包括由铝材料制作而成的栅电极、源电极、漏电极、栅线、数据线、阴极、阳极和电极引线至少之一。
6.一种基板的制作方法，其特征在于，包括：在衬底上形成具有第一设定图形的铝电极的过程，以及在所述衬底上形成与所述铝电极同层设置的具有第二设定图形的氧化铝层或氮化铝层的过程；所述第一设定图形和所述第二设定图形互补。
7.根据权利要求6所述的制作方法，其特征在于，形成所述铝电极和所述氧化铝层或氮化铝层的过程，具体为：
在衬底上形成第一设定厚度的铝层；
在所述铝层上待形成所述铝电极的区域形成保护层，露出所述保护层对应区域之外的铝层；
将形成有所述保护层的衬底置于通有氧气或氮气的退火设备进行退火，所述露出的铝层形成所述氧化铝层或氮化铝层，保护层正下方的铝层形成所述铝电极。
8.根据权利要求7所述的制作方法，其特征在于，所述方法还包括：去除所述铝电极上的保护层。
9.根据权利要求8所述的制作方法，其特征在于，在形成保护层之后，退火之前，对所述露出的铝层进行刻蚀工艺，将第一设定厚度的铝层刻蚀为第二设定厚度的铝层。
10.根据权利要求9所述的制作方法，其特征在于，所述第一设定厚度的铝层和第二设定厚度的铝层的高度差为0～700nm。
11.根据权利要求10所述的制作方法，其特征在于，所述第一设定厚度为300～800nm，所述第二设定厚度为100～300nm。
12.根据权利要求7所述的制作方法，其特征在于，所述退火过程的条件包括：退火温度为150～450℃、退火时间为30～180min。
13.根据权利要求7所述的制作方法，其特征在于，在所述铝层上形成保护层，露出所述保护层对应区域之外的铝层，具体为：
通过成膜工艺在所述铝层上形成钼层，对所述钼层进行构图工艺，保留与所述待形成的铝电极对应区域的钼层作为所述保护层，去除其余区域的钼层，露出所述保护层对应区域之外的铝层。
14.根据权利要求7所述的制作方法，其特征在于，在形成所述铝电极和所述氧化铝层或氮化铝层之后还包括：形成位于所述铝电极和所述氧化铝层或氮化铝层上的绝缘层。
15.根据权利要求6所述的制作方法，其特征在于，所述第一设定图形为栅电极图形、源电极图形、漏电极图形、栅线图形、数据线图形、阴极图形、阳极图形和电极引线图形中的至少之一。
16.一种显示装置，其特征在于，包括权利要求1～5任一所述的基板。
CN201410268289.5A 2014-06-16 2014-06-16 一种基板及其制作方法、显示装置 Active CN104103645B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410268289.5A CN104103645B (zh) 2014-06-16 2014-06-16 一种基板及其制作方法、显示装置
US14/654,329 US9960185B2 (en) 2014-06-16 2014-09-30 Base and manufacturing method thereof, display device
PCT/CN2014/087894 WO2015192538A1 (zh) 2014-06-16 2014-09-30 基板及其制作方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410268289.5A CN104103645B (zh) 2014-06-16 2014-06-16 一种基板及其制作方法、显示装置

Publications (2)

Publication Number Publication Date
CN104103645A true CN104103645A (zh) 2014-10-15
CN104103645B CN104103645B (zh) 2017-03-29

Family

ID=51671648

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410268289.5A Active CN104103645B (zh) 2014-06-16 2014-06-16 一种基板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US9960185B2 (zh)
CN (1) CN104103645B (zh)
WO (1) WO2015192538A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783774A (zh) * 2016-12-20 2017-05-31 上海芯石微电子有限公司 一种氧化铝钝化结构及其制备方法
CN107833874A (zh) * 2017-11-15 2018-03-23 上海芯石微电子有限公司 一种多功能铝和氧化铝结构及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1961408A (zh) * 2004-03-31 2007-05-09 先进微装置公司 形成侧壁间隔物的方法
CN102033370A (zh) * 2009-09-25 2011-04-27 北京京东方光电科技有限公司 液晶显示基板及其制造方法
US20130089975A1 (en) * 2011-10-06 2013-04-11 Canon Kabushiki Kaisha Method for manufacturing semiconductor device
CN103048840A (zh) * 2012-11-12 2013-04-17 京东方科技集团股份有限公司 阵列基板及其制作方法、液晶显示面板和显示装置
CN103489922A (zh) * 2013-09-30 2014-01-01 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN103839794A (zh) * 2014-02-25 2014-06-04 京东方科技集团股份有限公司 透明导电电极及阵列基板的制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7985986B2 (en) * 2008-07-31 2011-07-26 Cree, Inc. Normally-off semiconductor devices
JP5280309B2 (ja) * 2009-07-17 2013-09-04 新光電気工業株式会社 半導体装置及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1961408A (zh) * 2004-03-31 2007-05-09 先进微装置公司 形成侧壁间隔物的方法
CN102033370A (zh) * 2009-09-25 2011-04-27 北京京东方光电科技有限公司 液晶显示基板及其制造方法
US20130089975A1 (en) * 2011-10-06 2013-04-11 Canon Kabushiki Kaisha Method for manufacturing semiconductor device
CN103048840A (zh) * 2012-11-12 2013-04-17 京东方科技集团股份有限公司 阵列基板及其制作方法、液晶显示面板和显示装置
CN103489922A (zh) * 2013-09-30 2014-01-01 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN103839794A (zh) * 2014-02-25 2014-06-04 京东方科技集团股份有限公司 透明导电电极及阵列基板的制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783774A (zh) * 2016-12-20 2017-05-31 上海芯石微电子有限公司 一种氧化铝钝化结构及其制备方法
CN107833874A (zh) * 2017-11-15 2018-03-23 上海芯石微电子有限公司 一种多功能铝和氧化铝结构及其制备方法

Also Published As

Publication number Publication date
WO2015192538A1 (zh) 2015-12-23
CN104103645B (zh) 2017-03-29
US20160268314A1 (en) 2016-09-15
US9960185B2 (en) 2018-05-01

Similar Documents

Publication Publication Date Title
CN108288621B (zh) 阵列基板的制造方法、阵列基板及显示面板
JP5149464B2 (ja) コンタクト構造、基板、表示装置、並びに前記コンタクト構造及び前記基板の製造方法
CN104393000B (zh) 一种阵列基板及其制作方法、显示装置
CN103872142A (zh) 像素结构及其制作方法
CN102487042B (zh) 阵列基板及其制造方法和检测方法、液晶面板
US20170263645A1 (en) Substrate, manufacturing method thereof, and display device
CN205428907U (zh) 层堆叠结构、阵列基板和显示装置
CN104091810A (zh) 阵列基板及其制作方法、显示装置
WO2015192595A1 (zh) 阵列基板及其制备方法、显示装置
CN103928400A (zh) 阵列基板及其制作方法、显示装置
CN102842587A (zh) 阵列基板及其制作方法、显示装置
CN104133313A (zh) 阵列基板及其制备方法、液晶显示装置
CN102629588B (zh) 阵列基板的制造方法
CN103094287A (zh) 阵列基板及其制备方法、显示装置
CN106783889A (zh) 显示基板及其制备方法、显示装置
CN104407463A (zh) 像素结构的制造方法及液晶显示面板的制造方法
EP3320555B1 (en) Thin-film-transistor, thin-film-transistor array substrate, fabricating methods thereof, and display panel
CN102629589B (zh) 一种阵列基板及其制作方法和显示装置
CN104465670A (zh) 一种阵列基板及其制作方法、显示装置
CN104103645A (zh) 一种基板及其制作方法、显示装置
CN104916649A (zh) 阵列基板及其制造方法
CN103985708A (zh) 薄膜晶体管阵列基板及其制作方法
US9331105B2 (en) Array substrate, manufacturing method thereof and display device
US20140367706A1 (en) Thin film transistor array panel and method of manufacturing the same
CN104538405A (zh) 一种阵列基板及其制造方法和显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant