CN104051400A - 接合线的支架 - Google Patents

接合线的支架 Download PDF

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Publication number
CN104051400A
CN104051400A CN201410090520.6A CN201410090520A CN104051400A CN 104051400 A CN104051400 A CN 104051400A CN 201410090520 A CN201410090520 A CN 201410090520A CN 104051400 A CN104051400 A CN 104051400A
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CN
China
Prior art keywords
lead
wire
closing line
tube core
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410090520.6A
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English (en)
Inventor
罗丽贞
黄保杰
叶荣丰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
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Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN104051400A publication Critical patent/CN104051400A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了用于接合线的支架。在具有在第一方向上延伸的多层接合线的半导体器件中，虚设绝缘接合线在与第一方向垂直的第二方向上和在线层之间延伸以支撑上层线以防止它们下垂和接触下层线。

Description

接合线的支架
技术领域
本发明涉及具有多层接合线的半导体器件，并且更具体地说，涉及带有用于防止单独层中的线彼此接触的支架的半导体器件
背景技术
很多半导体器件使用接合线来将集成电路管芯的焊盘连接到引线框的引线或衬底的盘。随着集成电路变得越来越小并包含更多功能，就需要多层接合线来连接管芯焊盘和引线/衬底盘。参照图1，示出了封装的半导体器件10。器件10包括利用诸如粘合剂16的管芯附着材料，附着到引线框的标志14的集成电路（IC）管芯12。IC管芯12利用接合线被电连接到引线框的引线，其中引线提供到外部电路和器件的连接。在这种情况下，器件10包括一组内引线18和一组外引线20。第一组接合线22将管芯12的焊盘连接到内引线18，并且第二组接合线24将管芯12的焊盘连接到外引线20。第二组线24可以长于第一组线22，因为它们从板中焊盘延伸到外引线20，而第一线组22从管芯12边缘附近的焊盘延伸到内引线18。因此，第二组接合线24可以有相当大的长度。
由于线下垂，带有多层接合线的这种器件常常会遇到线短路问题。例如，由于第二组线24长，所以它们可能具有下垂的倾向，如线26所示。优化环轮廓不保证100％消除线下垂。如果只有两组线22、24所延伸到的所述行引线的一行（即，只有外引线20），短路的发生可能是比较麻烦。
鉴于上述情况，期望有一种防止来自多层或具有不同环高度的线发生短路的方法。
附图说明
当结合附图阅读时，将更好地理解本发明的优选实施例的下列详细描述。本发明通过示例的方式被说明并且不受限于附图，在附图中，类似的标记指示相似的元素。应当理解，为了容易理解本发明，附图没有按比例并且已经被简化。
图1是常规集成电路（IC）器件的放大的截面图；
图2A是根据本发明的第一实施例的部分装配的集成电路（IC）器件的放大的顶部平面图；
图2B是图2A的IC器件的放大的部分侧视图；
图3A是根据本发明的第二实施例的部分装配的IC器件的放大的顶部平面图；
图3B是图3A的IC器件的放大的部分侧视图；
图4是根据本发明的第三实施例的部分装配的IC器件的放大的顶视图。
具体实施方式
在下面结合附图陈述的详细描述旨在作为本发明目前优选实施例的描述，并不旨在表示可以实施本发明的唯一形式。应了解，相同或等同功能可以通过旨在被包含在本发明精神和范围内的不同实施例来实现。
在一个实施例中，本发明提供了一种半导体器件，该半导体器件包括管芯标志和附着到所述管芯标志的顶面的集成电路（IC）管芯。多个第一引线与所述管芯标志的第一侧边缘间隔开。第一虚设引线与所述管芯标志的第二侧边缘间隔开，并且第二虚设引线与所述管芯标志的与所述第二侧边缘相对的第三侧边缘间隔开。多个第一接合线从所述IC管芯的顶面上的第一组焊盘延伸到所述多个第一引线的第一组以用于将所述第一组焊盘电连接到第一引线的所述第一组。多个第二接合线从所述IC管芯的所述顶面上的第二组焊盘延伸到所述多个第一引线的第二组以用于将所述第二组焊盘电连接到第一引线的所述第二组。至少一个绝缘接合线从所述第一虚设引线延伸到所述第二虚设引线并且在第一多个接合线和第二多个接合线之间。所述至少一个绝缘接合线防止所述多个第二接合线下垂和接触所述多个第一接合线的接合线。
在另一个实施例中，本发明提供了一种半导体器件，该半导体器件具有管芯标志和附着到所述管芯标志的顶面的IC管芯。多个第一引线与所述管芯标志的第一侧边缘间隔开，并且虚设引线与所述管芯标志的第二侧边缘间隔开，所述第二侧边缘与所述管芯标志的所述第一侧边缘相邻。多个第一接合线从所述管芯的顶面上的第一组焊盘延伸到所述多个第一引线的第一组以用于将所述第一组焊盘电连接到第一引线的所述第一组。多个第二接合线从所述集成电路管芯的所述顶面上的第二组焊盘延伸到所述多个第一引线的第二组以用于将所述第二组焊盘电连接到第一引线的所述第二组。至少一个绝缘接合线从第三焊盘延伸到所述虚设引线并且在第一多个接合线和第二多个接合线之间，所述第三焊盘在所述IC管芯的顶面上并且在所述IC管芯的边缘附近。所述至少一个绝缘接合线防止所述多个第二接合线下垂和接触所述多个第一接合线的接合线。
在参照图2A和2B，图2A是根据本发明的第一优选实施例的半导体器件30的放大的部分顶部平面图，并且图2B是根据本发明的第一优选实施例的器件30的截面中的放大的部分侧视图。半导体器件30具有被管芯标志34支撑的集成电路（IC）管芯32。管芯标记34可以是引线框标志或衬底的管芯支撑区域，这两者都是本领域技术人员所已知的。IC管芯32利用管芯附着材料或粘合剂36被附着到管芯标记34的顶面，这也是本领域已知的。管芯附着材料36被放置在IC管芯32和管芯标记34的顶面之间，并将IC管芯32固定到管芯标记34的顶面。IC管芯32可以包括处理器、微控制器、片上系统（SOC）、或通常形成于硅衬底上的其它已知电路。
多个第一引线38与管芯标志34的第一侧边缘40间隔开。如果半导体器件30是引线框类型器件，那么第一引线38包括引线框的引线指，并且如果器件30是衬底类型器件，那么第一引线38包括衬底互连盘。用于组装半导体器件的引线框和衬底在本领域是已知的，并且完整的描述对本发明的完全理解是没有必要的。
为了便于说明，所述多个第一引线38被示为单一块。然而，如本领域所属技术人员了解的，第一引线38包括单独引线或衬底连接盘。第一引线38可以包括单行或多行引线。通常，引线被间隔开并且围绕管芯标记34，然而，为了便于说明，在附图中，引线38被示为只在管芯标记34的一侧。
在本发明的实施例中，如图2B中所示，IC管芯32的顶面位于第一平面中，并且所述多个第一引线38位于第二平面中，所述第二平面平行于所述第一平面并与所述第一平面间隔开，并且更具体地说，所述第一平面高于所述第二平面。而且，管芯标志34和第一引线38都位于所述第二平面中。
半导体器件30还具有第一虚设引线42和第二虚设引线44，第一虚设引线42与所述管芯标记34的第二侧边缘间隔开，第二虚设引线44与所述管芯标志34的与所述第二侧边缘相对的第三侧边缘间隔开。第一和第二虚设引线42、44可以包括一个或多个单独引线或如图2A中所示的细长条。在本发明的一个实施例中，第一和第二虚设引线42、44不用于电连接以在不同点之间传递信号，而是如下所述用于固定虚设接合线。
多个第一接合线46从IC管芯32的顶面上的第一组管芯焊盘48延伸到所述多个第一引线38的第一组以用于将所述第一组管芯焊盘48电连接到第一引线38的所述第一组。还有多个第二接合线50，多个第二接合线50从集成电路管芯32的顶面上的第二组管芯焊盘52延伸到所述多个第一引线38的第一组以用于将所述第二组管芯焊盘52电连接到第一引线38的所述第二组。
在所示的实施例中，第一组管芯焊盘48位于管芯32附近并沿着管芯32的外边缘，并且第二组管芯焊盘52与管芯32的外边缘间隔开，使得第一和第二组管芯焊盘48、52包括两行管芯焊盘。焊盘48、52可以相对于彼此交错或非交错。
如本领域已知的，第一和第二多个接合线46、50优选地包括裸或镀铜、金或铝线中的一个。为了便于将第一和第二组管芯焊盘48、52互联到第一引线38，第一和第二多个接合线46、50具有不同的环高度。也就是说，第二接合线50较长并有比第一接合线46更大的环高度。
半导体器件30还具有至少一个绝缘接合线54，所述至少一个绝缘接合线54从所述第一虚设引线42延伸到所述第二虚设引线44并且在第一和第二多个接合线之间以便防止所述多个第二接合线50下垂和接触所述多个第一接合线46的接合线。在本发明的一个实施例中，存在间隔开且彼此平行的至少两个绝缘接合线54，而在另一个实施例中，存在至少三个绝缘接合线54，每一个绝缘接合线彼此间隔开并通常与其它两个平行地延伸。
涂层或绝缘接合线在本领域是已知的并且在市场上是可买到的。在本发明的优选实施例中，绝缘接合线的直径等于或大于第一和第二接合线46、50的直径。如前面所讨论的，在一个实施例中，第一和第二虚设引线42和44不用于将信号发射到管芯外，因此引线42、44只需要调整大小和形状以允许使用引线接合工艺附着绝缘线54。
如图1中所示的常规器件10，半导体器件30包括塑封材料，该塑封材料至少封装了IC管芯32的顶面、第一和第二虚设引线42、44、至少一个绝缘接合线54、第一和第二多个接合线46、50以及所述多个第一引线38的一部分，其中未覆盖表面或第一引线的一部分允许通过外部电路或器件电连接到IC管芯32。
现在参照图3A和3B，图3A是根据本发明的第二优选实施例的半导体器件58的放大的部分顶部平面图，并且图3B是根据本发明的第二优选实施例的器件58的截面中的放大的部分侧视图。半导体器件58包括集成电路（IC）管芯32、第一引线38、第一和第二虚设引线42、44、以及在IC管芯32的顶面或有源表面上的第一和第二组管芯焊盘48、52。第一和第二组接合线60和62将第一和第二组管芯焊盘48、52与第一引线38电连接。由于第二组接合线52从焊盘52的内部行延伸，所以第二组接合线52具有比第一组接合线60更大的环高度。在该实施例中，只是单一绝缘线64从第一虚设引线42延伸到第二虚设引线44并且在第一和第二组接合线60、62之间以给第二组接合线62提供支撑，使得第二组接合线62将不下垂和接触第一组接合线60。虽然绝缘线64被示为穿过IC管芯32附近的第一和第二组接合线60、62，但是绝缘线64可被定位成使得它在IC管芯32和第一引线38之间，诸如大约是IC管芯32和第一引线38中间的位置穿过第一和第二组接合线60、62。
现在参照图4，图4示出了根据本发明的第三实施例的部分装配的半导体器件70的放大的顶部平面图。半导体器件70包括安装在管芯标记（未示出）上的IC管芯72和与管芯72的第一侧边缘76间隔开的多个第一引线74。管芯72的第二侧边缘和第三侧边缘分别在78和80被指示。
存在与管芯72的第三侧边缘80间隔开的虚设引线82。管芯72具有多个管芯焊盘，在这个例子中被示为放置在两行中，其中管芯焊盘84在外部行（最接近侧边缘76），而管芯焊盘86在与管芯焊盘84相对的内部行。当然，与其它实施例一样，IC管芯可以具有在其所有四个侧面周围的多行管芯焊盘以及在它的所有四个侧面周围的对应行的引线。
多个第一接合线88从管芯焊盘84的外部行延伸到第一引线74的第一组92以用于将管芯焊盘84的外部行电连接到第一引线74的第一组92，并且多个第二接合线90从管芯焊盘86的内部行延伸到多个第一引线74的第二组94以用于将管芯焊盘86的内部行电连接到第一引线74的第二组94。在该实施例中，第二接合线90比第一接合线88长并具有比第一接合线88更大的环高度。
存在从第一附加管芯焊盘94延伸并且在第一和第二多个接合线88、90之间的第一绝缘接合线92，第一附加管芯焊盘94位于IC管芯72的顶面上并且在IC管芯的第一和第二侧边缘76和78接触虚设引线82的拐角处附近。第一绝缘接合线92防止所述多个第二接合线90下垂和接触所述多个第一接合线88的接合线。在该实施例中，第一附加管芯焊盘94可以是虚设盘。替代地，第一附加盘94可以是用于将信号发射到虚设引线82或用于接收从虚设引线82发射的电压（电源或接地）或信号的有源盘，其中虚设引线82实际上不是虚设引线，而是实际电源、接地或信号引线。
半导体器件70还可以包括从第二附加管芯焊盘98延伸到虚设引线82并且在第一和第二多个接合线88、90之间的第二绝缘接合线96，第二附加管芯焊盘98位于IC管芯72的顶面上并且在第二侧边缘78附近。第二绝缘接合线96也有助于防止所述多个第二接合线90下垂和接触所述多个第一接合线88的接合线。如同第一附加管芯焊盘94，第二附加管芯焊盘98可以是虚设盘或有源盘。
因此，如从前面的讨论中显而易见的，本发明提供了一种通过给上层线提供支架或支撑以防止上层线下垂而用于防止具有多层接合线的不同层器件中的线之间的线短路的手段。支架或支撑可以采取从一个虚设引线延伸到另一个虚设引线、从管芯焊盘延伸到虚设引线、或甚至从管芯焊盘延伸到功能引线的绝缘线的形式。在多芯片模块的情况下，支架/支撑线可以从第一IC管芯的表面上的焊盘延伸到第二IC管芯的表面上的焊盘。接合线可以是铝、金或铜，而完成的器件可以是BGA类型器件。
因此，虽然说明并描述了本发明的优选实施例，但是将清楚的是，本发明不仅限定于这些实施例。在不脱离如在权利要求中描述的本发明的精神及范围的情况下，各种修改、改变、变体、替换和等同物对本领域技术人员来说将是显而易见的。

Claims (20)

1.一种半导体器件，包括：
管芯标志；
集成电路管芯，所述集成电路管芯附着到所述管芯标志的顶面；
多个第一引线，所述多个第一引线与所述管芯标志的第一侧边缘间隔开；
第一虚设引线，所述第一虚设引线与所述管芯标志的第二侧边缘间隔开；
第二虚设引线，所述第二虚设引线与所述管芯标志的与所述第二侧边缘相对的第三侧边缘间隔开；
多个第一接合线，所述多个第一接合线从所述集成电路管芯的顶面上的第一组焊盘延伸到所述多个第一引线的第一组以用于将所述第一组焊盘电连接到第一引线的所述第一组；
多个第二接合线，所述多个第二接合线从所述集成电路管芯的所述顶面上的第二组焊盘延伸到所述多个第一引线的第二组以用于将所述第二组焊盘电连接到第一引线的所述第二组；以及
至少一个绝缘接合线，所述至少一个绝缘接合线从所述第一虚设引线延伸到所述第二虚设引线并且在所述第一多个接合线和第二多个接合线之间，其中所述至少一个绝缘接合线防止所述多个第二接合线下垂和接触所述多个第一接合线中的接合线。
2.根据权利要求1所述的半导体器件，其中所述至少一个绝缘接合线包括两个绝缘接合线，所述两个绝缘接合线间隔开并且彼此平行。
3.根据权利要求1所述的半导体器件，其中所述至少一个绝缘接合线包括三个绝缘接合线，所述三个绝缘接合线的每一个间隔开并且彼此平行。
4.根据权利要求1所述的半导体器件，其中所述第一多个接合线和第二多个接合线包括裸铜线、裸铝线、和裸金线中的一个。
5.根据权利要求1所述的半导体器件，其中所述第一多个接合线和第二多个接合线具有不同的环高度。
6.根据权利要求1所述的半导体器件，其中所述集成电路管芯的所述顶面位于第一平面中，并且所述多个第一引线位于第二平面中，所述第二平面平行于所述第一平面并且与所述第一平面间隔开。
7.根据权利要求3所述的半导体器件，其中所述第一平面高于所述第二平面。
8.根据权利要求1所述的半导体器件，进一步包括管芯附着材料，所述管芯附着材料在所述集成电路管芯和所述管芯标志的所述顶面之间以用于将所述集成电路管芯固定到所述管芯标志的所述顶面。
9.根据权利要求8所述的半导体器件，进一步包括塑封材料，所述塑封材料至少封装了所述集成电路管芯的所述顶面、所述第一虚设引线和第二虚设引线、所述至少一个绝缘接合线、所述第一多个接合线和第二多个接合线、以及所述多个第一引线的一部分。
10.一种半导体器件，包括：
管芯标志；
集成电路管芯，所述集成电路管芯附着到所述管芯标志的顶面；
多个第一引线，所述多个第一引线与所述管芯标志的第一侧边缘间隔开；
第一虚设引线，所述第一虚设引线与所述管芯标志的第二侧边缘间隔开；
第二虚设引线，所述第二虚设引线与所述管芯标志的与所述第二侧边缘相对的第三侧边缘间隔开；
多个第一接合线，所述多个第一接合线从所述集成电路管芯的顶面上的第一组焊盘延伸到所述多个第一引线的第一组以用于将所述第一组焊盘电连接到第一引线的所述第一组；
多个第二接合线，所述多个第二接合线从所述集成电路管芯的所述顶面上的第二组焊盘延伸到所述多个第一引线的第二组以用于将所述第二组焊盘电连接到第一引线的所述第二组，
其中所述多个第一接合线具有与所述多个第二接合线不同的环高度；以及
至少一个绝缘接合线，所述至少一个绝缘接合线从所述第一虚设引线延伸到所述第二虚设引线并且在第一多个接合线和第二多个接合线之间，其中所述至少一个绝缘接合线防止所述多个第二接合线下垂和接触所述多个第一接合线中的接合线。
11.根据权利要求10所述的半导体器件，其中所述至少一个绝缘接合线包括两个绝缘接合线，所述两个绝缘接合线间隔开并且彼此平行。
12.根据权利要求10所述的半导体器件，其中所述至少一个绝缘接合线包括三个绝缘接合线，所述三个绝缘接合线的每一个间隔开并且彼此平行。
13.根据权利要求10所述的半导体器件，其中所述第一多个接合线和第二多个接合线包括裸铜线、裸铝线、和裸金线中的一个。
14.根据权利要求10所述的半导体器件，进一步包括管芯附着材料，所述管芯附着材料在所述集成电路管芯和所述管芯标志的所述顶面之间以用于将所述集成电路管芯固定到所述管芯标志的所述顶面。
15.根据权利要求14所述的半导体器件，进一步包括塑封材料，所述塑封材料至少封装了所述集成电路管芯的所述顶面、所述第一虚设引线和第二虚设引线、所述至少一个绝缘接合线、所述第一多个接合线和第二多个接合线、以及所述多个第一引线的一部分。
16.一种半导体器件，包括：
管芯标志；
集成电路管芯，所述集成电路管芯附着到所述管芯标志的顶面；
多个第一引线，所述多个第一引线与所述管芯标志的第一侧边缘间隔开；
虚设引线，所述虚设引线与所述管芯标志的第二侧边缘间隔开，所述第二侧边缘与所述管芯标志的所述第一侧边缘相邻；
多个第一接合线，所述多个第一接合线从所述管芯的顶面上的第一组焊盘延伸到所述多个第一引线的第一组以用于将所述第一组焊盘电连接到第一引线的所述第一组；
多个第二接合线，所述多个第二接合线从所述集成电路管芯的所述顶面上的第二组焊盘延伸到所述多个第一引线的第二组以用于将所述第二组焊盘电连接到第一引线的所述第二组；以及
至少一个绝缘接合线，所述至少一个绝缘接合线从第三焊盘延伸到所述虚设引线并且在所述第一多个接合线和第二多个接合线之间，所述第三焊盘在所述集成电路管芯的顶面上并且在所述集成电路管芯的边缘附近，其中所述至少一个绝缘接合线防止所述多个第二接合线下垂和接触所述多个第一接合线中的接合线。
17.根据权利要求16所述的半导体器件，其中所述至少一个绝缘接合线包括两个绝缘接合线，其中所述第二绝缘接合线从第四焊盘延伸到所述虚设引线，所述第四焊盘在所述集成电路管芯的所述表面上并且靠近所述第三焊盘。
18.根据权利要求16所述的半导体器件，其中所述第一多个接合线和第二多个接合线具有不同的环高度。
19.根据权利要求16所述的半导体器件，其中所述第一多个接合线和第二多个接合线包括裸铜线、裸铝线、和裸金线中的一个。
20.根据权利要求16所述的半导体器件，进一步包括：
管芯附着材料，所述管芯附着材料在所述集成电路管芯和所述管芯标志的所述顶面之间以用于将所述集成电路管芯固定到所述管芯标志的所述顶面；以及
塑封材料，所述塑封材料至少封装了所述集成电路管芯的所述顶面、所述第一虚设引线、所述至少一个绝缘接合线、所述第一多个接合线和第二多个接合线、以及所述多个第一引线的一部分。
CN201410090520.6A 2013-03-12 2014-03-12 接合线的支架 Pending CN104051400A (zh)

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