CN104022024A - Method for repeated ion implantation - Google Patents
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- CN104022024A CN104022024A CN201310066357.5A CN201310066357A CN104022024A CN 104022024 A CN104022024 A CN 104022024A CN 201310066357 A CN201310066357 A CN 201310066357A CN 104022024 A CN104022024 A CN 104022024A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000005468 ion implantation Methods 0.000 title claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 25
- 238000002513 implantation Methods 0.000 claims description 90
- 230000035515 penetration Effects 0.000 claims description 62
- 238000001816 cooling Methods 0.000 claims description 37
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 238000004364 calculation method Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 238000002955 isolation Methods 0.000 abstract 2
- 238000000059 patterning Methods 0.000 description 15
- 230000008602 contraction Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 101100129500 Caenorhabditis elegans max-2 gene Proteins 0.000 description 2
- 101100083446 Danio rerio plekhh1 gene Proteins 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012887 quadratic function Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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Abstract
The invention provides a method for repeated ion implantation. In repeated ion implantation, by limiting queuing time of adjacent ion implantation, the degree of shrinkage distortion of a photoresistor after ion implantation each time is reduced, so that the photoresistor can protect an isolation layer, thereby preventing an ion implantation region from continuously expanding, and preventing implanted ions from permeating into the isolation layer and causing failure of a semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of method of repeatedly Implantation.
Background technology
Implantation (Implantation) is the important method that semiconductor manufacture forms device doped region, along with device complexity is more and more higher, form the required Implantation step of device doped region also more and more, even a device area needs continuous a plurality of Implantation steps to form.For example, lightly doped drain (LDD) generally needs continuous 2 to 3 Implantation steps.
In prior art, wafer 30 is provided with separator 20, and described separator 20 is not wish to be injected into ion, and just in the predetermined Implantation region 40 of wafer 30, injects ion.Before Implantation, general first spin coating photoresistance (Photo resist) on described wafer 30 and described separator 20, and described photoresistance is formed to the photoresistance 10 of patterning by photoetching process, the photoresistance 10 of described patterning has the opening that exposes described wafer 30, and the photoresistance 10 of described patterning must shelter from described separator 20.Generally, the sectional dimension of the photoresistance 10 of described patterning is greater than the sectional dimension of separator 20, to guarantee to cover the end face that described separator 20(should cover described separator 20 comprehensively, also to cover the side certain thickness of described separator 20), thereby utilize described patterning 10 pairs of ions of photoresistance block the object that reaches Selective implantation, as shown in Figure 1.
Yet present inventor finds in actual production, after having carried out repeatedly Implantation step, the region that actual ions is injected has often exceeded the predetermined Implantation region of wafer 30, and then causes semiconductor device failure.
Summary of the invention
The present invention proposes a kind of method of repeatedly Implantation, and its object is to prevent semiconductor device failure.
In order to realize the problems referred to above, the present invention proposes repeatedly the method for Implantation, comprises step:
Wafer is provided, on described wafer, be formed with successively separator and photoresistance, described photoresistance covers described separator, the sectional dimension of described photoresistance is greater than the sectional dimension of described separator, described photoresistance has pattern openings, described pattern openings exposes predetermined Implantation region, and described pattern openings and described separator keep a safe distance;
Carry out repeatedly Implantation, and limit the queuing time of the wafer of adjacent ions injection.
Further, the calculation procedure of described queuing time comprises:
Measure the bottom size of pattern openings and the actual (real) thickness of described photoresistance of described photoresistance, and calculate the minimum thickness of described photoresistance;
The top dimension of measuring the described photoresistance pattern openings of the described photoresistance of different time points in cooling procedure after N secondary ion implantation step, wherein N is positive integer;
Each Implantation region of using the first formula to calculate different time points infiltrates through the depth of penetration to described photoresistance, and draws the correlation curve of described depth of penetration and cooling time;
According to described correlation curve, draw the relation of described depth of penetration and cooling time, and according to the relation of described depth of penetration and cooling time, calculate the minimum value of the depth of penetration in each Implantation region;
The minimum value of N depth of penetration after each Implantation step is added, calculates the minimum total of the depth of penetration after N secondary ion implantation step;
According to the minimum total of described depth of penetration, be less than or equal to the queuing time that described Calculation of Safety Distance goes out the wafer after each Implantation.
Further, described the first formula is:
d
N=1/2(T-B)*h/H，
Described d
nbe the depth of penetration that N secondary ion injects, the pattern openings top dimension that described T is described photoresistance, the pattern openings bottom size that described B is described photoresistance, the minimum thickness that described h is described photoresistance, the actual (real) thickness that described H is described photoresistance.
Further, the pass of described depth of penetration and cooling time is:
d
N=a
Nt
N 2+b
Nt
N+c
N，
Described t
nfor the cooling time that described photoresistance N secondary ion injects, described a
n, b
n, c
nfor constant.
Further, and according to described depth of penetration and the relation of cooling time, calculate the maximum of the depth of penetration of this secondary ion injection zone.
Further, the maximum of depth of penetration after Implantation step is repeatedly added, calculates repeatedly the maximum total value of the depth of penetration after Implantation step.
Further, described maximum total value is greater than described depth of penetration.
Further, safe distance is averagely allocated to the repeatedly depth of penetration in Implantation region, and calculates the queuing time after each Implantation with this.
Compared with prior art; beneficial effect of the present invention is mainly reflected in: the degree of photoresistance contraction distortion after the queuing time injecting by restriction adjacent ions when Implantation repeatedly reduces each Implantation; make described photoresistance can protect described separator; and then prevent that Implantation region from constantly expanding, avoid iontophoretic injection to enter separator and cause semiconductor device failure.
Accompanying drawing explanation
Fig. 1 is Implantation structure schematic diagram;
Fig. 2 is the Implantation structure schematic diagram after photoresistance contraction distortion;
Fig. 3 is the Implantation structure schematic diagram after photoresistance contraction distortion in one embodiment of the invention;
Fig. 4 is depth of penetration and the correlation curve of cooling time in one embodiment of the invention;
Fig. 5 is depth of penetration and the actual curve of cooling time in one embodiment of the invention.
Embodiment
For the ease of understanding, below in conjunction with specific embodiment and accompanying drawing, the present invention is described further.
In background technology, mention, form the required Implantation step of device doped region more and more, even a device area needs continuous a plurality of Implantation steps to form, and through after Implantation step repeatedly, the region that actual ions is injected against regulation (the predetermined Implantation region that has exceeded wafer 300), and then cause semiconductor device failure.Through present inventor, repeatedly study discovery, why there is this problem, be the energy very high (general about 10keV～500keV) of ion during due to Implantation, these high-octane ions can make the surface temperature of the surface of described wafer 300 and the photoresistance 100 of described patterning raise.After Implantation finishes for the first time, the temperature of the photoresistance 100 of described wafer 300 and described patterning can be reduced to room temperature gradually, variation due to temperature, the pattern of the photoresistance 100 of described patterning can shrink distortion, cause the pattern openings of the photoresistance 100 of described patterning to become large, as shown in Figure 2, for example, the cross section of the pattern openings of the photoresistance 100 of described patterning is become as inverted trapezoidal by initial rectangle, thereby cause the pattern edge thickness attenuation of the photoresistance 100 of described patterning, affect the occlusion effect of 100 pairs of described separators 200 of photoresistance of patterning, cause the ion of Implantation for the second time subsequently can be through the photoresistance 100 of described patterning, cause the area in actual Implantation region 400 constantly to expand.Especially, when Implantation step through repeatedly continuous, after each Implantation, the photoresistance 100 of patterning all can shrink distortion, and so actual Implantation region 400 can constantly expand and be uncontrollable.If actual Implantation region 400 continues expand and make iontophoretic injection enter described separator 200, will cause semiconductor device failure.And twice Implantation step interlude (also referred to as queuing time) is longer, photoresistance 100 distortion of patterning are more serious so, and the problems referred to above also will be more serious.For this reason, the present invention reduces the degree of photoresistance contraction distortion after each Implantation by controlling the queuing time of adjacent ions injection technology, prevent semiconductor device failure.
Specifically as shown in Figure 3, the present invention proposes a kind of method of repeatedly Implantation, comprising:
First, wafer 300 is provided, on described wafer 300, form successively separator 200 and photoresistance 100, described photoresistance 100 covers described separator 200, the sectional dimension of described photoresistance 100 is greater than the sectional dimension of separator 200 conventionally, to guarantee to cover described separator 200 comprehensively, described photoresistance 100 is provided with pattern openings, described pattern openings exposes predetermined Implantation region 400, it is the distance at pattern openings bottom and separator 200 edges that described pattern openings and described separator 200 keep certain safe distance X(), as shown in Figure 3;
Then, carry out repeatedly Implantation, and limit the queuing time that adjacent ions is injected.
Wherein, the computational process of described Preset Time comprises:
(1) measure the bottom size B of described photoresistance 100 pattern openings and the actual (real) thickness H of described photoresistance 100, and calculate the minimum thickness h of photoresistance 100, described minimum thickness h refers to as blocking the minimum thickness of the required photoresistance of Implantation, described minimum thickness h can obtain according to common experience, that is, those skilled in the art are tested and can be calculated minimum thickness h by limited number of time;
(2) measure the top dimension T of described photoresistance 100 described photoresistance 100 pattern openings of different time points in cooling procedure after N secondary ion implantation step, wherein N is positive integer;
(3) each Implantation region 400 of using the first formula to calculate different time points infiltrates into the depth of penetration d of described photoresistance 100 bottom portion
n, and draw described depth of penetration d
nwith t cooling time
ncorrelation curve (as shown in Figure 4);
(4) according to described correlation curve, draw described depth of penetration d
nwith t cooling time
nrelation, and according to described depth of penetration d
nwith t cooling time
nrelation calculate the depth of penetration d in each Implantation region 400
nminimum value d
min;
(5) by N depth of penetration d after each Implantation step
nminimum value d
minbe added, calculate the minimum total of the depth of penetration after N secondary ion implantation step;
(6) according to the minimum total of described depth of penetration, be less than or equal to the queuing time that described safe thickness X calculates the wafer after each Implantation.
In the present embodiment, the actual (real) thickness H of described photoresistance 100 is the actual (real) thickness that described photoresistance 100 is coated in described wafer 300 and described separator 200, the minimum thickness h of described photoresistance 100 is that described photoresistance 100 can shelter from Implantation and makes described separator 200 avoid minimum photoresistance 100 thickness of Implantation infringement,, when the actual (real) thickness H of described photoresistance 100 is greater than the minimum thickness h of described photoresistance 100, described photoresistance 100 can protect described separator 200 to make it not to be subject to the infringement of Implantation; When the actual (real) thickness H of described photoresistance 100 is less than the minimum thickness h of described photoresistance 100, described photoresistance 100 can not guarantee that described separator 200 avoids the infringement of Implantation.
Wherein, described photoresistance 100 is after applying, the cross section of the pattern openings that described photoresistance 100 is initial is rectangle, be that the top dimension of described photoresistance 100 initial pattern openings and the bottom size B of described photoresistance 100 equate, Implantation causes the temperature on described photoresistance 100 surfaces to rise, after Implantation is complete, As time goes on the temperature on described photoresistance 100 surfaces can slowly decline and return to normal temperature, yet, reduction along with temperature, described photoresistance 100 is also by the contraction distortion occurring to a certain degree, cause the pattern openings of described photoresistance 100 to become large, as shown in Figure 4, , the cross section of the pattern openings of described photoresistance 100 is become as inverted trapezoidal by initial rectangle, cause the top dimension of described photoresistance 100 pattern openings slowly to expand, become the top dimension T of described photoresistance 100 cooled pattern openings.
Through long-term experiment, inventor finds that too large variation can't occur the bottom size B of described photoresistance 100 pattern openings, and inventor has drawn depth of penetration d in the cooling process of described photoresistance 100
nand the relation between the minimum thickness h of the top dimension T of the bottom size B of described photoresistance 100 pattern openings, described photoresistance 100 pattern openings, the actual (real) thickness H of described photoresistance 100 and described photoresistance 100, that is, and the first formula:
d
N=1/2(T-B)*h/H，
Wherein, d
nit is the depth of penetration that N secondary ion injects;
Because the minimum thickness h of the bottom size B of described photoresistance 100 pattern openings, the actual (real) thickness H of described photoresistance 100 and described photoresistance 100 all can not change along with the variation of time, only there is the top dimension T of described photoresistance 100 cooling rear pattern openings to change along with the variation of time, therefore in conjunction with the known depth of penetration d of the first formula
nalso can change along with the variation of time.
According to the first formula, draw described depth of penetration d
nwith t cooling time
ncorrelation curve, as shown in Figure 4, wherein, described t
nfor the cooling time of described photoresistance N secondary ion injection.
Visible, as t cooling time
nbe less than time t
mtime, described depth of penetration d
nwith t cooling time
nthe approximate quadratic function relation that is.As t cooling time
nbe greater than t
mafter, described depth of penetration d
nalmost reach stable maximum d
max.As depth of penetration d
nwith t cooling time
ncorrelation curve can draw at t cooling time
nbe less than time t
mtime, depth of penetration d
nwith t cooling time
nequation be d
n=a
nt
n 2+ b
nt
n+ c
n, wherein, described a, b, c are constant, described t
mfor described depth of penetration d
nreach stable maximum d
maxtime time.According to depth of penetration d
nwith t cooling time
ncorrelation curve calculate a
n, b
n, c
noccurrence, then according to described equation d
n=a
nt
n 2+ b
nt
n+ c
ncalculate the depth of penetration d of this secondary ion injection zone 300
nmaximum d
max, and will be repeatedly depth of penetration d after Implantation step
nmaximum d
maxbe added, calculate repeatedly the depth of penetration d after Implantation step
nmaximum total value.
Now, as depth of penetration d
nmaximum total value while being less than described safe distance X, illustrate that repeatedly Implantation is without restriction queuing time t
n(be t cooling time
n); As depth of penetration d
nminimum total while being greater than described safe distance X, illustrate that repeatedly ion implantation technology condition does not meet design requirement, need Optimizing Technical as photoresistance type, thickness and ion implantation dosage etc.; Only have the described maximum total value of working as to be greater than described depth of penetration d
n, and as depth of penetration d
nminimum total while being less than described safe distance X, between adjacent Implantation, limit queuing time t and can prevent that described Implantation region 300 from infiltrating through described separator 200 and causing component failure.
For the ease of better understanding, explanation below gives an actual example: certain device technology design rule defines described photoresistance 100, and to make described separator 200 keep minimum safe distance X with described Implantation region 300 be 180 μ m, and in this technological process, need continuous 4 secondary ion implantation steps.So, first, measure the minimum thickness h of the bottom size B of described photoresistance 100 pattern openings, the actual (real) thickness H of described photoresistance 100 and described photoresistance 100; Then measure the top dimension T of the described photoresistance 100 different time points pattern openings in cooling procedure after primary ions implantation step wherein, and draw the depth of penetration d that first three secondary ion injects
1, d
2and d
3with t cooling time
nactual curve, as shown in Figure 5.
The depth of penetration d injecting according to first three secondary ion
1, d
2and d
3with t cooling time
nactual curve 1, curve 2, curve 3 calculate:
a
1=-3.3658E-04，b
1=2.6418E-01，c
1=16.786；
a
2=-3.0628E-04，b
2=2.3250E-01，c
2=26.822；
a
3=-2.8500E-04，b
3=2.1502E-01，c
3=33.462；
So depth of penetration d
1, d
2and d
3with t cooling time
nequation as follows:
d
1=-3.3658E-04t
1 2+2.6418E-01t
1+16.786
d
2=-3.0628E-04t
2 2+2.3250E-01t
2+26.822
d
3=-2.8500E-04t
3 2+2.1502E-01t
3+33.462；
By aforesaid equation, can draw d
min1=16.8, d
max1=68.7, d
min2=26.9, d
max2=71.0, d
min3=33.5, d
max3=74.1.
Due to d
min1+ d
min2+ d
min3=77.2<180 and d
max1+ d
max2+ d
max3=213.8>180 needs to limit the queuing time t of 3 step maximums in this technological process
n(be maximum t cooling time
n): t
1, t
2, t
3; Make d
1=d
2=d
3=180/3=60, can solve respectively maximum queuing time t by aforesaid equation
1=233 minutes, t
2=191 minutes, t
3=156 minutes, in actual production, can flexible allocation d
1, d
2, d
3numerical value, as long as guarantee d
min1+ d
min2+ d
min3>=180.Now, at this kind of device, carry out in technological process, the time of carrying out the second Implantation after Implantation is for the first time no more than 233 minutes, the time of carrying out the 3rd Implantation after the second Implantation is no more than 191 minutes, and the time of carrying out the 4th Implantation after the 3rd Implantation is no more than 156 minutes and can prevents that described Implantation region 300 from infiltrating through described separator 200 and causing component failure.
These are only the preferred embodiments of the present invention, the present invention is not played to any restriction.Any person of ordinary skill in the field; within not departing from the scope of technical scheme of the present invention; the technical scheme that the present invention is disclosed and technology contents are made any type of changes such as replacement or modification that are equal to; all belong to the content that does not depart from technical scheme of the present invention, within still belonging to protection scope of the present invention.
Claims (8)
1. a method for Implantation repeatedly, comprising:
Wafer is provided, on described wafer, be formed with successively separator and photoresistance, described photoresistance covers described separator, the sectional dimension of described photoresistance is greater than the sectional dimension of described separator, described photoresistance has pattern openings, described pattern openings exposes predetermined Implantation region, and described pattern openings and described separator keep a safe distance;
Carry out repeatedly Implantation, and limit the queuing time of the wafer of adjacent ions injection.
2. the method for repeatedly Implantation as claimed in claim 1, is characterized in that, the calculation procedure of described queuing time comprises:
Measure the bottom size of pattern openings and the actual (real) thickness of described photoresistance of described photoresistance, and calculate the minimum thickness of described photoresistance;
The top dimension of measuring the described photoresistance pattern openings of the described photoresistance of different time points in cooling procedure after N secondary ion implantation step, wherein N is positive integer;
Each Implantation region of using the first formula to calculate different time points infiltrates through the depth of penetration to described photoresistance, and draws the correlation curve of described depth of penetration and cooling time;
According to described correlation curve, draw the relation of described depth of penetration and cooling time, and according to the relation of described depth of penetration and cooling time, calculate the minimum value of the depth of penetration in each Implantation region;
The minimum value of N depth of penetration after each Implantation step is added, calculates the minimum total of the depth of penetration after N secondary ion implantation step;
According to the minimum total of described depth of penetration, be less than or equal to the queuing time that described Calculation of Safety Distance goes out the wafer after each Implantation.
3. the method for repeatedly Implantation as claimed in claim 2, is characterized in that, described the first formula is:
d
N=1/2(T-B)*h/H，
Wherein, d
nbe the depth of penetration that N secondary ion injects, the pattern openings top dimension that T is described photoresistance, the pattern openings bottom size that B is described photoresistance, the minimum thickness that h is described photoresistance, the actual (real) thickness that H is described photoresistance.
4. the method for repeatedly Implantation as claimed in claim 3, is characterized in that, the pass of described depth of penetration and cooling time is:
d
N=a
Nt
N 2+b
Nt
N+c
N，
Wherein, t
nfor the cooling time that described photoresistance N secondary ion injects, a
n, b
n, c
nfor constant.
5. the method for repeatedly Implantation as claimed in claim 4, is characterized in that, and according to described depth of penetration and the relation of cooling time, calculates the maximum of the depth of penetration of this secondary ion injection zone.
6. the method for repeatedly Implantation as claimed in claim 5, is characterized in that, the maximum of depth of penetration after Implantation step is repeatedly added, and calculates repeatedly the maximum total value of the depth of penetration after Implantation step.
7. the method for repeatedly Implantation as claimed in claim 6, is characterized in that, described maximum total value is greater than described depth of penetration.
8. the method for repeatedly Implantation as claimed in claim 2, is characterized in that, safe distance is averagely allocated to the repeatedly depth of penetration in Implantation region, and calculates the queuing time after each Implantation with this.
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|---|---|---|---|
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|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116313876A (en) * | 2023-05-25 | 2023-06-23 | 粤芯半导体技术股份有限公司 | Method for monitoring substrate temperature in ion implantation process |
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| JPH05198522A (en) * | 1992-01-23 | 1993-08-06 | Canon Inc | Manufacture of semiconductor device |
| JPH1186776A (en) * | 1997-09-09 | 1999-03-30 | Nissin Electric Co Ltd | Ion-implanting device |
| JP2000164731A (en) * | 1998-11-30 | 2000-06-16 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| CN1088914C (en) * | 1995-03-08 | 2002-08-07 | 现代电子产业株式会社 | Method for fabricating metal oxide semiconductor field effect transistor |
| KR100807501B1 (en) * | 2006-12-27 | 2008-02-26 | 동부일렉트로닉스 주식회사 | Fabricating method of semiconductor device |
-
2013
- 2013-03-01 CN CN201310066357.5A patent/CN104022024B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05198522A (en) * | 1992-01-23 | 1993-08-06 | Canon Inc | Manufacture of semiconductor device |
| CN1088914C (en) * | 1995-03-08 | 2002-08-07 | 现代电子产业株式会社 | Method for fabricating metal oxide semiconductor field effect transistor |
| JPH1186776A (en) * | 1997-09-09 | 1999-03-30 | Nissin Electric Co Ltd | Ion-implanting device |
| JP2000164731A (en) * | 1998-11-30 | 2000-06-16 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| KR100807501B1 (en) * | 2006-12-27 | 2008-02-26 | 동부일렉트로닉스 주식회사 | Fabricating method of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116313876A (en) * | 2023-05-25 | 2023-06-23 | 粤芯半导体技术股份有限公司 | Method for monitoring substrate temperature in ion implantation process |
| CN116313876B (en) * | 2023-05-25 | 2023-08-04 | 粤芯半导体技术股份有限公司 | Method for monitoring substrate temperature in ion implantation process |
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