CN105470259B - The structure of embedded flash memory and the manufacturing method of embedded flash memory - Google Patents

The structure of embedded flash memory and the manufacturing method of embedded flash memory Download PDF

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Publication number
CN105470259B
CN105470259B CN201410466050.9A CN201410466050A CN105470259B CN 105470259 B CN105470259 B CN 105470259B CN 201410466050 A CN201410466050 A CN 201410466050A CN 105470259 B CN105470259 B CN 105470259B
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China
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flash memory
active area
embedded flash
photoresist
light shield
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CN201410466050.9A
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Chinese (zh)
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CN105470259A (en
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胡勇
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上海华虹宏力半导体制造有限公司
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Abstract

The invention proposes a kind of embedded flash memory structure and the manufacturing methods of embedded flash memory, the multiple active areas and multiple virtual active areas kept apart by shallow groove isolation structure are formed in polysilicon device region, by the shallow trench isolation light shield for defining polysilicon device region, pattern shallow trenches isolation photoresist is set to be formed in the top of virtual active area and a part of shallow groove isolation structure, expose active area and another part shallow groove isolation structure, when carrying out ion implanting, in order to not influence the performance of flush memory device, the angle of usual ion implanting is fixed, by adjusting active area, virtual active area, spacing between fleet plough groove isolation structure and the line width and pattern shallow trenches isolation photoresist of pattern shallow trenches isolation photoresist avoids ion pair active area from causing secondary be repeatedly injected, under the premise of not influencing flush memory device, it ensure that MPO The performance of L device, while light shield when can save to form WLSP1, reduce production cost.

Description

The structure of embedded flash memory and the manufacturing method of embedded flash memory

Technical field

The present invention relates to the systems of the structure and embedded flash memory of field of semiconductor manufacture more particularly to a kind of embedded flash memory Make method.

Background technique

In current semiconductor industry, IC products can be divided mainly into three categories type: analog circuit, digital circuit With D/A hybrid circuit, wherein memory device is an important kind in digital circuit.In recent years, embedding in memory device The development for entering formula flash memory (Embedded Flash Memory) is especially rapid.Embedded flash memory is mainly characterized by not powered In the case where can keep for a long time storage information;And have many advantages, such as that integrated level is high, access speed is fast, be easy to wipe and rewrite, Thus it is widely used in the multinomial field such as microcomputer, automation control.

Polycrystalline silicon device (Memory Poly) can provide stable fixed current (Fix for embedded flash memory Current), it is the performance for improving embedded flash memory, needs to introduce MPOL device in design.In manufacture without containing the embedding of MPOL device In the technique for entering formula flash memory, under normal circumstances, need using WLSP1 (the first wordline spacing, Word Line Space 1) light Cover, shelters from all areas in addition to embedded flash memory region, only carries out ion implanting to embedded flash memory region.In order to subtract The use of few light shield, reduces cost, usually borrows GSTI light shield and carries out ion implanting to embedded flash memory device.

In embedded flash memory technical process of the manufacture comprising polycrystalline silicon device, according to prior art, WLSP1 light shield is needed Realize MPOL device substrate and surface doping.If borrowing GSTI light shield according to existing scheme carries out ion implanting, while again The performance of flush memory device is taken into account, the angle of ion implanting, dosage cannot be adjusted, and will cause the excessively high threshold value of MPOL device in this way Voltage influences its performance, so that the light shield of WLSP1 can not be saved, in semiconductor manufacturing industry, it is well known that the valence of light shield Lattice are sufficiently expensive, and manufacturing cost usually calculating at original with light shield, production cost will be will be greatly reduced by saving one piece of light shield.Cause This, light shield when how to save to form WLSP1 when forming the embedded flash memory with storage polycrystalline silicon device is this field skill Art personnel technical problem urgently to be solved.

Summary of the invention

The purpose of the present invention is to provide a kind of structure of embedded flash memory and the manufacturing method of embedded flash memory, Neng Goujie Light shield is saved, production cost is reduced.

To achieve the goals above, the invention proposes a kind of structures of embedded flash memory, comprising: polysilicon device region With embedded flash memory remaining area, the embedded flash memory remaining area is that the embedded flash memory removes the polycrystalline silicon device area Region other than domain;The polysilicon device region includes substrate and the multiple active areas being formed on the substrate and multiple void Quasi- active area, is kept apart between the active area and virtual active area by fleet plough groove isolation structure, the virtual active area and A part of shallow groove isolation structure is located at the lower section of pattern shallow trenches isolation photoresist, the pattern shallow trenches isolation photoresist exposure The active area and another part shallow groove isolation structure out, the active area, virtual active area, fleet plough groove isolation structure and pattern Change shallow trench isolation photoresist and all have predetermined line width, keeps preset space length between the pattern shallow trenches isolation photoresist.

Further, in the structure of the embedded flash memory, the line width range of the active area is 0.2 μm~0.6 μ m。

Further, in the structure of the embedded flash memory, the line width range of the virtual active area is 0.1 μm~ 0.7μm。

Further, in the structure of the embedded flash memory, the line width range of the fleet plough groove isolation structure is 0.1 μm~0.5 μm.

Further, in the structure of the embedded flash memory, the line width model of the pattern shallow trenches isolation photoresist Enclosing is 0.3 μm~1.7 μm, and the preset space length range between the pattern shallow trenches isolation photoresist is 1 μm~1.5 μm.

The invention also provides a kind of manufacturing method of embedded flash memory, the method includes the steps:

Offer include the embedded flash memory structure as described in any one of claims 1 to 5 polysilicon device region and Embedded flash memory remaining area;

The shallow trench isolation light shield for defining the polysilicon device region forms corresponding pattern shallow trenches isolation light Resistance, and the pattern shallow trenches isolation photoresist for being maintained at the formation of embedded flash memory remaining area is constant;

Using pattern shallow trenches isolation photoresist as mask, ion implanting is carried out to the active area.

Further, in the manufacturing method of the embedded flash memory, other than using shallow trench isolation light shield, also Active area light shield, the second wordline spacing light shield, N trap light shield are successively used, is blocked using the photoresist that the active area light shield is formed The active area of polycrystalline silicon device is stated in residence, shelters from the polysilicon device using the photoresist that the second wordline spacing light shield is formed The grid in part region exposes the polysilicon device region using the photoresist that the N trap light shield is formed.

Compared with prior art, the beneficial effects are mainly reflected as follows: polysilicon device region formed by shallow slot The multiple active areas and multiple virtual active areas that isolation structure is kept apart, by the shallow trench isolation for defining polysilicon device region Light shield makes pattern shallow trenches isolation photoresist be formed in the top of virtual active area and a part of shallow groove isolation structure, exposes Active area and another part shallow groove isolation structure, when carrying out ion implanting, in order to not influence the performance of flush memory device, usually from The angle of son injection is fixed, by adjust active area, virtual active area, fleet plough groove isolation structure and pattern shallow trenches every From the line width of photoresist and pattern shallow trenches isolation photoresist between spacing avoid ion pair active area cause it is secondary be repeatedly injected, Under the premise of not influencing flush memory device, light shield when ensure that the performance of MPOL device, while can save to form WLSP1, Reduce production cost.

Detailed description of the invention

Fig. 1 is the diagrammatic cross-section when embedded flash memory without MPOL device carries out ion implanting;

Fig. 2 forms top view when active area and the area GSTI for polysilicon device region in one embodiment of the invention;

Fig. 3 is in one embodiment of the invention along the diagrammatic cross-section of the A-A ' of Fig. 2;

Fig. 4 is the top view that polysilicon device region forms final structure in one embodiment of the invention.

Specific embodiment

The structure of embedded flash memory of the invention and the manufacturing method of embedded flash memory are carried out below in conjunction with schematic diagram More detailed description, which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify herein The present invention of description, and still realize advantageous effects of the invention.Therefore, following description should be understood as this field skill Art personnel's is widely known, and is not intended as limitation of the present invention.

For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend Time, but to those skilled in the art it is only routine work.

The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non- Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.

As mentioned by background technique, during manufacturing embedded flash memory, formed before WLSP1, it is also necessary to use One of light shield, referred to as shallow trench isolation light shield (GSTI light shield), in order to by the shallow groove isolation structure in embedded flash memory region (STI) etching it is more lower, prevent the bridging (bridge) between floating gate (Foating gate), at the same also made of it from Son injection, realization are doped embedded flash memory area substrate and surface, achieve the purpose that save WLSP1 light shield.It is described shallow Trench isolations light shield is must to use, and is the light shield that embedded flash memory natively has.There is the insertion of MPOL device due to being formed The structure of formula flash memory can not save light shield when forming WLSP1, and therefore, inventor uses the knot by changing existing MPOL device Structure, and the shallow trench isolation light shield for accordingly changing definition polysilicon device region replaces shape to realize with shallow trench isolation light shield Light shield is saved when at WLSP1, to achieve the purpose that save light shield, reduce cost, and does not change embedded flash memory region Light shield does not influence the normal process flow in embedded flash memory region.I.e. in superperformance (the suitable threshold value for guaranteeing MPOL device Voltage 1.1v) while, and it is technologic compatible with the realization of embedded flash memory region.

Referring to FIG. 1, Fig. 1 is the diagrammatic cross-section when embedded flash memory without MPOL device carries out ion implanting, Form polysilicon layer 10 in substrate (not shown go out), silicon nitride layer 11 be formed on polysilicon layer 10, need to active area into When the corresponding ion implanting of row, the patterning GSTI photoresist 20 that the GSTI light shield of use is formed is coated on silicon nitride layer 11, cruelly Expose active area, since the angle of ion implanting fixes (ion implanting is as shown by the arrows in Figure 1), when patterning GSTI photoresist 20 Between spacing L it is excessive when, active area can be caused it is secondary be repeatedly injected, be repeatedly injected if there is secondary, will lead to be formed The Vt of embedded flash memory be increased to 2 times, and channel current can very little, influence its performance.Only pattern GSTI photoresist 20 Between spacing L when meeting the requirements, the above problem will not just occur.Therefore, it can be defined in the prior art by some algorithms GSTI light shield, to form satisfactory patterning GSTI photoresist 20.The algorithm can be simplified as:

GSTI={ MCEL not [(((FLGT or DUM_CAP) size 0.17) size-0.17) size 0.08] },

Wherein, GSTI is the generating mode of GSTI light shield, and MCEL is embedded flash memory remaining area and MPOL device Reference lamina, FLGT are the floating gate definition region in embedded flash memory, and DUM_CAP is the capacitor regions except embedded flash memory, not It is logical check operation for " the subtracting " of logical operation, size 0.17) size-0.17), size 0.08 is logical operation, by two Side respectively swells 0.08 μm.

Fig. 2 and Fig. 3 are please referred to, above-mentioned thought is based on, the present embodiment proposes a kind of embedded sudden strain of a muscle with MPOL device The structure deposited, comprising: polysilicon device region 400 and embedded flash memory remaining area (not shown go out), the embedded flash memory Remaining area is region of the embedded flash memory in addition to the polysilicon device region 400;The polysilicon device region 400 include substrate (not shown go out) and the multiple active areas 100 and multiple virtual active area (Dummy that are formed on the substrate ACT) 110, kept apart between the active area 100 and virtual active area 110 by fleet plough groove isolation structure 200, it is described virtual Active area 110 and a part of shallow groove isolation structure 200 are located at the lower section of pattern shallow trenches isolation photoresist 300, the patterning Shallow trench isolation photoresist 300 exposes the active area 100 and another part shallow groove isolation structure 200, the active area 100, Virtual active area 110, fleet plough groove isolation structure 200 and pattern shallow trenches isolation photoresist 300 all have predetermined line width, the figure Preset space length is kept between case shallow trench isolation photoresist 300.

Specifically, the line width W1 range of the active area 100 is 0.2 μm~0.6 μm, e.g. 0.5 μm, it is described virtually to have The line width W2 range of source region 110 is 0.1 μm~0.7 μm, e.g. 0.4 μm, the line width W3 model of the fleet plough groove isolation structure 200 Enclosing is 0.1 μm~0.5 μm, e.g. 0.3 μm, the line width W4 range of the pattern shallow trenches isolation photoresist 300 is 0.3 μm~ 1.7 μm, e.g. 1 μm, the preset space length L1 range that the pattern shallow trenches are isolated between photoresist 300 is 1 μm~1.5 μm, E.g. 1.3 μm.Using this kind of structure, define between the line width and pattern shallow trenches isolation photoresist 300 of each structure Preset space length L1 be will cause to guarantee ion implanting not it is secondary be repeatedly injected, make the ion implanting of an angle from active Close to pattern shallow trenches isolation photoresist 300, nearest distance L2 is 0.6 μm on one side in area 100, but needs to guarantee active area 100 Line width W1 is less than or equal to distance L2, and just can guarantee will not occur secondary be repeatedly injected.

Wherein, active area 100 includes polysilicon 101 and the silicon nitride 102 being formed on polysilicon 101, polysilicon 101 Thickness can be 600 angstroms, and the thickness of silicon nitride 102 can be 800 angstroms, pattern shallow trenches be isolated photoresist 300 with a thickness of 9000 angstroms.

In the another aspect of the present embodiment, it is also proposed that a kind of manufacturing method of embedded flash memory, comprising steps of

Structure including embedded flash memory as described above is provided;

When forming the area GSTI, the shallow trench isolation light shield (GSTI0) of the polysilicon device region 400 is first defined, then Corresponding pattern shallow trenches isolation photoresist 300 is formed, and is maintained at the patterning shallow ridges of embedded flash memory remaining area formation It is constant that photoresist 300 is isolated in slot;

Take pattern shallow trenches isolation photoresist 300 as the mask in the area GSTI, ion note is carried out to the active area 100 Enter.

Likewise, the present embodiment be also defined by some algorithms the shallow trench of the polysilicon device region 400 every From light shield, to form corresponding pattern shallow trenches isolation photoresist 300, specific algorithm is as follows:

GSTI={ MCEL not [((((FLGT or DUM_CAP) size 0.17) size-0.17) size 0.08) or GSTI0] },

Wherein, GSTI is the generating mode of GSTI light shield, and MCEL is embedded flash memory remaining area and MPOL device Reference lamina, FLGT are the floating gate definition region in embedded flash memory, and DUM_CAP is the capacitor regions except embedded flash memory, not It is logical check operation for " the subtracting " of logical operation, size 0.17) size-0.17), size 0.08 is logical operation, by two Side respectively swells 0.08 μm, and or is " adding " of logical operation, and GSTI0 is the customized shallow trench isolation in polysilicon device region 400 Light shield part, " or GSTI0 " are the modification in the present invention to the generating mode of GSTI light shield, and final GSTI photoresist has been added certainly This part of the GSTI0 of row definition.

Therefore, it just can be realized only to do the shallow trench isolation light shield of polysilicon device region 400 using such mode and change Become, the shallow trench isolation light shield without changing remaining area makes shallow trench isolation under the premise of not influencing the technique of remaining area Light shield plays the role of achieving the purpose that reduce cost so as to save the light shield of WLSP1 as formation WLSP1 light shield.

In addition, the technique realize with the embedded flash memory process compatible that is free of MPOL device, will not to existing production capacity and Operation impacts.Light shield adjusts accordingly as follows: GSIT light shield has modified the part of polysilicon device region 400, such as above It is described;Active area light shield has modified the part of polysilicon device region 400, the part as shown in active area 100 in Fig. 2; WLSP2 light shield has modified the part of polysilicon device region 400, the part as shown in grid 500 in Fig. 4.

In the method that the present embodiment proposes, in forming the structure with the embedded flash memory of MPOL device, in addition to using Except shallow trench isolation light shield, active area light shield, the second wordline spacing light shield (WLSP2), N trap light shield are also successively used (NGRD), the active area that the polycrystalline silicon device is sheltered from using the photoresist that the active area light shield is formed, using described second The photoresist that wordline spacing light shield is formed shelters from the grid of the polysilicon device region, the light formed using the N trap light shield Resistance exposes the polysilicon device region.

To sum up, in the structure of embedded flash memory provided in an embodiment of the present invention and the manufacturing method of embedded flash memory, Polysilicon device region forms the multiple active areas and multiple virtual active areas kept apart by shallow groove isolation structure, more by defining The shallow trench isolation light shield of crystal silicon device area, pattern shallow trenches are isolated, and photoresist is formed in virtual active area and a part is shallow The top of recess isolating structure exposes active area and another part shallow groove isolation structure, when carrying out ion implanting, in order not to shadow The performance of flush memory device is rung, the angle of usual ion implanting is fixed, by adjusting active area, virtual active area, shallow trench Spacing between isolation structure and the line width and pattern shallow trenches isolation photoresist of pattern shallow trenches isolation photoresist avoids ion To active area cause it is secondary be repeatedly injected, under the premise of not influencing flush memory device, ensure that the performance of MPOL device, while energy Enough light shields saved when forming WLSP1, reduce production cost.

The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still Within belonging to the scope of protection of the present invention.

Claims (7)

1. a kind of structure of embedded flash memory characterized by comprising polysilicon device region and embedded flash memory remaining area Domain, the embedded flash memory remaining area are region of the embedded flash memory in addition to the polysilicon device region;It is described Polysilicon device region includes substrate and the multiple active areas and multiple virtual active areas that are formed on the substrate, described active Kept apart between area and virtual active area by fleet plough groove isolation structure, the virtual active area and a part of shallow groove isolation structure Positioned at the lower section of pattern shallow trenches isolation photoresist, pattern shallow trenches isolation photoresist exposes the active area and another Part shallow groove isolation structure, the pattern shallow trenches isolation photoresist are the shallow trench by defining the polysilicon device region It is isolated what light shield was formed;Wherein, light is isolated in the active area, virtual active area, fleet plough groove isolation structure and pattern shallow trenches Resistance all has predetermined line width, preset space length is kept between the pattern shallow trenches isolation photoresist, to hold to the active area When row ion implanting, make the ion implanting of fixed angle that photoresist side be isolated close to the pattern shallow trenches from the active area Minimum distance be more than or equal to the active area line width.
2. the structure of embedded flash memory as described in claim 1, which is characterized in that the line width range of the active area is 0.2 μ M~0.6 μm.
3. the structure of embedded flash memory as described in claim 1, which is characterized in that the line width range of the virtual active area is 0.1 μm~0.7 μm.
4. the structure of embedded flash memory as described in claim 1, which is characterized in that the line width model of the fleet plough groove isolation structure Enclose is 0.1 μm~0.5 μm.
5. the structure of embedded flash memory as described in claim 1, which is characterized in that the pattern shallow trenches isolation photoresist Line width range is 0.3 μm~1.7 μm, and the preset space length range between the pattern shallow trenches isolation photoresist is 1 μm~1.5 μ m。
6. a kind of manufacturing method of embedded flash memory, which is characterized in that the method includes the steps:
Offer includes the structure of the embedded flash memory as described in any one of claims 1 to 5;
The shallow trench isolation light shield for defining the polysilicon device region forms corresponding pattern shallow trenches isolation photoresist, and The pattern shallow trenches isolation photoresist for being maintained at the formation of embedded flash memory remaining area is constant;
Using pattern shallow trenches isolation photoresist as mask, ion implanting is carried out to the active area.
7. the manufacturing method of embedded flash memory as claimed in claim 6, which is characterized in that in addition to using shallow trench isolation light shield Except, active area light shield, the second wordline spacing light shield, N trap light shield are also successively used, the light formed using the active area light shield Resistance shelters from the active area of the polycrystalline silicon device, is sheltered from using the photoresist that the second wordline spacing light shield is formed described more The grid of crystal silicon device area exposes the polysilicon device region using the photoresist that the N trap light shield is formed.
CN201410466050.9A 2014-09-12 2014-09-12 The structure of embedded flash memory and the manufacturing method of embedded flash memory CN105470259B (en)

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CN101256981A (en) * 2007-03-02 2008-09-03 富士通株式会社 Semiconductor device and method of manufacturing the same

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US8513105B2 (en) * 2010-10-14 2013-08-20 Texas Instruments Incorporated Flexible integration of logic blocks with transistors of different threshold voltages

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