CN106449387A - Method for improving durability of flash memory through junction morphology - Google Patents
Method for improving durability of flash memory through junction morphology Download PDFInfo
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- CN106449387A CN106449387A CN201611086062.4A CN201611086062A CN106449387A CN 106449387 A CN106449387 A CN 106449387A CN 201611086062 A CN201611086062 A CN 201611086062A CN 106449387 A CN106449387 A CN 106449387A
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- Prior art keywords
- flash memory
- internal junction
- storage tube
- durability
- ion implanting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Abstract
The invention discloses a method for improving durability of a flash memory through junction morphology. The method comprises the following steps: rotating a silicon piece that an internal junction is formed in a 2T embedded flash memory unit array for 90 degrees, and injecting ions in directions of a storage tube and the grid of a selection tube; inclining an ion injection angle, and injecting the internal junction far away from an isolating area by virtue of a shadow effect of the height of the isolating area; performing a first time of ion injection; further rotating the silicon piece that the internal junction is formed in the 2T embedded flash memory unit array for 90 degrees, and injecting the ions in the directions of the storage tube and the grid of the selection tube; at the same time, inclining the ion injection angle; performing a second time of ion injection. Therefore, influence of an interface state in the programming and erasure process can be alleviated, and the durability of the flash memory can be improved.
Description
Technical field
The invention belongs to technical field of semiconductors, it is related to the test circuit of chip, more particularly, to one kind is a kind of passes through to tie shape
The method that looks improve flash memory durability.
Background technology
Flash disk be based on flash memory be storage medium, a kind of storage mode with USB as interface；Flash disk
As soon as occurring, " terminator of floppy disk " is considered by computer insider, the memory capacity of flash disk grows with each passing day, present highest
The flash disk every of grade can accommodate the information being equivalent to 1500 floppy disks, and flash memory disk technology has also been used digital phase
The frontiers such as machine, walkman.
To have the advantages that high density, low price, electrically programmable and erasing have been widely used as non-volatile due to it for flash memory
The optimal choice of memory body application.Although the development and application initially for flash memory is for single flash memory products, embedding
Entering formula flash memory can provide more advantages.
Embedded flash memory is to be combined existing flash memory from physics or electricity with existing logic module, provides more
Various performance.Each unit of 2T embedded flash memory is made up of two transistor-storage tubes and selecting pipe, and it is due to leading to
Cross selecting pipe to reduce external disturbance (for example, programming interference or erasing crosstalk) or even forgo and be widely used.
Refer to Fig. 1, Fig. 1 show 2T embedded flash memory cell array schematic diagram in prior art.As illustrated, 2T is embedding
Enter formula flash memory and include N-type and p-type storage tube composition.
Refer to Fig. 2, Fig. 2 show the embedded storage tube of Fig. 1 in figure 2T and selects tubular construction (along Figure 1A A ' dotted line side
To) cut-away illustration.As shown in Fig. 2 this 2T flash memory structure is in addition to comprising storage tube and selecting pipe, in storage tube and selection
Pipe also comprises therebetween shared internal junction, and this internal junction is used as the drain terminal of storage tube, accepts from selecting pipe to storage tube
Voltage transfer.
This internal junction and storage tube gate overlap region are that the having electronic tunnelling of taking to for storage tube induces thermoelectron
The region that injection mode (Band-to-band tunnel-induced hot-electron (BTBTIHE)) programs.
Refer to Fig. 3, Fig. 3 is 2T internal junction position view in prior art；Wherein, along the arrow in Figure 1B B ' dotted line direction
Head represents the direction of knot ion implanting.As shown in figure 3, the 2T structure in the prior art mainly makes for the formation of internal junction
Formed with vertical ion implanting, the area of knot can be maximized by this structure, increases electron injection during programming.
However, this method can produce impact for the durability of flash memory, during electron injection, have electronics and enter
Enter the near interface (as shown in Figure 4) to active area and isolation area, electronics is by the interface of the neighbouring isolation area of internal junction and active area
Capture, can reduce the electron injection efficiency of programming.
Equally, in the erasing stage of raceway groove Fowler-Nordheim (FN), the electrons of this capture make erasing speed become
Slowly, or even make erasing complete, lead to wipe window and decline.
Because the interfacial state that injection is formed can affect the durability of whole flash memory, (durability refers to that flash memory passes through certain volume
The holding capacity of programmed and erased window after journey and erasing circulation.It is the major criterion weighing flash capabilities).Therefore, how to keep away
Exempt from flash memory-durability to decline is the problem that those skilled in the art need to solve.
Content of the invention
In order to overcome problem above, the present invention is intended to provide a kind of method that flash memory durability is improved by knot pattern, its
Aim to solve the problem that due to electronics enter into the near interface of active area and isolation area when, electronics is tied nearby isolation area and active area
Interface captures, and can reduce the electron injection efficiency of programming, and because the change of programmed and erased window leads under the durability of flash memory
Fall.
For achieving the above object, technical scheme is as follows：
A kind of method improving flash memory durability by knot pattern, the internal junction of 2T embedded flash memory cell array forms and is
Formed by ion implanting；Wherein, described 2T embedded flash memory structure is in addition to comprising storage tube and selecting pipe, described
Storage tube and selecting pipe also comprise therebetween shared internal junction, and described internal junction is used as the drain terminal of described storage tube, accept
From described selecting pipe to the voltage transfer of described storage tube；It is characterized in that, comprise the steps：
Step S1：90 degree of silicon slice rotating after internal junction will be formed in 2T embedded flash memory cell array, make ion implanting
Along described storage tube and selection tube grid direction；Angle-tilt ion implant angle simultaneously；
Step S2：Carry out first time ion implanting；
Step S3：Revolve forming the silicon chip after internal junction in 2T embedded flash memory cell array again on the position of step S1
It turn 90 degrees, still make ion implanting along described storage tube and select tube grid direction；Also tilt and the ion in step S1 simultaneously
Implant angle；
Step S4：Carry out second ion implanting, thus the impact of the interfacial state during reducing programmed and erased.
Preferably, described inclined twice ion implantation angle is identical.
Preferably, described angle-tilt ion implant angle is highly relevant according to described isolation area, and it utilizes isolation area height
Shadow effect makes the injection of internal junction away from isolation area.
Preferably, described angle-tilt ion implant angle defines according to the thickness of described isolation area laying and technique.
From technique scheme as can be seen that technical scheme, from reducing even elimination effect of the interface, is led to
Cross the silicon chip changing internal junction injection and ion implanting direction, 90 degree of silicon slice rotating angle-tilt ion implant angle simultaneously utilizes
The shadow effect of isolation area height makes the injection of knot away from isolation area, thus the shadow of the interfacial state during reducing programmed and erased
Ring；And inject at twice, make ion implanting along storage and select tube grid direction, angle-tilt ion implant angle simultaneously, can drop
The probability that low electronics is captured by interfacial state, reduces the impact to programmed and erased window, improves the durability of flash cell.
Brief description
Fig. 1 show 2T embedded flash memory cell array schematic diagram in prior art
Fig. 2 show the embedded storage tube of Fig. 1 in figure 2T and selects the cutting of tubular construction (along Figure 1A A ' dotted line direction) to show
It is intended to
Fig. 3 be prior art in 2T internal junction position view, wherein, along Figure 1B B ' dotted line direction arrow represent knot from
The direction of son injection
Fig. 4 electronics enters into the schematic diagram of active area near internal junction and isolation region interface
Fig. 5 is the schematic flow sheet improving flash memory durability method in the embodiment of the present invention by tying pattern
Fig. 6 is 2T internal junction position view in the embodiment of the present invention, and wherein, arrow represents the direction of knot ion implanting
Fig. 7 is the schematic diagram away from interfacial state for the diffusion profiles of internal junction injection in the embodiment of the present invention
Specific embodiment
Embody feature of present invention to describe in detail in the explanation of back segment with the embodiment of advantage.It should be understood that the present invention
Can have various changes in different examples, it neither departs from the scope of the present invention, and therein illustrate and be shown in
Substantially regard purposes of discussion, and be not used to limit the present invention.
Below in conjunction with accompanying drawing, by a kind of side improving flash memory durability by tying pattern to the present invention for the specific embodiment
Method further describes.
It should be noted that the method that flash memory durability is improved by knot pattern of the present invention, for 2T embedded flash memory
It is in the processing step being formed using ion implanting that cell array is formed for internal junction；Wherein, 2T embedded flash memory structure
In addition to comprising storage tube and selecting pipe, also comprise therebetween shared internal junction in storage tube and selecting pipe, internal junction is used
Make the drain terminal of storage tube, accept the voltage transfer from selecting pipe to storage tube.
Refer to Fig. 5, Fig. 5 is that the flow process improving flash memory durability method in the embodiment of the present invention by tying pattern is illustrated
Figure.As illustrated, the flow process that should improve flash memory durability method by tying pattern comprises the steps：
Step S1：90 degree of silicon slice rotating after internal junction will be formed in 2T embedded flash memory cell array, make ion implanting
Along storage tube and selection tube grid direction；Angle-tilt ion implant angle simultaneously.
Specifically, technical scheme, from reducing even elimination effect of the interface, is injected by changing internal junction
Silicon chip and ion implanting direction, by 90 degree of silicon slice rotating angle-tilt ion implant angle simultaneously, using the shade of isolation area height
Effect makes the injection of knot away from isolation area, thus reducing the impact of programmed and erased process interface states.
In an embodiment of the present invention, angle-tilt ion implant angle can be according to isolation area height adjustment, for example, to isolate
As a example area's height is 180 angstroms, the interplanar distance due to silicon chip is about 2.5 angstroms, if it is considered that interfacial state is 20 near isolation area
Near silicon atom, then the angle tilting can be：
Arctang* (50/180)=15.52 degree
Additionally, specific angle-tilt ion implant angle isolation area height then needs the thickness according to above isolation area laying
To define with technique.
Refer to Fig. 6, Fig. 6 is 2T internal junction position view in the embodiment of the present invention.As shown in fig. 6, implementation steps S2：
Carry out first time ion implanting；Wherein, arrow represents the direction of knot ion implanting.
After the completion of above-mentioned steps, then carry out the ion implanting of wafer another side, it is preferred that inclined twice ion implantation angle
Identical.
Step S3：Revolve forming the silicon chip after internal junction in 2T embedded flash memory cell array again on the position of step S1
It turn 90 degrees, still make ion implanting along storage tube and select tube grid direction；Also tilt and the ion implanting in step S1 simultaneously
Angle；
Step S4：Carry out second ion implanting, thus the impact of the interfacial state during reducing programmed and erased.
After the completion of above-mentioned steps, refer to Fig. 7, Fig. 7 be the embodiment of the present invention in internal junction injection diffusion profiles away from
The schematic diagram of interfacial state.As illustrated, due to the injection of electronics and remove away from interfacial state during programmed and erased, can drop
The probability that low electronics is captured by interfacial state, reduces the impact to programmed and erased window, improves 2T embedded flash memory cell array
Durability.
Above is only embodiments of the invention, and embodiment simultaneously is not used to limit the scope of patent protection of the present invention, therefore
The equivalent structure change that the description of every utilization present invention and accompanying drawing content are made, should be included in the protection of the present invention in the same manner
In the range of.
Claims (4)
1. a kind of method improving flash memory durability by knot pattern, for 2T embedded flash memory cell array for internal junction shape
One-tenth is in the processing step being formed using ion implanting；Wherein, described 2T embedded flash memory structure except comprise storage tube and
Outside selecting pipe, also comprise therebetween shared internal junction in described storage tube and selecting pipe, described internal junction is used as described depositing
The drain terminal of storage pipe, accepts from described selecting pipe to the voltage transfer of described storage tube；It is characterized in that, comprise the steps：
Step S1：90 degree of silicon slice rotating after internal junction will be formed in 2T embedded flash memory cell array, make ion implanting along institute
State storage tube and select tube grid direction；Angle-tilt ion implant angle simultaneously；
Step S2：Carry out first time ion implanting；
Step S3：Rotate 90 by forming the silicon chip after internal junction in 2T embedded flash memory cell array again on the position of step S1
Degree, still makes ion implanting along described storage tube and select tube grid direction；Also angle-tilt ion implant angle simultaneously；
Step S4：Carry out second ion implanting, thus the impact of the interfacial state during reducing programmed and erased.
2. according to claim 1 by tie pattern improve flash memory durability method it is characterised in that described inclined twice from
Sub- implant angle is identical.
3. according to claim 1 and 2 by tie pattern improve the method for flash memory durability it is characterised in that described incline
Oblique ion implant angle is highly relevant according to described isolation area, and it makes the injection of internal junction using the shadow effect of isolation area height
Away from isolation area.
4. according to claim 1 and 2 by tie pattern improve the method for flash memory durability it is characterised in that described incline
Oblique ion implant angle defines according to the thickness of described isolation area laying and technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611086062.4A CN106449387A (en) | 2016-11-30 | 2016-11-30 | Method for improving durability of flash memory through junction morphology |
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|---|---|---|---|
| CN201611086062.4A CN106449387A (en) | 2016-11-30 | 2016-11-30 | Method for improving durability of flash memory through junction morphology |
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| CN106449387A true CN106449387A (en) | 2017-02-22 |
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