CN105097707A - Memory element and manufacturing method thereof - Google Patents
Memory element and manufacturing method thereof Download PDFInfo
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- CN105097707A CN105097707A CN201410211577.7A CN201410211577A CN105097707A CN 105097707 A CN105097707 A CN 105097707A CN 201410211577 A CN201410211577 A CN 201410211577A CN 105097707 A CN105097707 A CN 105097707A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 238000000034 method Methods 0.000 claims abstract description 76
- 238000005468 ion implantation Methods 0.000 claims abstract description 20
- 230000002262 irrigation Effects 0.000 claims description 48
- 238000003973 irrigation Methods 0.000 claims description 48
- 238000002955 isolation Methods 0.000 claims description 32
- 238000005516 engineering process Methods 0.000 claims description 22
- 230000005641 tunneling Effects 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000007667 floating Methods 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 12
- 239000004020 conductor Substances 0.000 description 39
- 239000000463 material Substances 0.000 description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 239000003989 dielectric material Substances 0.000 description 10
- 238000002513 implantation Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 239000000243 solution Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000012937 correction Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
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- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Abstract
The invention provides a memory element and a manufacturing method thereof. The manufacturing method of the memory element comprises the step of adopting a mask layer as an implanted mask, and subjecting the mask layer to the ion implantation process to form a first embedded type doped region and a second embedded type doped region in a substrate. The first embedded type doped region extends along a first direction to be electrically connected with a first doped region, a second doped region and a third doped region via a control grid, wherein the first doped region, the second doped region and the third doped region are arranged at the two sides of the control grid. The second embedded type doped region extends along a second direction and is positioned in the substrate below the third doped region. The second embedded type doped region is electrically connected with the third doped region. Meanwhile, the first embedded type doped region is electrically connected with the second embedded type doped region.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of memory cell and manufacture method thereof.
Background technology
Nonvolatile memory due to have stored in the data advantage that also can not disappear after a loss of power, therefore must possess this type of memory body in many electric equipment products, to maintain the normal running of electric equipment products.Particularly, fast flash memory bank (FlashMemory) due to have can repeatedly carry out data stored in operations such as, reading, erasings, so become a kind of memory cell that PC and electronic equipment extensively adopt.
Along with the increase of element integrated level, component size constantly reduces.But fast flash memory bank is not that each component can continue to reduce, and must maintain certain size.For example, when manufacturing fast flash memory bank, usually the size of source electrode line and source contacts can be made comparatively be greater than the size of bit line and drain contact window, to reduce sheet resistor.But adopt this kind of method, the layout of character line is quite complicated, character line is by being designed to bending during source electrode line, and need consider complicated optical proximity effect correction problem, therefore, the appropriate litigation fees of its light shield is high.In addition, its process margin is also very little, the problem such as easily cause the uniformity not good.
As can be seen here, above-mentioned existing memory cell and manufacture method thereof, in product structure, manufacture method and use, obviously still have inconvenience and defect, and are urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development always, and common product and method do not have appropriate structure and method to solve the problem, this is obviously the anxious problem for solving of relevant dealer.Therefore how to found a kind of new memory cell and manufacture method thereof, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
The object of the invention is to, overcome the defect of existing memory cell and manufacture method existence thereof, and a kind of new memory cell and manufacture method thereof are provided, technical problem to be solved makes its sheet resistor that can reduce source electrode line and source contacts, is very suitable for practicality.
Another object of the present invention is to, overcome the defect of existing memory cell and manufacture method existence thereof, and a kind of new memory cell and manufacture method thereof are provided, technical problem to be solved is that the light shield making it use can not need to carry out too complicated optical proximity effect correction, thus is more suitable for practicality.
Another object of the present invention is, overcome the defect of existing memory cell and manufacture method existence thereof, and a kind of new memory cell and manufacture method thereof are provided, technical problem to be solved be make its can with existing process integration, thus be more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.The manufacture method of a kind of memory cell proposed according to the present invention, comprise and form multiple isolation structure in the substrate, each isolation structure extends at first direction.Form multiple control gate over the substrate, each control gate extends in second direction, and described first direction is different from described second direction.Below each control gate, the described substrate between two isolation structures of arbitrary neighborhood sequentially forms tunneling dielectric layer, dielectric layer between floating grid and grid.The both sides of the described control gate in the firstth district of described substrate form the first doped region respectively, the both sides of the described control gate in the secondth district of described substrate form the second doped region respectively and form multiple 3rd doped region in the 3rd districts of described substrate, and wherein said 3rd district is positioned between the firstth district and the secondth district.Form cover curtain layer over the substrate, described cover curtain layer has the first crossing opening and the second opening.Described first opening extends at described first direction, at least expose described first doped region of part, described second doped region of part, described 3rd doped region of part and the described control gate of part, and described second opening extends in described second direction, expose the described isolation structure in described 3rd district and described 3rd doped region.Remove the described isolation structure that described second opening is exposed, aim at irrigation canals and ditches voluntarily to form multiple first in described substrate.With described cover curtain layer for implanting cover curtain, carry out ion implantation technology, to form the first doping region in embedding type and the second doping region in embedding type.First doping region in embedding type extends at described first direction, be arranged in described first opening exposed and by the described substrate below described control gate, be electrically connected exposed described first doped region of described first opening, described second doped region and described 3rd doped region.Second doping region in embedding type extends in described second direction, the described substrate and described first be arranged in below exposed described 3rd doped region of described second opening aims at the described substrate of trench bottom and lateral wall circumference voluntarily, and being electrically connected described 3rd doped region, described first doping region in embedding type is electrically connected described second doping region in embedding type.Remove described cover curtain layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid memory cell, is also included in and is electrically connected with described first doping region in embedding type and forms at least one first source contacts near on described first doped region of described second doping region in embedding type.Be electrically connected with described first doping region in embedding type and forming at least one second source contacts near on described second doped region of described second doping region in embedding type.
The manufacture method of aforesaid memory cell, wherein said first opening exposes at least two the first adjacent doped regions, at least two adjacent the second doped regions, at least two adjacent the 3rd doped regions, at least one isolation structure and the described control gate of part, and when carrying out formation described first and aiming at the step of irrigation canals and ditches voluntarily, also comprise and remove the exposed described isolation structure of described first opening, irrigation canals and ditches are aimed at voluntarily to form multiple second, and described first doping region in embedding type also extends to described second aims at voluntarily in the described substrate of trench bottom and lateral wall circumference.
The manufacture method of aforesaid memory cell, also comprises: in described firstth district, aiming at formation one first source contacts on irrigation canals and ditches voluntarily near described second of the second doping region in embedding type, is electrically connected with described first doping region in embedding type; And in described secondth district, aiming at formation one second source contacts on irrigation canals and ditches voluntarily near described second of the second doping region in embedding type, be electrically connected with described first doping region in embedding type.
The manufacture method of aforesaid memory cell, wherein said ion implantation technology is inclination angle ion implantation technology, and the angle of the implanted ions direction of wherein said inclination angle ion implantation technology and the normal of described substrate is 0 degree to 35 degree.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of memory cell that the present invention proposes, comprise substrate, comprise one first district, one second district and one the 3rd district, wherein said 3rd district is positioned between described firstth district and described secondth district.Have multiple first in substrate and aim at irrigation canals and ditches voluntarily.First doping region in embedding type, extends at a first direction, is arranged in the described substrate in described firstth district of part, described secondth district of part and described 3rd district of part.Second doping region in embedding type, extend in a second direction, be arranged in the described substrate that described first aims at described 3rd district of trench bottom and lateral wall circumference voluntarily, and described first doping region in embedding type and described second doping region in embedding type are electrically connected, described first direction is different from described second direction.Multiple control gate, extends in described second direction, is positioned at the described types of flexure of the both sides of described second doping region in embedding type, and strides across described first doping region in embedding type.Memory cell also comprises dielectric layer between multiple floating grid, multiple tunneling dielectric layer and multiple grid.Each floating grid is between corresponding control gate and described substrate.Each tunneling dielectric layer is between corresponding floating grid and described substrate.Between each grid, dielectric layer is between corresponding floating grid and corresponding control gate.Multiple first doped region, is arranged in the described substrate of control gate both sides described in each, described firstth district.Multiple second doped region, is arranged in the described substrate of control gate both sides described in each, described secondth district.Multiple 3rd doped region, is arranged in the described substrate in described 3rd district.Described first doping region in embedding type, through below described control gate, is electrically connected described first doped region of part, described second doped region of part and described 3rd doped region of part, and described second doping region in embedding type is electrically connected described 3rd doped region.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory cell, also comprises: the first source contacts, in described firstth district, is positioned at and is electrically connected with described first doping region in embedding type and near on described first doped region of described second doping region in embedding type; And second source contacts, in described secondth district, be positioned at and be electrically connected with described first doping region in embedding type and near on described second doped region of described second doping region in embedding type.
Aforesaid memory cell, wherein said first doping region in embedding type is electrically connected the first adjacent doped region of at least two row, the second doped region that at least two row are adjacent and at least two adjacent the 3rd doped regions, and the majority individual second more extended in described substrate is aimed in the described substrate of trench bottom and lateral wall circumference voluntarily, wherein said second aims at irrigation canals and ditches voluntarily extends in a line at described first direction, between the first doped region that described in being electrically connected in described first doping region in embedding type, at least two row are adjacent, between the second doped region that described at least two row are adjacent and between at least two adjacent the 3rd doped regions.
Aforesaid memory cell, also comprises: the first source contacts, is arranged in described firstth district and aims on irrigation canals and ditches voluntarily near described second of described second doping region in embedding type, be electrically connected with described first doping region in embedding type; And second source contacts, be arranged in described secondth district and aim on irrigation canals and ditches voluntarily near described second of described second doping region in embedding type, be electrically connected with described first doping region in embedding type.
Aforesaid memory cell, also comprises: at least two the first source contacts, in described firstth district, is positioned at and is electrically connected with described first doping region in embedding type and near at least two adjacent the first doped regions described in described second doping region in embedding type; And at least two one second source contacts, in described secondth district, be positioned at and be electrically connected with described first doping region in embedding type and near at least two adjacent the second doped regions described in described second doping region in embedding type.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, memory cell of the present invention and manufacture method thereof at least have following advantages and beneficial effect:
One, memory cell of the present invention and manufacture method thereof, can reduce the sheet resistor of source electrode line and source contacts.
Two, memory cell of the present invention and manufacture method thereof, the light shield used can not need to carry out too complicated optical proximity effect correction.
Three, memory cell of the present invention and manufacture method thereof, can with existing process integration.
In sum, the invention relates to a kind of memory cell and manufacture method thereof.The manufacture method of this memory cell, to comprise with cover curtain layer as implantation cover curtain, carries out ion implantation technology, to form the first doping region in embedding type and the second doping region in embedding type in the substrate.First doping region in embedding type extends at first direction, by described control gate, is electrically connected the first doped region of control gate both sides, the second doped region and the 3rd doped region.Second doping region in embedding type extends in described second direction, is arranged in the substrate below the 3rd doped region, be electrically connected the 3rd doped region, and the first doping region in embedding type is electrically connected the second doping region in embedding type.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A to Fig. 1 E is the vertical view of the flow process of the manufacture method of the memory cell that foundation first embodiment of the invention illustrates.
Fig. 2 A to Fig. 2 E is the generalized section illustrating Figure 1A to Fig. 1 E tangentially II-II.
Fig. 3 A to Fig. 3 E is the generalized section illustrating Figure 1A to Fig. 1 E tangentially III-III.
Fig. 4 A to Fig. 4 E illustrates Figure 1A to Fig. 1 E tangentially IV-IV generalized section.
Fig. 5 is the vertical view of the manufacture method of the memory cell that foundation second embodiment of the invention illustrates.
Fig. 6 is the vertical view of the manufacture method of the memory cell that foundation third embodiment of the invention illustrates.
Fig. 7 is the vertical view of the manufacture method of the memory cell that foundation fourth embodiment of the invention illustrates.
Fig. 8 is the vertical view of the manufacture method of the memory cell that foundation fifth embodiment of the invention illustrates.
10: substrate
11: well region
12: isolation structure
13: active region
14,14a: tunneling dielectric layer
16,16a, 20: conductor layer
18: dielectric layer between grid
22,22a, 22b, 22c: doped region
102nd: the first district
104th: the second district
106: the three districts
200,500,600,700,800: cover curtain layer
202,502,602,702,802: the first openings
204,504,604,704,804: the second openings
206,208,506,508,606,608,708,806,808: aim at irrigation canals and ditches voluntarily
210: ion implantation technology
212,214,512,514,612,614,712,714,812,814: doping region in embedding type
216a, 216b, 220a, 220b, 516a, 516b, 520a, 520b, 616,620,716,72,816a, 816b, 816c, 820a, 820b, 820c: source contacts
218,218a, 222,222a: drain contact window
A: region
P1, P2: path
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the memory cell proposed according to the present invention and its embodiment of manufacture method, structure, method, step, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, should to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the present invention.
Figure 1A to Fig. 1 E is the vertical view of the flow process of the manufacture method of the memory cell that foundation first embodiment of the invention illustrates.Fig. 2 A to Fig. 2 E illustrates the generalized section along Figure 1A to Fig. 1 E tangent line II-II.Fig. 3 A to Fig. 3 E illustrates the generalized section along Figure 1A to Fig. 1 E tangent line III-III.Fig. 4 A to Fig. 4 E illustrates along Figure 1A to Fig. 1 E tangent line IV-IV generalized section.
Refer to shown in Figure 1A, substrate 10 is provided.Substrate 10 comprises the first district 104 of district 102, second and the 3rd district 106.3rd district 106 is between the first district 102 and the second district 104.Substrate 10 such as has Semiconductor substrate (SemiconductorOverInsulator, SOI) on Semiconductor substrate, semiconducting compound substrate or insulating barrier.Semiconductor is such as the atom of IVA race, such as silicon or germanium.Semiconducting compound substrate is such as the semiconducting compound that the atom of IVA race is formed, such as, be carborundum or germanium silicide, or the semiconducting compound (being such as GaAs) that IIIA race atom and VA race atom are formed.Well region 11 can be formed in substrate 10.Well region 11 has the admixture of the first conductivity type.In one embodiment, the admixture of the first conductivity type is such as P type admixture.In another embodiment, the first conductivity type admixture is such as N-type admixture.P type admixture such as boron.N-type admixture is such as phosphorus or arsenic.
Many isolation structures 12 that first direction extends are formed in, to define multiple active region 13 in the well region 11 of substrate 10.First direction can be X-direction or Y-direction.The present embodiment graphic in, first direction is such as Y-direction.The formation method of isolation structure 12 can be shallow trench isolation method (STI) or deep trenches isolation method (DTI).The material of isolation structure 12 is insulating material, such as, be silica.Oxide be such as spin-on glasses (Spin-OnGlass,
sOG) or high density plasma oxide (HighDensityPlasma,
hDPoxide).
Then, shown in Figure 1A to Fig. 4 A, the active region 13 of substrate 10 is formed in tunneling dielectric layer 14 and the conductor layer 16 of first direction extension.Tunneling dielectric layer 14 is such as form tunneling dielectric materials layer and conductor material layer over the substrate 10 with the formation method of conductor layer 16, recycles micro-shadow and etch process by tunneling dielectric materials layer and conductor material pattern layers.Tunneling dielectric materials layer can be made up of single material layer.Single material layer is such as advanced low-k materials or high dielectric constant material.Advanced low-k materials be dielectric constant lower than 4 dielectric material, be such as silica or silicon oxynitride.High dielectric constant material be dielectric constant higher than 4 dielectric material, be such as HfAlO, HfO
2, Al
2o
3or Si
3n
4.Tunneling dielectric materials layer also can select double stacked structure or the multilayer lamination structure that can improve Injection Current according to energy gap engineering theory (Band-gapEngineering (BE) Theory).Double stacked structure example is the double stacked structure (representing with advanced low-k materials/high dielectric constant material) that forms of advanced low-k materials and high dielectric constant material in this way, such as, be silica/HfSiO, silica/HfO
2or silica/silicon nitride.Multilayer lamination structure is such as the multilayer lamination structure (representing with advanced low-k materials/high dielectric constant material/advanced low-k materials) that advanced low-k materials, high dielectric constant material and advanced low-k materials form, such as, be silicon oxide/silicon nitride/silicon oxide or silica/Al
2o
3/ silica.The formation method of tunneling dielectric materials layer be such as chemical vapour deposition technique, situ steam method of formation (
iSSG), low pressure free-radical oxidation method (LPRO) or furnace oxidation method etc. formed.Conductor material layer is such as doped polycrystalline silicon, un-doped polysilicon or its combination, and its formation method can utilize chemical vapour deposition technique to be formed.Admixture in doped polycrystalline silicon is such as boron.In one embodiment, the thickness of tunneling dielectric layer 14 is 80nm to 120nm; The thickness of conductor layer 16 is 40nm to 120nm.
Refer to shown in Figure 1B to Fig. 4 B, be formed in dielectric layer 18 and conductor layer 20 between grid that second direction extends over the substrate 10, and conductor layer 16 and tunneling dielectric layer 14 are patterned as conductor layer 16a and tunneling dielectric layer 14a respectively.Conductor layer 16a is such as floating grid; Conductor layer 20 is such as control gate or is called character line.Second direction is different from first direction.Second direction and first direction can be such as mutually vertical.Second direction can be Y-direction or X-direction.The present embodiment graphic in, second direction is such as X-direction.More particularly, form dielectric materials layer and conductor material layer between grid over the substrate 10, recycle micro-shadow and etch process by dielectric materials layer between grid and conductor material pattern layers, to form dielectric layer 18 and conductor layer 20 between grid.Between formation grid after dielectric layer 18 and conductor layer 20, proceed etch process, conductor layer 16 and tunneling dielectric layer 14 are patterned as conductor layer 16a and tunneling dielectric layer 14a respectively.In one embodiment, between grid, dielectric materials layer is such as by oxide layer/nitration case/oxide layer (Oxide-Nitride-Oxide, ONO) composite bed formed, this composite bed can be three layers or more layers, the present invention is not limited to this, and its formation method can be chemical vapour deposition technique or thermal oxidation method etc.The material of conductor material is such as doped polycrystalline silicon, un-doped polysilicon or its combination, and its formation method can utilize chemical vapour deposition technique.The thickness of conductor layer 20 is such as 10nm to 18nm.
Afterwards, in the active region 13 of conductor layer 20 both sides, multiple doped region 22 is formed.Doped region 22 by conductor layer 20 as implantation cover curtain, can be carried out ion implantation technology to be formed.In one embodiment, substrate 10 and well region 11 have the first conductivity type; Doped region 22 has the second conductivity type.In one embodiment, the first conductivity type is such as P type; Second conductivity type is such as N-type.In another embodiment, the first conductivity type is such as N-type; Second conductivity type is such as P type.In an exemplary embodiment, substrate 10 and well region 11 are for having boron admixture; The admixture that doped region 22 is implanted is such as phosphorus or arsenic, and the dosage of doping is such as 5 × 10
13/ cm
2to 2 × 10
14/ cm
2, the energy of implantation is such as 5KeV to 15KeV.In fig. ib, doped region 22 be included in doped region 22a in the first district 102, in the second district 104 doped region 22b and in the 3rd district 106 doped region 22c.
Refer to shown in Fig. 1 C to Fig. 4 C, form cover curtain layer 200 over the substrate 10.Cover curtain layer 200 has the first crossing opening 202 and the second opening 204.First opening 202 extends at first direction, the isolation structure 12 exposing two doped region 22c adjacent in two row doped region 22b adjacent in two row doped region 22a adjacent in the first district 102, the second district 104, the 3rd district 106, multiple conductor layer (control gate) 20 and enclose.Second opening 204 extends in described second direction, exposes the multiple adjacent doped region 22c and its isolation structure 12 enclosed that are arranged in the 3rd district 106.In one embodiment, the second opening 204 can extend the conductor layer (control gate) 20 exposing part again.The formation method of cover curtain layer 200 is such as form photoresist layer over the substrate 10, and then by lithography process by photoresist layer patterning.
Afterwards, shown in Fig. 1 C to Fig. 4 C, with cover curtain layer 200 as etch mask, carry out anisotropic etching (being such as plasma etching) technique, remove the isolation structure 12 that the first opening 202 is exposed, to form multiple irrigation canals and ditches 206 of aligning voluntarily in substrate 10, expose well region 11.And remove the isolation structure 12 that the second opening 204 is exposed simultaneously, to form multiple irrigation canals and ditches 208 of aligning voluntarily in substrate 10, expose the well region 11 of substrate 10.In one embodiment, the described irrigation canals and ditches 206 of aligning voluntarily, extend at first direction and are in line; The described irrigation canals and ditches of aligning voluntarily 208, extend in second direction and form a line.
Thereafter, shown in Fig. 1 D to Fig. 4 D, with cover curtain layer 200 for implanting cover curtain, carry out ion implantation technology 210, to form the doping region in embedding type 212 and doping region in embedding type 214 that are electrically connected to each other.Ion implantation technology 210 is such as inclination angle ion implantation technology.The angle theta of the implanted ions direction of inclination angle ion implantation technology and the normal of substrate 10 is such as 0 degree to 35 degree.The implant dosage of ion implantation technology 210 is such as 5 × 10
13/ cm
2to 3 × 10
14/ cm
2.The implantation energy of ion implantation technology 210 is such as 10K to 35KeV.Admixture can be implanted to by inclination angle ion implantation technology in the well region 11 aimed at voluntarily bottom irrigation canals and ditches 206 but also side direction is implanted in the well region 11 aiming at irrigation canals and ditches 206 sidewall voluntarily, make formed doping region in embedding type 212 be not only arranged in the first opening 202 exposed aim at well region 11 bottom irrigation canals and ditches 206 voluntarily but also the well region 11 be implanted to below control gate 20, to extend continuously at first direction and the doped region 22a exposed with the first opening 202, doped region 22b and doped region 22c are electrically connected.Similarly, the well region 11 that doping region in embedding type 214 is arranged in the well region 11 below the exposed doped region 22c of the second opening 204 and aims at voluntarily below irrigation canals and ditches 208, extends continuously in second direction, and is electrically connected with doped region 22c.
Thereafter, refer to shown in Fig. 1 E to Fig. 4 E, remove cover curtain layer 200.The method removing cover curtain layer 200 can adopt that wet type divests method, dry type divests method or its combination.Afterwards, two source contacts 216a, 216b, multiple drain contact window 218, two source contacts 220a, 220b and multiple drain contact windows 222 are formed over the substrate 10.More particularly, source contacts 216a, 216b and drain contact window 218 are arranged in the first district 102.Source contacts 216a, 216b are positioned on two doped region 22a near doping region in embedding type 214, and are electrically connected with doping region in embedding type 212.Drain contact window 218 is positioned on other the doped region 22a near doping region in embedding type 214, and is not electrically connected with doping region in embedding type 212.Source contacts 220a, 220b and drain contact window 222 are arranged in the second district 104.Source contacts 220a, 220b are positioned on two doped region 22b near described doping region in embedding type 214, and are electrically connected with doping region in embedding type 212.Drain contact window 222 is positioned on the doped region 22b near described doping region in embedding type 214, and is not electrically connected with doping region in embedding type 212.Because doping region in embedding type 212 is electrically connected with source contacts 216a, 216b and source contacts 220a, 220b respectively, be therefore also called source electrode line (SourceRail).
Refer to shown in Fig. 1 E to Fig. 4 E, memory cell comprise dielectric layer 18 between substrate 10, well region 11, multiple tunneling dielectric layer 14a, multiple conductor layer (floating grid) 16a, multiple grid, multiple conductor layer (control gate) 20, doping region in embedding type 212,214, doped region 22a, 22b, 22c, two source contacts 216a, 216b, two source contacts 220a, 220b, multiple drain contact window 218 and multiple drain contact windows 222.
Substrate 10 comprises the first district 104 of district 102, second and the 3rd district 106.3rd district 106 is between the first district 102 and the second district 104.And substrate 10 have multiple voluntarily aim at irrigation canals and ditches 206 aim at irrigation canals and ditches 208 voluntarily with multiple.Described irrigation canals and ditches 206 of aiming at voluntarily extend in a line at first direction, extend to the 3rd district 106 from the first district 102.More particularly, described irrigation canals and ditches 206 of aiming at voluntarily are between two adjacent doped region 22a, between two adjacent doped region 22b and between two adjacent doped region 22c.Described irrigation canals and ditches 208 of aiming at voluntarily extend in row in second direction.
Described conductor layer (control gate) 20 extends in second direction, above the substrate 10 being positioned at the both sides of doping region in embedding type 214, and strides across described doping region in embedding type 212.Each conductor layer (floating grid) 16a is positioned between corresponding conductor layer (control gate) 20 and substrate 10.Each tunneling dielectric layer 14a is positioned between corresponding conductor layer (floating grid) 16a and substrate 10.Between each grid, dielectric layer 18 is positioned between corresponding conductor layer (floating grid) 16a and corresponding conductor layer (control gate) 20.
Described doped region 22a is arranged in the well region 11 of the first both sides, district 102 conductor layer (control gate) 20.Described doped region 22b is arranged in the well region 11 of the second both sides, district 104 conductor layer (control gate) 20.Described doped region 22c is arranged in the well region 11 in the 3rd district 106.
Described doping region in embedding type 212 extends at first direction, be arranged in the first district 104 of district 102, second and the 3rd district 106, what formed after removing isolation structure 12 aims in the bottom of irrigation canals and ditches 206 and the well region 11 of lateral wall circumference voluntarily, itself and two source contacts 216a, 216b and two source contacts 220a, 220b are electrically connected, and are therefore also called source electrode line.Doping region in embedding type 214 extends in second direction, be arranged in the 3rd district 106, aiming in the bottom of irrigation canals and ditches 208 and the well region 11 of lateral wall circumference voluntarily of removing that isolation structure 12 formed, and described doping region in embedding type 212 and described doping region in embedding type 214 are electrically connected.Described first direction is different from described second direction.In the present embodiment, described doping region in embedding type 212, through the below of conductor layer (control gate) 20, is electrically connected two adjacent row doped region 22a, adjacent two doped region 22c and two adjacent row doped region 22b.Described doping region in embedding type 214 is electrically connected the doped region 22c of row.The memory cell had a common boundary in doping region in embedding type 212 and doping region in embedding type 214 can be described as again compound and runs through memory cell (CompositePunchCell), the memory cell that namely in figure, region A encloses.
Described drain contact window 218, in the first district 102, is positioned on the multiple doped region 22a near a part for doping region in embedding type 214, and is not electrically connected with doping region in embedding type 212.Described source contacts 222, in the second district 104, is positioned on the multiple doped region 22b near a part for described doping region in embedding type 214, and is not electrically connected with doping region in embedding type 212.
In the present embodiment, two source contacts 216a, the 216b in the first district 102 and described drain contact window 218 are in the same side; Two source contacts 220a, the 220b in the second district 104 and described drain contact window 222 are also in the same side.More particularly, described two source contacts 216a, 216b, in the first district 102, are positioned at and are electrically connected with doping region in embedding type 212 and near on two doped region 22a of doping region in embedding type 214, and between multiple drain contact window 218.Described two source contacts 220a, 220b, in the second district 104, are positioned at and are electrically connected with doping region in embedding type 212 and near on two doped region 22b of described doping region in embedding type 214, and between multiple drain contact window 222.When voltage Vg1 is applied to character line W2, and voltage Vs1 is applied to the source electrode (via source contacts 216a, 216b, 220a, 220b) in the first district 102 and the second district 104 and voltage Vd1 when being applied to drain electrode (via the drain contact window 222a) in the second district 104, doping region in embedding type 212 and doping region in embedding type 214 as a part of current path P1, can make electric current run through one of memory cell by compound and flow to one of target memory born of the same parents (targetcell).Similarly, when voltage Vg1 is applied to character line W1, and voltage Vs2 is applied to source electrode (via source contacts 216a, 216b, 220a, 220b) and voltage Vd2 when being applied to drain electrode (via the drain contact window 218a) in the first district 102, doping region in embedding type 212 and doping region in embedding type 214 can as parts of current path P2, and another making electric current run through memory cell by compound flows to another target memory born of the same parents.
Referring to shown in Fig. 1 C to 1E, in the first above embodiment, is as forming the etch mask of multiple aligning irrigation canals and ditches 206 voluntarily and multiple irrigation canals and ditches 208 of aligning voluntarily and forming the implantation cover curtain of doping region in embedding type 212,214 with cover curtain layer 200.First opening 202 of cover curtain layer 200 exposes two adjacent row doped region 22a, adjacent two doped region 22c, adjacent two row doped region 22b, multiple segment conductor layer (control gate) 20 and an isolation structure 12.Therefore, the width of the first opening 202 of cover curtain layer 200 is substantially equal to the width summation of an isolation structure 12 and complete two adjacent doped region 22a.But the first opening of cover curtain layer of the present invention and the width of the second opening are not limited with above-mentioned, can according to reality need adjustment.In addition, two source contacts 216a, 216b and two source contacts 220a, 220b are that correspondence is arranged on two doped region 22a and two doped region 22b respectively.But the position of source contacts of the present invention or quantity are not also limited with above-mentioned, can according to reality need adjustment.
Fig. 5 is the vertical view of the manufacture method of the memory cell that foundation second embodiment of the invention illustrates.
Referring to shown in Fig. 5, in the second embodiment of the present invention, is as forming the etch mask of multiple aligning irrigation canals and ditches 506 voluntarily and multiple irrigation canals and ditches 508 of aligning voluntarily and forming the implantation cover curtain of doping region in embedding type 512 and 514 with cover curtain layer 500.First opening 502 of cover curtain layer 500 exposes two adjacent row doped region 22a of part, the two row doped region 22b that part is adjacent, two doped region 22c, multiple segment conductor layer (control gate) 20 and isolation structures 12.Therefore, the width of the first opening 502 of cover curtain layer 500 is substantially equal to the summation of the partial width of an isolation structure 12 and two adjacent doped region 22a; The width of the second opening 504 is then roughly the same with the width of the second opening 204 (Fig. 1 C) of the first embodiment.Therefore, the width of the doping region in embedding type 512 formed is less than the width of the doping region in embedding type 212 (Fig. 1 D) of the first embodiment; And the width of doping region in embedding type 514 is roughly the same with the width of the doping region in embedding type 214 of the first embodiment.In addition, the position of two source contacts 516a, 516b and two source contacts 520a, 520b is still separately positioned on two the adjacent doped region 22a near doping region in embedding type 214 and two the adjacent doped region 22b near doping region in embedding type 214, and is electrically connected with doping region in embedding type 512.
Fig. 6 is the vertical view of the manufacture method of the memory cell that foundation third embodiment of the invention illustrates.
Referring to shown in figure, in the third embodiment of the present invention, is aim at the etch mask of irrigation canals and ditches 608 voluntarily and form the implantation cover curtain of doping region in embedding type 612 and 614 as the multiple irrigation canals and ditches 606 of aiming at voluntarily of formation with multiple with cover curtain layer 600.The width of the first opening 602 of cover curtain layer 600 is roughly the same with the width of the first opening 202 (Fig. 1 C) of the first embodiment; The width of its second opening 604 is roughly the same with the width of the second opening 204 (Fig. 1 C) of the first embodiment.Therefore, the width of the doping region in embedding type 612 formed is roughly the same with the width of the doping region in embedding type 212 (Fig. 1 D) of the first embodiment; And the width of doping region in embedding type 614 is roughly the same with the width of the doping region in embedding type 214 (Fig. 1 D) of the first embodiment.In addition, the irrigation canals and ditches of aligning voluntarily 606 between two the adjacent doped region 22a near doping region in embedding type 214 arrange single source contacts 616, and this source contacts 616 is electrically connected with doping region in embedding type 612; And irrigation canals and ditches of aligning voluntarily 606 between two the adjacent doped region 22b near doping region in embedding type 214 arrange single source contacts 620, and this source contacts 620 is electrically connected with doping region in embedding type 612.
Fig. 7 is the vertical view of the manufacture method of the memory cell that foundation fourth embodiment of the invention illustrates.Referring to shown in Fig. 7, in the fourth embodiment of the present invention, is as forming the etch mask of multiple irrigation canals and ditches 708 of aligning voluntarily and forming the implantation cover curtain of doping region in embedding type 712 and 714 with cover curtain layer 700.First opening 702 of cover curtain layer 700 exposes multiple doped region 22a of the single row extended at first direction, single doped region 22c, multiple doped region 22b of single row and multiple segment conductor layer (control gate) 20.Therefore, in the present embodiment, only can form multiple irrigation canals and ditches 708 of aligning voluntarily below corresponding second opening 704, and can't be formed below corresponding first opening 702 as the multiple of the first embodiment aim at irrigation canals and ditches 206 (Fig. 1 C) voluntarily.The width of the first opening 702 of cover curtain layer 700 is suitable with the width of single doped region 22a, and the width of the doping region in embedding type 712 formed is less than the width of the doping region in embedding type 212 (Fig. 1 D) of the first embodiment.The width of the second opening 704 of cover curtain layer 700 is then roughly the same with the width of the second opening 204 (Fig. 1 C) of the first embodiment.Therefore, the width of the doping region in embedding type 714 formed is roughly the same with the width of the doping region in embedding type 214 (Fig. 1 D) of the first embodiment.In addition, single source contacts 716 is being set near on the doped region 22a of doping region in embedding type 214, and source contacts 716 and doping region in embedding type 712 are electrically connected; And be provided with single source contacts 720 near on the doped region 22b of doping region in embedding type 214, and source contacts 720 and doping region in embedding type 712 are electrically connected.
Fig. 8 is the vertical view of the manufacture method of the memory cell that foundation fifth embodiment of the invention illustrates.Referring to shown in Fig. 8, in the fifth embodiment of the present invention, is as forming multiple aligning irrigation canals and ditches 806 voluntarily and forming the etch mask of multiple irrigation canals and ditches 808 of aligning voluntarily and form the implantation cover curtain of doping region in embedding type 812 and 814 with cover curtain layer 800.The described isolation structure 12 that first opening 802 of cover curtain layer 800 exposes the multirow that extends at first direction adjacent doped region 22a, multiple adjacent doped region 22c, doped region 22b that multirow is adjacent, multiple segment conductor layer (control gate) 20 and encloses.Therefore, in the present embodiment, corresponding first opening can form the multiple irrigation canals and ditches 806 of aligning being voluntarily arranged in multirow for 802 times.The summation of the width of described isolation structure that the width of the first opening 802 is substantially equal to multiple doped region 22a and encloses, the width of therefore formed doping region in embedding type 812 is greater than the width of the doping region in embedding type 212 (Fig. 1 D) of the first embodiment.The width of the second opening 804 of cover curtain layer 800 is then roughly the same with the width of the second opening 204 of the first embodiment.Therefore, the width of the doping region in embedding type 814 formed is roughly the same with the width of the doping region in embedding type 214 (Fig. 1 D) of the first embodiment.In addition, the position of multiple source contacts 816a, 816b, 816c and multiple source contacts 820a, 820b, 820c is separately positioned on the multiple doped region 22a near the doping region in embedding type 214 and multiple doped region 22b near doping region in embedding type 214, and is electrically connected with doping region in embedding type 812.
Comprehensive the above, the present invention can be formed in the substrate through control gate by ion implantation technology and be connected in series the low resistance doping region in embedding type of multiple doped region.This doping region in embedding type can be electrically connected with source contacts, as source electrode line.In addition, the doping region in embedding type of another low resistance can be formed between Liang Qu simultaneously.In addition, source contacts and the drain contact window in same district are arranged on the same side, and are arranged in row, reduce the asymmetric and light shield manufacture complexity of exposure figure.And the manufacturing process of doping region in embedding type does not need additionally to increase light shield, and can with existing process integration, and can to aim at voluntarily, there is great process margin and the uniformity.In addition, the layout of doping region in embedding type roughly linearly, can not make bending, does not therefore need to carry out complicated optical proximity effect correction, therefore significantly can reduce manufacturing cost.In addition, due to doping region in embedding type layout roughly linearly, do not need to do in bending, therefore can save chip area and reach more than 3%.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the method and technology contents that can utilize above-mentioned announcement are made a little change or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a manufacture method for memory cell, is characterized in that it comprises the following steps:
In a substrate, form multiple isolation structure, each isolation structure extends at a first direction;
Form multiple control gate over the substrate, each control gate extends in a second direction, and described first direction is different from described second direction;
Below each control gate, the described substrate between two isolation structures of arbitrary neighborhood sequentially forms a tunneling dielectric layer, dielectric layer between a floating grid and grid;
The both sides of the described control gate in one first district of described substrate form one first doped region respectively, the both sides of the described control gate in one second district of described substrate form one second doped region respectively and form multiple 3rd doped region in one the 3rd districts of described substrate, and wherein said 3rd district is positioned between the firstth district and the secondth district;
Form a cover curtain layer over the substrate, described cover curtain layer has one first crossing opening and one second opening, wherein:
Described first opening extends at described first direction, at least exposes described first doped region of part, described second doped region of part, described 3rd doped region of part and the described control gate of part, and
Described second opening extends in described second direction, exposes the described isolation structure in described 3rd district and described 3rd doped region;
Remove the described isolation structure that described second opening is exposed, aim at irrigation canals and ditches voluntarily to form multiple first in described substrate;
With described cover curtain layer for implanting cover curtain, carry out an ion implantation technology, to be formed:
One first doping region in embedding type, it extends at described first direction, be arranged in described first opening exposed and by the described substrate below described control gate, be electrically connected exposed described first doped region of described first opening, described second doped region and described 3rd doped region; And
One second doping region in embedding type, it extends in described second direction, the described substrate and described first be arranged in below exposed described 3rd doped region of described second opening aims at the described substrate of trench bottom and lateral wall circumference voluntarily, and being electrically connected described 3rd doped region, described first doping region in embedding type is electrically connected described second doping region in embedding type; And
Remove described cover curtain layer.
2. the manufacture method of memory cell according to claim 1, is characterized in that it also comprises:
Be electrically connected with described first doping region in embedding type and forming at least one first source contacts near on described first doped region of described second doping region in embedding type; And
Be electrically connected with described first doping region in embedding type and forming at least one second source contacts near on described second doped region of described second doping region in embedding type.
3. the manufacture method of memory cell according to claim 1, it is characterized in that wherein said first opening exposes at least two adjacent the first doped regions, at least two adjacent the second doped regions, at least two adjacent the 3rd doped regions, at least one isolation structure and the described control gate of part, and when carrying out formation described first and aiming at the step of irrigation canals and ditches voluntarily, also comprise and remove the exposed described isolation structure of described first opening, irrigation canals and ditches are aimed at voluntarily to form multiple second, and described first doping region in embedding type also extends to described second aims at voluntarily in the described substrate of trench bottom and lateral wall circumference.
4. the manufacture method of memory cell according to claim 3, is characterized in that it also comprises:
In described firstth district, aiming at formation one first source contacts on irrigation canals and ditches voluntarily near described second of the second doping region in embedding type, be electrically connected with described first doping region in embedding type; And
In described secondth district, aiming at formation one second source contacts on irrigation canals and ditches voluntarily near described second of the second doping region in embedding type, be electrically connected with described first doping region in embedding type.
5. the manufacture method of memory cell according to claim 1, it is characterized in that wherein said ion implantation technology is an inclination angle ion implantation technology, the angle of the implanted ions direction of wherein said inclination angle ion implantation technology and the normal of described substrate is 0 degree to 35 degree.
6. a memory cell, is characterized in that it comprises:
One substrate, comprises one first district, one second district and one the 3rd district, and wherein said 3rd district to be positioned between described firstth district with described secondth district and to have multiple first aims at irrigation canals and ditches voluntarily;
One first doping region in embedding type, extends at a first direction, is arranged in the described substrate in described firstth district of part, described secondth district of part and described 3rd district of part;
One second doping region in embedding type, extend in a second direction, be arranged in the described substrate that described first aims at described 3rd district of trench bottom and lateral wall circumference voluntarily, and described first doping region in embedding type and described second doping region in embedding type are electrically connected, described first direction is different from described second direction;
Multiple control gate, extends in described second direction, is positioned at the described types of flexure of the both sides of described second doping region in embedding type, and strides across described first doping region in embedding type;
Multiple floating grid, each floating grid is between corresponding control gate and described substrate;
Multiple tunneling dielectric layer, each tunneling dielectric layer is between corresponding floating grid and described substrate;
Dielectric layer between multiple grid, between each grid, dielectric layer is between corresponding floating grid and corresponding control gate;
Multiple first doped region, is arranged in the described substrate of control gate both sides described in each, described firstth district;
Multiple second doped region, is arranged in the described substrate of control gate both sides described in each, described secondth district; And
Multiple 3rd doped region, is arranged in the described substrate in described 3rd district, wherein
Described first doping region in embedding type, through below described control gate, is electrically connected described first doped region of part, described second doped region of part and described 3rd doped region of part, and described second doping region in embedding type is electrically connected described 3rd doped region.
7. memory cell according to claim 6, is characterized in that it also comprises:
One first source contacts, in described firstth district, is positioned at and is electrically connected with described first doping region in embedding type and near on described first doped region of described second doping region in embedding type; And
One second source contacts, in described secondth district, is positioned at and is electrically connected with described first doping region in embedding type and near on described second doped region of described second doping region in embedding type.
8. memory cell according to claim 6, it is characterized in that wherein said first doping region in embedding type is electrically connected the first adjacent doped region of at least two row, the second doped region that at least two row are adjacent and at least two adjacent the 3rd doped regions, and also extend to multiple second in described substrate and aim at voluntarily in the described substrate of trench bottom and lateral wall circumference, wherein said second aims at irrigation canals and ditches voluntarily extends in a line at described first direction, between the first doped region that described in being electrically connected in described first doping region in embedding type, at least two row are adjacent, between the second doped region that described at least two row are adjacent and between at least two adjacent the 3rd doped regions.
9. memory cell according to claim 8, is characterized in that it also comprises:
One first source contacts, is arranged in described firstth district and aims on irrigation canals and ditches voluntarily near described second of described second doping region in embedding type, be electrically connected with described first doping region in embedding type; And
One second source contacts, is arranged in described secondth district and aims on irrigation canals and ditches voluntarily near described second of described second doping region in embedding type, be electrically connected with described first doping region in embedding type.
10. memory cell according to claim 8, is characterized in that it also comprises:
At least two the first source contacts, in described firstth district, are positioned at and are electrically connected with described first doping region in embedding type and near at least two adjacent the first doped regions described in described second doping region in embedding type; And
At least two one second source contacts, in described secondth district, are positioned at and are electrically connected with described first doping region in embedding type and near at least two adjacent the second doped regions described in described second doping region in embedding type.
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