CN105097707B - Memory cell and its manufacture method - Google Patents
Memory cell and its manufacture method Download PDFInfo
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- CN105097707B CN105097707B CN201410211577.7A CN201410211577A CN105097707B CN 105097707 B CN105097707 B CN 105097707B CN 201410211577 A CN201410211577 A CN 201410211577A CN 105097707 B CN105097707 B CN 105097707B
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Abstract
The invention relates to a kind of memory cell and its manufacture method.The manufacture method of the memory cell, including ion implantation technology is carried out, to form the first doping region in embedding type and the second doping region in embedding type in the substrate as implantation mask with cover curtain layer.First doping region in embedding type extends in a first direction, passes through the control gate, the first doped region, the second doped region and the 3rd doped region of electric connection control gate both sides.Second doping region in embedding type extends in the second direction, in the substrate below the 3rd doped region, is electrically connected with the 3rd doped region, and the first doping region in embedding type is electrically connected with the second doping region in embedding type.
Description
Technical field
The present invention relates to a kind of semiconductor element and its manufacture method, more particularly to a kind of memory cell and its manufacturer
Method.
Background technology
Nonvolatile memory is due to the advantages of data with deposit will not also disappear after a loss of power, therefore much electrical equipment
Must possess such memory body in product, to maintain the normal operating of electric equipment products.Particularly, fast flash memory bank (Flash
Memory) due to being operated with deposit, reading, erasing that can repeatedly carry out data etc., so turning into PC and electronics
A kind of widely used memory cell of equipment.
With the increase of element integrated level, component size constantly reduces.However, fast flash memory bank be not each component can
With lasting diminution, and it must be maintained at certain size.For example, when manufacturing fast flash memory bank, it will usually by source electrode line with
And the size for being sized so as to relatively larger than bit line and drain contact window of source contacts, to reduce sheet resistance.However, adopt
With such a method, the layout of word-line is considerably complicated, and word-line is necessarily designed to bending when passing through source electrode line, need to consider multiple
Miscellaneous optical proximity effect amendment problem, therefore, the expense of its light shield is at a relatively high.In addition, its process margin is also very small, easily
The problems such as causing the uniformity bad.
As can be seen here, above-mentioned existing memory cell and its manufacture method are upper with using in product structure, manufacture method, show
Inconvenience and defect have so been still suffered from, and has urgently been further improved.In order to solve above-mentioned problem, relevant manufactures are there's no one who doesn't or isn't
Painstakingly seek solution, but have no that applicable design is developed completing always for a long time, and common product and side
Method can solve the problem that above mentioned problem without appropriate structure and method again, and this is clearly the problem of related dealer is suddenly to be solved.Therefore
How a kind of new memory cell and its manufacture method, real category current important research and development problem one of are founded, also as current industry
Boundary pole needs improved target.
The content of the invention
It is an object of the present invention to the defects of overcoming existing memory cell and its manufacture method to exist, and provide a kind of
New memory cell and its manufacture method, technical problem to be solved are it is reduced source electrode line and source contacts
Sheet resistance, be very suitable for practicality.
Another object of the present invention is to, the defects of overcoming existing memory cell and its manufacture method to exist, and provide
A kind of new memory cell and its manufacture method, technical problem to be solved are its used light shield is entered
The excessively complicated optical proximity effect amendment of row, thus more suitable for practicality.
Another object of the present invention is, the defects of overcoming existing memory cell and its manufacture method to exist, and provides
A kind of new memory cell and its manufacture method, technical problem to be solved are to allow itself and existing process integration, from
And it is more suitable for practicality.
The object of the invention to solve the technical problems is realized using following technical scheme.Itd is proposed according to the present invention
A kind of memory cell manufacture method, including form multiple isolation structures in the substrate, each isolation structure is in a first direction
Extension.Multiple control gates are formed over the substrate, and each control gate extends in second direction, the first direction and institute
State second direction difference.Below each control gate, on the substrate between two isolation structures of arbitrary neighborhood sequentially
Dielectric layer between formation tunneling dielectric layer, floating grid and grid.The both sides of the control gate in the firstth area of the substrate
The first doped region is formed respectively, and the both sides of the control gate in the secondth area of the substrate form the second doped region respectively
And form multiple 3rd doped regions in the 3rd area of the substrate, wherein the 3rd area be located at the firstth area and the secondth area it
Between.Cover curtain layer is formed over the substrate, and the cover curtain layer has the first intersecting opening and the second opening.First opening
Extend in the first direction, at least expose part first doped region, part second doped region, part described the
Three doped regions and the part control gate, and second opening extends in the second direction, exposes the described 3rd
The isolation structure in area and the 3rd doped region.The exposed isolation structure of second opening is removed, with described
Multiple first are formed in substrate and is voluntarily directed at irrigation canals and ditches.Using the cover curtain layer as implantation mask, ion implantation technology is carried out, to be formed
First doping region in embedding type and the second doping region in embedding type.First doping region in embedding type extends in the first direction, positioned at institute
It is exposed and exposed by the substrate below the control gate, being electrically connected with first opening to state the first opening
First doped region, second doped region and the 3rd doped region.Second doping region in embedding type is in the second party
To extension, in the substrate below the 3rd doped region exposed positioned at the described second opening and described first is voluntarily right
In the substrate of quasi- trench bottom and lateral wall circumference, and the 3rd doped region is electrically connected with, the first flush type doping
Area is electrically connected with second doping region in embedding type.Remove the cover curtain layer.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
The manufacture method of foregoing memory cell, it is additionally included in and is electrically connected with first doping region in embedding type and most leans on
At least one first source contacts are formed on first doped region of nearly second doping region in embedding type.With described first
Doping region in embedding type is electrically connected with and forms at least one on second doped region of second doping region in embedding type
Second source contacts.
The manufacture method of foregoing memory cell, wherein first opening exposes at least two the first adjacent doping
Area, at least two the second adjacent doped regions, at least two the 3rd adjacent doped regions, at least an isolation structure and part institute
Control gate is stated, and when to be formed the described first voluntarily step of alignment irrigation canals and ditches, in addition to removal first opening is naked
The isolation structure of dew, is voluntarily directed at irrigation canals and ditches, and first doping region in embedding type also extends into institute to form multiple second
Second is stated voluntarily to be aligned in the substrate of trench bottom and lateral wall circumference.
The manufacture method of foregoing memory cell, in addition to：In firstth area, adulterated near the second flush type
Described the second of area is voluntarily directed at one first source contacts of formation on irrigation canals and ditches, electrically connects with first doping region in embedding type
Connect；And in secondth area, one is formed being voluntarily aligned on irrigation canals and ditches near described the second of the second doping region in embedding type
Second source contacts, it is electrically connected with first doping region in embedding type.
The manufacture method of foregoing memory cell, wherein the ion implantation technology is inclination angle ion implantation technology, its
Described in the angle of the normal that direction and the substrate is ion implanted of inclination angle ion implantation technology be 0 degree to 35 degree.
The object of the invention to solve the technical problems is also realized using following technical scheme.According to proposed by the present invention
A kind of memory cell, including substrate, including one first area, one second area and one the 3rd area, wherein the 3rd area is positioned at described
Between firstth area and secondth area.Have multiple first to be voluntarily directed at irrigation canals and ditches in substrate.First doping region in embedding type, one
One direction extends, in the substrate of part firstth area, part secondth area with part the 3rd area.Second
Doping region in embedding type, extend in a second direction, described the of trench bottom and lateral wall circumference is voluntarily directed at positioned at described first
In the substrate in 3rd area, and first doping region in embedding type and second doping region in embedding type are electrically connected with, and described the
One direction is different from the second direction.Multiple control gates, extend in the second direction, mixed positioned at second flush type
Above the substrates of the both sides in miscellaneous area, and across first doping region in embedding type.Memory cell also includes multiple floating grids
Dielectric layer between pole, multiple tunneling dielectric layers and multiple grid.Each floating grid is located at corresponding control gate and the lining
Between bottom.Each tunneling dielectric layer is between corresponding floating grid and the substrate.Dielectric layer is located at institute between each grid
Between corresponding floating grid and corresponding control gate.Multiple first doped regions, it is each described in firstth area
In the substrate of control gate both sides.Multiple second doped regions, each control gate both sides in secondth area
The substrate in.Multiple 3rd doped regions, in the substrate in the 3rd area.Wear first doping region in embedding type
Cross below the control gate, be electrically connected with described in part first doped region, part second doped region and part
3rd doped region, and second doping region in embedding type is electrically connected with the 3rd doped region.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
Foregoing memory cell, in addition to：First source contacts, in firstth area, buried positioned at described first
Enter formula doped region to be electrically connected with and on first doped region of second doping region in embedding type；And second source electrode
Contact hole, in secondth area, positioned at first doping region in embedding type electric connection and near the described second embedment
On second doped region of formula doped region.
Foregoing memory cell, wherein first doping region in embedding type is electrically connected with the first adjacent doping of at least two rows
The second adjacent doped region of area, at least two rows and at least two the 3rd adjacent doped regions, and more extend in the substrate
More several second be voluntarily aligned in the substrate of trench bottom and lateral wall circumference, wherein described second voluntarily alignment irrigation canals and ditches exist
The first direction extension is in a line, positioned at adjacent with least two rows described in the electric connection of first doping region in embedding type
Between first doped region, between the second doped region that at least two rows are adjacent and at least two the 3rd adjacent doped regions it
Between.
Foregoing memory cell, in addition to：First source contacts, buried in firstth area near described second
Enter formula doped region described second is voluntarily aligned on irrigation canals and ditches, is electrically connected with first doping region in embedding type；And second source
Pole contact hole, described second near second doping region in embedding type in secondth area is voluntarily aligned on irrigation canals and ditches,
It is electrically connected with first doping region in embedding type.
Foregoing memory cell, in addition to：At least two first source contacts, in firstth area, positioned at institute
The first doping region in embedding type is stated to be electrically connected with and near described at least two adjacent the of second doping region in embedding type
On one doped region；And at least two one the second source contacts, in secondth area, mixed positioned at first flush type
Miscellaneous area is electrically connected with and on described at least two the second adjacent doped region of second doping region in embedding type.
The present invention has clear advantage and beneficial effect compared with prior art.By above-mentioned technical proposal, the present invention
Memory cell and its manufacture method at least have following advantages and beneficial effect：
First, memory cell of the invention and its manufacture method, the sheet resistance of source electrode line and source contacts can be reduced.
2nd, memory cell of the invention and its manufacture method, used light shield need not can carry out excessively complicated
Optical proximity effect amendment.
3rd, memory cell of the invention and its manufacture method, can be with existing process integration.
In summary, the invention relates to a kind of memory cell and its manufacture method.The manufacture method of the memory cell,
Including, as implantation mask, ion implantation technology being carried out, to form the first doping region in embedding type and the in the substrate with cover curtain layer
Two doping region in embedding type.First doping region in embedding type extends in a first direction, by the control gate, is electrically connected with control gate
The first doped region, the second doped region and the 3rd doped region of pole both sides.Prolong in the second direction the second doping region in embedding type
Stretch, in the substrate below the 3rd doped region, be electrically connected with the 3rd doped region, and the first doping region in embedding type is electrically connected with the
Two doping region in embedding type.The present invention technically has significant progress, and has obvious good effect, is really a novelty, enters
Step, practical new design.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow the above and other objects, features and advantages of the present invention can
Become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.
Brief description of the drawings
Figure 1A to Fig. 1 E is the vertical view of the flow of the manufacture method of the memory cell illustrated according to first embodiment of the invention
Figure.
Fig. 2A to Fig. 2 E is the diagrammatic cross-section for illustrating Figure 1A to Fig. 1 E tangentially II-II.
Fig. 3 A to Fig. 3 E are the diagrammatic cross-sections for illustrating Figure 1A to Fig. 1 E tangentially III-III.
Fig. 4 A to Fig. 4 E are to illustrate Figure 1A to Fig. 1 E tangentially IV-IV diagrammatic cross-sections.
Fig. 5 is the top view of the manufacture method of the memory cell illustrated according to second embodiment of the invention.
Fig. 6 is the top view of the manufacture method of the memory cell illustrated according to third embodiment of the invention.
Fig. 7 is the top view of the manufacture method of the memory cell illustrated according to fourth embodiment of the invention.
Fig. 8 is the top view of the manufacture method of the memory cell illustrated according to fifth embodiment of the invention.
10：Substrate
11：Well region
12：Isolation structure
13：Active region
14、14a：Tunneling dielectric layer
16、16a、20：Conductor layer
18：Dielectric layer between grid
22、22a、22b、22c：Doped region
102：Firstth area
104：Secondth area
106：3rd area
200、500、600、700、800：Cover curtain layer
202、502、602、702、802：First opening
204、504、604、704、804：Second opening
206、208、506、508、606、608、708、806、808：Voluntarily it is directed at irrigation canals and ditches
210：Ion implantation technology
212、214、512、514、612、614、712、714、812、814：Doping region in embedding type
216a、216b、220a、220b、516a、516b、520a、520b、616、620、716、72、816a、816b、
816c、820a、820b、820c：Source contacts
218、218a、222、222a：Drain contact window
A：Region
P1、P2：Path
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to according to memory cell proposed by the present invention and its manufacture method its embodiment, structure, side
Method, step, feature and its effect, describe in detail as after.
For the present invention foregoing and other technology contents, feature and effect, in the following preferable reality coordinated with reference to schema
Applying in the detailed description of example to clearly appear from.By the explanation of embodiment, the present invention can should be reached predetermined
The technological means and effect that purpose is taken obtain one and more go deep into and specifically understand, but institute's accompanying drawings are only to provide reference
With the use of explanation, not it is used for being any limitation as the present invention.
Figure 1A to Fig. 1 E is the vertical view of the flow of the manufacture method of the memory cell illustrated according to first embodiment of the invention
Figure.Fig. 2A to Fig. 2 E is to illustrate the diagrammatic cross-section along Figure 1A to Fig. 1 E tangent lines II-II.Fig. 3 A to Fig. 3 E are to illustrate along Figure 1A extremely
Fig. 1 E tangent lines III-III diagrammatic cross-section.Fig. 4 A to Fig. 4 E are illustrated along Figure 1A to Fig. 1 E tangent line IV-IV diagrammatic cross-sections.
Refer to shown in Figure 1A, there is provided substrate 10.Substrate 10 includes the first area 102, the second area 104 and the 3rd area 106.The
Three areas 106 are between the first area 102 and the second area 104.Substrate 10 be, for example, Semiconductor substrate, semiconducting compound substrate or
It is to have Semiconductor substrate (Semiconductor Over Insulator, SOI) on insulating barrier.Semiconductor is, for example, IVA races
Atom, such as silicon or germanium.Semiconducting compound substrate is, for example, the semiconducting compound that the atom of IVA races is formed, and is, for example,
Carborundum or germanium silicide, or the semiconducting compound (being, for example, GaAs) that Group IIIA atom is formed with VA races atom.
Well region 11 can be formed in substrate 10.Well region 11 has the admixture of the first conductivity type.In one embodiment, first conductivity type is mixed
Matter is, for example, p-type admixture.In another embodiment, the first conductivity type admixture is, for example, N-type admixture.P-type admixture such as boron.N-type
Admixture is e.g. phosphorus or arsenic.
The more isolation structures 12 extended in a first direction are formed in the well region 11 of substrate 10, to define multiple active regions
13.First direction can be X-direction or Y-direction.In the schema of the present embodiment, first direction is, for example, Y-direction.Isolation structure
12 forming method can be shallow trench isolation method (STI) or deep trenches isolation method (DTI).The material of isolation structure 12 is insulation
Material, e.g. silica.Oxide be, for example, spin-on glasses (Spin-On Glass,SOG) or high-density plasma oxygen
Compound (High Density Plasma,HDP oxide)。
Then, please continue to refer to shown in Figure 1A to Fig. 4 A, formed on the active region 13 of substrate 10 and extended in a first direction
Tunneling dielectric layer 14 and conductor layer 16.Tunneling dielectric layer 14 and the forming method of conductor layer 16 are e.g. formed over the substrate 10
Tunneling dielectric materials layer and conductor material layer, lithographic and etch process are recycled by tunneling dielectric materials layer and conductor material layer figure
Case.Tunneling dielectric materials layer can be made up of single material layer.Single material layer is, for example, advanced low-k materials or high dielectric
Constant material.Advanced low-k materials are the dielectric material that dielectric constant is less than 4, e.g. silica or silicon oxynitride.Gao Jie
Permittivity material is the dielectric material that dielectric constant is higher than 4, e.g. HfAlO, HfO2、Al2O3Or Si3N4.Tunneling dielectric material
Layer can also select that Injection Current can be improved according to energy gap engineering theory (Band-gap Engineering (BE) Theory)
Double stacked structure or multilayer lamination structure.Double stacked structure is, for example, advanced low-k materials and high-k material
The formed double stacked structure (being represented with advanced low-k materials/high dielectric constant material) of material, e.g. silica/
HfSiO, silica/HfO2Or silica/silicon nitride.Multilayer lamination structure is, for example, that advanced low-k materials, high dielectric are normal
Number materials and advanced low-k materials formed multilayer lamination structure (with advanced low-k materials/high dielectric constant material/
Advanced low-k materials represent), e.g. silicon oxide/silicon nitride/silicon oxide or silica/Al2O3/ silica.Tunneling dielectric
The forming method of material layer be, for example, chemical vapour deposition technique, situ steam method of formation (ISSG), low pressure free-radical oxidation method
(LPRO) or furnace oxidation method etc. is formed.Conductor material layer be, for example, DOPOS doped polycrystalline silicon, un-doped polysilicon or its combination, its
Forming method can be formed using chemical vapour deposition technique.Admixture in DOPOS doped polycrystalline silicon is, for example, boron.In one embodiment,
The thickness of tunneling dielectric layer 14 is 80nm to 120nm；The thickness of conductor layer 16 is 40nm to 120nm.
Refer to shown in Figure 1B to Fig. 4 B, form dielectric layer 18 and conductor between the grid of second direction extension over the substrate 10
Layer 20, and conductor layer 16 and tunneling dielectric layer 14 are distinguished into patterned conductor layer 16a and tunneling dielectric layer 14a.Conductor layer 16a
E.g. as floating grid；Conductor layer 20 is, for example, as control gate or is word-line.Second direction and first direction
It is different.Second direction may, for example, be with first direction and be mutually perpendicular to.Second direction can be Y-direction or X-direction.In this implementation
In the schema of example, second direction is, for example, X-direction.More specifically, over the substrate 10 formed grid between dielectric materials layer and conductor
Material layer, lithographic and etch process is recycled to pattern dielectric materials layer between grid and conductor material layer, to form dielectric between grid
Layer 18 and conductor layer 20.After dielectric layer 18 between forming grid and conductor layer 20, continue etch process, by conductor layer 16 with
Tunneling dielectric layer 14 distinguishes patterned conductor layer 16a and tunneling dielectric layer 14a.In one embodiment, dielectric materials layer between grid
The composite bed being e.g. made up of oxide layer/nitration case/oxide layer (Oxide-Nitride-Oxide, ONO), this composite bed
Can be three layers or more layers, the present invention is not limited thereto, and its forming method can be chemical vapour deposition technique or thermal oxidation method etc..
The material of conductor material is, for example, that DOPOS doped polycrystalline silicon, un-doped polysilicon or its combination, its forming method can utilize chemical gas
Phase sedimentation.The thickness of conductor layer 20 is, for example, 10nm to 18nm.
Afterwards, multiple doped regions 22 are formed in the active region 13 of the both sides of conductor layer 20.Doped region 22 can be by conductor
Layer 20 carries out ion implantation technology to be formed as implantation mask.In one embodiment, substrate 10 has first to lead with well region 11
Electric type；Doped region 22 has the second conductivity type.In one embodiment, the first conductivity type is, for example, p-type；Second conductivity type is, for example,
N-type.In another embodiment, the first conductivity type is, for example, N-type；Second conductivity type is, for example, p-type.In an one exemplary embodiment
In, substrate 10 is with boron admixture with well region 11；The admixture that doped region 22 is implanted into is, for example, phosphorus or arsenic, and the dosage of doping is for example
It is 5 × 1013/cm2To 2 × 1014/cm2, the energy of implantation is, for example, 5KeV to 15KeV.In fig. ib, doped region 22 is included in
Doped region 22a, the doped region 22b and doped region 22c in the 3rd area 106 in the second area 104 in first area 102.
Refer to shown in Fig. 1 C to Fig. 4 C, form cover curtain layer 200 over the substrate 10.Cover curtain layer 200 has intersecting first
The opening 204 of opening 202 and second.First opening 202 extends in a first direction, exposes two rows adjacent in the first area 102 and mixes
Two doped region 22c adjacent in two adjacent row doped region 22b, the 3rd area 106 in miscellaneous area 22a, the second area 104, multiple lead
Body layer (control gate) 20 and its isolation structure 12 enclosed.Second opening 204 extends in the second direction, exposes and is located at
The isolation structure 12 that multiple adjacent doped region 22c in 3rd area 106 are enclosed with it.In one embodiment, the second opening 204
The conductor layer (control gate) 20 for exposing part can be re-extended.The forming method of cover curtain layer 200 is, for example, over the substrate 10
Photoresist layer is formed, then again by lithography process by photoresistance pattern layers.
Afterwards, please continue to refer to shown in Fig. 1 C to Fig. 4 C, with cover curtain layer 200 as etch mask, anisotropic erosion is carried out
(being, for example, plasma etching) technique is carved, removes the first 202 exposed isolation structures 12 of opening, it is more to be formed in substrate 10
It is individual to be voluntarily directed at irrigation canals and ditches 206, expose well region 11.While the second 204 exposed isolation structures 12 of opening are removed, to serve as a contrast
Multiple well regions 11 for being voluntarily directed at irrigation canals and ditches 208, exposing substrate 10 are formed in bottom 10.In one embodiment, it is described to be voluntarily aligned
Irrigation canals and ditches 206, extend and are in line in a first direction；Described voluntarily alignment irrigation canals and ditches 208, extend in second direction and line up one
Row.
Thereafter, please continue to refer to shown in Fig. 1 D to Fig. 4 D, it is implantation mask with cover curtain layer 200, carries out ion implantation technology
210, to form the doping region in embedding type 212 being electrically connected to each other and doping region in embedding type 214.Ion implantation technology 210 is for example
It is inclination angle ion implantation technology.Direction and the angle theta example of the normal of substrate 10 is ion implanted in inclination angle ion implantation technology
Such as it is 0 degree to 35 degree.The implant dosage of ion implantation technology 210 is, for example, 5 × 1013/cm2To 3 × 1014/cm2.It is ion implanted
The implantation energy of technique 210 is, for example, 10K to 35KeV.Admixture can be implanted to voluntarily by inclination angle ion implantation technology
It is implanted in the well region 11 of alignment irrigation canals and ditches 206 bottom but also laterally and is voluntarily aligned in the well region 11 of the side wall of irrigation canals and ditches 206 so that institute
The doping region in embedding type 212 of formation be not only located at the first opening 202 it is exposed be voluntarily aligned in the well region 11 of irrigation canals and ditches 206 bottoms and
And be also implanted in the well region 11 of the lower section of control gate 20, it is with continuous extension in a first direction and exposed with the institute of the first opening 202
Doped region 22a, doped region 22b and doped region 22c be electrically connected with.Similarly, doping region in embedding type 214 is positioned at the second opening
In well region 11 below 204 exposed doped region 22c and voluntarily it is aligned in the well region 11 of the lower section of irrigation canals and ditches 208, in second direction
Continuous extension, and be electrically connected with doped region 22c.
Thereafter, refer to shown in Fig. 1 E to Fig. 4 E, remove cover curtain layer 200.The method of removal cover curtain layer 200 can use wet
Formula divests method, dry type divests method or its combination.Afterwards, two source contacts 216a, 216b, multiple leakages are formed over the substrate 10
Pole contact hole 218, two source contacts 220a, 220b and multiple drain contact windows 222.More specifically, source contact
Window 216a, 216b and drain contact window 218 are located in the first area 102.Source contacts 216a, 216b are located most closely to flush type
On two doped region 22a of doped region 214, and it is electrically connected with doping region in embedding type 212.Drain contact window 218, which is located at, most to be leaned on
On other doped region 22a of nearly doping region in embedding type 214, and electrically it is not connected to doping region in embedding type 212.Source contacts
220a, 220b and drain contact window 222 are located in the second area 104.Source contacts 220a, 220b are located most closely to the embedment
On two doped region 22b of formula doped region 214, and it is electrically connected with doping region in embedding type 212.Drain contact window 222 is positioned at most
On the doped region 22b of the doping region in embedding type 214, and electrically it is not connected to doping region in embedding type 212.Due to flush type
Doped region 212 is electrically connected with source contacts 216a, 216b and source contacts 220a, 220b respectively, therefore also known as
Source electrode line (Source Rail).
Refer to shown in Fig. 1 E to Fig. 4 E, memory cell includes substrate 10, well region 11, multiple tunneling dielectric layer 14a, multiple
Dielectric layer 18 between conductor layer (floating grid) 16a, multiple grid, multiple conductor layers (control gate) 20, doping region in embedding type 212,
214th, doped region 22a, 22b, 22c, two source contacts 216a, 216b, two source contacts 220a, 220b, multiple leakages
Pole contact hole 218 and multiple drain contact windows 222.
Substrate 10 includes the first area 102, the second area 104 and the 3rd area 106.3rd area 106 is located at the first area 102 and second
Between area 104.And there are substrate 10 multiple voluntarily alignment irrigation canals and ditches 206 to be voluntarily directed at irrigation canals and ditches 208 with multiple.It is described to be voluntarily aligned
It is in a line that irrigation canals and ditches 206 extend in a first direction, and the 3rd area 106 is extended to from the first area 102.More specifically, it is described voluntarily right
Quasi- irrigation canals and ditches 206 are between two adjacent doped region 22a, between two adjacent doped region 22b and two adjacent are mixed
Between miscellaneous area 22c.It is described to be voluntarily directed at irrigation canals and ditches 208 in second direction extension in a row.
Described conductor layer (control gate) 20 extends in second direction, the lining positioned at the both sides of doping region in embedding type 214
The top of bottom 10, and across the doping region in embedding type 212.Each conductor layer (floating grid) 16a is located at corresponding conductor layer
Between (control gate) 20 and substrate 10.Each tunneling dielectric layer 14a is located at corresponding conductor layer (floating grid) 16a and lining
Between bottom 10.Dielectric layer 18 is located at corresponding conductor layer (floating grid) 16a and corresponding conductor layer (control between each grid
Grid) between 20.
The doped region 22a is located in the first area 102 in the well region 11 of the both sides of conductor layer (control gate) 20.The doping
Area 22b is located in the well region 11 of the secondth area 104 conductor layer (control gate) 20 both sides.The doped region 22c is located at the 3rd area 106
Well region 11 in.
The doping region in embedding type 212 extends in a first direction, positioned at the first area 102, the second area 104 and the 3rd area 106
In, formed after removing isolation structure 12 voluntarily be aligned irrigation canals and ditches 206 bottom and lateral wall circumference well region 11 in, its with
Two source contacts 216a, 216b and two source contacts 220a, 220b are electrically connected with, therefore also known as source electrode line.
Doping region in embedding type 214 extends in second direction, and in the 3rd area 106, it is voluntarily right to be formed in removal isolation structure 12
In the bottom of quasi- irrigation canals and ditches 208 and the well region 11 of lateral wall circumference, and the doping region in embedding type 212 and the doping region in embedding type
214 are electrically connected with.The first direction is different from the second direction.In the present embodiment, the doping region in embedding type 212 is worn
Cross the lower section of conductor layer (control gate) 20, be electrically connected with two adjacent row doped region 22a, adjacent two doped region 22c with
And two adjacent row doped region 22b.The doping region in embedding type 214 is electrically connected with the doped region 22c of a row.Adulterated in flush type
The memory cell that area 212 and doping region in embedding type 214 have a common boundary can be described as compound running through memory cell (Composite Punch again
Cell), i.e., the memory cell that region A is enclosed in figure.
The drain contact window 218 in the first area 102, be located most closely to doping region in embedding type 214 a part it is more
On individual doped region 22a, and electrically it is not connected to doping region in embedding type 212.The source contacts 222 are in the second area 104, position
In on multiple doped region 22b of the part near the doping region in embedding type 214, and it is electrical with doping region in embedding type 212
It is not connected to.
In the present embodiment, two source contacts 216a, the 216b in the first area 102 exist with the drain contact window 218
The same side；Two source contacts 220a, the 220b in the second area 104 are with the drain contact window 222 also in the same side.More specifically
Ground says, described two source contacts 216a, 216b in the first area 102, positioned at being electrically connected with doping region in embedding type 212 and
On two doped region 22a of doping region in embedding type 214, and between multiple drain contact windows 218.Described two sources
Pole contact hole 220a, 220b are in the second area 104, positioned at being electrically connected with doping region in embedding type 212 and near the embedment
On two doped region 22b of formula doped region 214, and between multiple drain contact windows 222.When voltage Vg1 is applied to character
Line W2, and by voltage Vs1 be applied to the first area 102 and the second area 104 source electrode (via source contacts 216a, 216b,
220a, 220b) and voltage Vd1 when being applied to drain electrode (via the drain contact window 222a) in the second area 104, doping region in embedding type
212 and doping region in embedding type 214 as a current path P1 part electric current can be made to be flowed to by compound through one of memory cell
One of target memory born of the same parents (target cell).Similarly, when voltage Vg1 is applied to word-line W1, and voltage Vs2 is applied
Drain electrode (the warp in the first area 102 is applied to source electrode (via source contacts 216a, 216b, 220a, 220b) and voltage Vd2
By drain contact window 218a) when, doping region in embedding type 212 and doping region in embedding type 214 can as a current path P2 part,
Electric current is set to flow to another target memory born of the same parents by compound another through memory cell.
Refer to shown in Fig. 1 C to 1E, be multiple voluntarily as formation with cover curtain layer 200 in the first embodiment more than
It is directed at irrigation canals and ditches 206 and multiple etch masks for being voluntarily directed at irrigation canals and ditches 208 and the implantation for forming doping region in embedding type 212,214
Mask.First opening 202 of cover curtain layer 200 exposes two adjacent row doped region 22a, adjacent two doped region 22c, adjacent
Two row doped region 22b, some conductor layers (control gate) 20 and an isolation structure 12.Therefore, cover curtain layer 200
The width of first opening 202 is substantially equal to an isolation structure 12 and complete two adjacent doped region 22a width is total
With.However, the width of the first opening and the second opening of the cover curtain layer of the present invention is not limited with above-mentioned, can be according to the needs of reality
Adjustment.In addition, two source contacts 216a, 216b and two source contacts 220a, 220b are to be correspondingly arranged at respectively
On two doped region 22a and two doped region 22b.However, the present invention source contacts position or quantity also not more than
State and be limited, can need to adjust according to reality.
Fig. 5 is the top view of the manufacture method of the memory cell illustrated according to second embodiment of the invention.
Refer to shown in Fig. 5, be multiple voluntarily right as being formed with cover curtain layer 500 in the second embodiment of the present invention
Quasi- irrigation canals and ditches 506 and multiple etch masks for being voluntarily directed at irrigation canals and ditches 508 and the implantation for forming doping region in embedding type 512 and 514
Mask.First opening 502 of cover curtain layer 500 exposes two adjacent row doped regions of two adjacent row doped region 22a of part, part
22b, two doped region 22c, some conductor layers (control gate) 20 and an isolation structure 12.Therefore, cover curtain layer 500
The width of the first opening 502 be substantially equal to an isolation structure 12 and two adjacent doped region 22a partial width
Summation；The width of second opening 504 is then roughly the same with the second 204 (Fig. 1 C) of opening of first embodiment width.Therefore, institute
The width of the doping region in embedding type 512 of formation is smaller than the width of the doping region in embedding type 212 (Fig. 1 D) of first embodiment；And it is embedded to
The width of formula doped region 514 is roughly the same with the width of the doping region in embedding type 214 of first embodiment.In addition, two source electrodes connect
The position for touching window 516a, 516b and two source contacts 520a, 520b is still separately positioned near flush type doping
The adjacent two doped region 22a in area 214 and on the adjacent two doped region 22b of doping region in embedding type 214, and
It is electrically connected with doping region in embedding type 512.
Fig. 6 is the top view of the manufacture method of the memory cell illustrated according to third embodiment of the invention.
Refer to shown in figure, be voluntarily to be aligned with cover curtain layer 600 as formation is multiple in the third embodiment of the present invention
Irrigation canals and ditches 606 and multiple etch masks for being voluntarily directed at irrigation canals and ditches 608 and the implantation mask of formation doping region in embedding type 612 and 614.
The width of first opening 602 of cover curtain layer 600 is roughly the same with the first 202 (Fig. 1 C) of opening of first embodiment width；Its
The width of second opening 604 is roughly the same with the second 204 (Fig. 1 C) of opening of first embodiment width.Therefore, formed
The width of doping region in embedding type 612 is roughly the same with the width of the doping region in embedding type 212 (Fig. 1 D) of first embodiment；And it is embedded to
The width of formula doped region 614 is roughly the same with the width of the doping region in embedding type 214 (Fig. 1 D) of first embodiment.In addition, most
Single individual source electrode is set on voluntarily alignment irrigation canals and ditches 606 between the adjacent two doped region 22a of doping region in embedding type 214
Contact hole 616, and this source contacts 616 is electrically connected with doping region in embedding type 612；And near doping region in embedding type
Single individual source contacts 620, and this source are set on the voluntarily alignment irrigation canals and ditches 606 between 214 adjacent two doped region 22b
Pole contact hole 620 is electrically connected with doping region in embedding type 612.
Fig. 7 is the top view of the manufacture method of the memory cell illustrated according to fourth embodiment of the invention.Refer to Fig. 7 institutes
Show, be as the etch masks for forming multiple voluntarily alignment irrigation canals and ditches 708 with cover curtain layer 700 in the fourth embodiment of the present invention
And form the implantation mask of doping region in embedding type 712 and 714.First opening 702 of cover curtain layer 700 exposes in a first direction
Multiple doped region 22a, single individual doped region 22c, multiple doped region 22b of single row and some of the single row of extension
Conductor layer (control gate) 20.Therefore, in the present embodiment, only can be formed below multiple voluntarily right in corresponding second opening 704
Quasi- irrigation canals and ditches 708, and can't form the multiple of first embodiment such as below corresponding first opening 702 and voluntarily be directed at irrigation canals and ditches 206
(Fig. 1 C).The width of first opening 702 of cover curtain layer 700 is suitable with single individual doped region 22a width, the flush type formed
The width of doped region 712 is less than the width of the doping region in embedding type 212 (Fig. 1 D) of first embodiment.The second of cover curtain layer 700 opens
The width of mouth 704 is then roughly the same with the second 204 (Fig. 1 C) of opening of first embodiment width.Therefore, the embedment formed
The width of formula doped region 714 is roughly the same with the width of the doping region in embedding type 214 (Fig. 1 D) of first embodiment.In addition, most
Single individual source contacts 716, and source contacts 716 and embedment are set on the doped region 22a of doping region in embedding type 214
Formula doped region 712 is electrically connected with；And single individual source electrode is provided with the doped region 22b near doping region in embedding type 214
Contact hole 720, and source contacts 720 are electrically connected with doping region in embedding type 712.
Fig. 8 is the top view of the manufacture method of the memory cell illustrated according to fifth embodiment of the invention.Refer to Fig. 8 institutes
Show, be more as the multiple voluntarily alignment irrigation canals and ditches 806 of formation and formation with cover curtain layer 800 in the fifth embodiment of the present invention
The individual etch mask for being voluntarily directed at irrigation canals and ditches 808 and the implantation mask for forming doping region in embedding type 812 and 814.Cover curtain layer 800
First opening 802 exposes the adjacent doped region 22a of the multirow extended in a first direction, multiple adjacent doped region 22c, multirow
Adjacent doped region 22b, some conductor layers (control gate) 20 and its isolation structure 12 enclosed.Therefore, at this
In embodiment, corresponding first, which is open 802 times, can form the multiple voluntarily alignment irrigation canals and ditches 806 for being arranged in multirow.First opening 802
Width be substantially equal to multiple doped region 22a and its isolation structure enclosed width summation, therefore what is formed buries
Enter width of the width more than the doping region in embedding type 212 (Fig. 1 D) of first embodiment of formula doped region 812.The of cover curtain layer 800
The width of two openings 804 is then roughly the same with the width of the second opening 204 of first embodiment.Therefore, the flush type formed
The width of doped region 814 is roughly the same with the width of the doping region in embedding type 214 (Fig. 1 D) of first embodiment.In addition, multiple sources
Pole contact hole 816a, 816b, 816c and multiple source contacts 820a, 820b, 820c position be separately positioned near
Multiple doped region 22a of doping region in embedding type 214 and on multiple doped region 22b of doping region in embedding type 214, and with
Doping region in embedding type 812 is electrically connected with.
In summary described, the present invention can be formed through control gate and concatenation in the substrate by ion implantation technology
The low resistance doping region in embedding type of multiple doped regions.This doping region in embedding type can be electrically connected with source contacts, as source
Polar curve.Furthermore, it is possible to the doping region in embedding type of another low resistance is formed between Liang Qu simultaneously.In addition, the source electrode in same area connects
Touch window and be arranged on the same side with drain contact window, and be arranged in a row, the asymmetry and light shield manufacture for reducing exposure figure are answered
Miscellaneous degree.And the manufacturing process of doping region in embedding type need not additionally increase light shield, and can be with existing process integration, and can
To be voluntarily aligned, there is great process margin and the uniformity., can be with addition, the layout of doping region in embedding type is substantially rectilinear
Bending is not made, therefore the optical proximity effect amendment of complexity need not be carried out, therefore manufacturing cost can be greatly reduced.Separately
Outside, because the layout of doping region in embedding type is substantially rectilinear, it is not necessary to do in bending, therefore chip area can be saved and reached
More than 3%.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, without departing from the scope of the present invention, when method and technology contents using the disclosure above make it is a little more
Equivalent embodiment that is dynamic or being modified to equivalent variations, as long as being the content without departing from technical solution of the present invention, according to the present invention's
Any simple modification, equivalent change and modification that technical spirit is made to above example, still falls within technical solution of the present invention
In the range of.
Claims (10)
1. a kind of manufacture method of memory cell, it is characterised in that it comprises the following steps：
Multiple isolation structures are formed in a substrate, each isolation structure extends in a first direction；
Form multiple control gates over the substrate, each control gate extends in a second direction, the first direction with
The second direction is different；
Below each control gate, tunneling Jie is sequentially formed on the substrate between two isolation structures of arbitrary neighborhood
Dielectric layer between electric layer, a floating grid and a grid；
The both sides of the control gate in one first area of the substrate form one first doped region respectively, in the substrate
One second area in the both sides of the control gate form one second doped region respectively and in one the 3rd area of the substrate
It is middle to form multiple 3rd doped regions, wherein the 3rd area is between the firstth area and the secondth area；
A cover curtain layer is formed over the substrate, the cover curtain layer has one first intersecting opening and one second opening, wherein：
First opening extends in the first direction, at least exposes part first doped region, part described second
Doped region, multiple 3rd doped regions and the part control gate, and
Second opening extends in the second direction, and the isolation structure for exposing the 3rd area is mixed with the described 3rd
Miscellaneous area；
The exposed isolation structure of second opening is removed, ditch is voluntarily directed to form multiple first in the substrate
Canal；
Using the cover curtain layer as implantation mask, an ion implantation technology is carried out, to be formed：
One first doping region in embedding type, it extends in the first direction, exposed and by described positioned at the described first opening
In the substrate below control gate, exposed first doped region of electric connection first opening, described second are mixed
Miscellaneous area and the 3rd doped region；And
One second doping region in embedding type, it extends in the second direction, is mixed positioned at the described second opening the exposed described 3rd
In the substrate below miscellaneous area and described first is voluntarily aligned in the substrate of trench bottom and lateral wall circumference, and electrically
The 3rd doped region is connected, first doping region in embedding type is electrically connected with second doping region in embedding type；And
Remove the cover curtain layer.
2. the manufacture method of memory cell according to claim 1, it is characterised in that it also includes：
Mixed in described first with first doping region in embedding type electric connection and near second doping region in embedding type
At least one first source contacts are formed in miscellaneous area；And
Mixed in described second with first doping region in embedding type electric connection and near second doping region in embedding type
At least one second source contacts are formed in miscellaneous area.
3. the manufacture method of memory cell according to claim 1, it is characterised in that wherein described first opening exposes
At least two the first adjacent doped regions, at least two the second adjacent doped regions, at least two the 3rd adjacent doped regions, extremely
A few isolation structure and the part control gate, and when to be formed the described first voluntarily step of alignment irrigation canals and ditches, also
The isolation structure exposed including removing first opening, irrigation canals and ditches, and described first are voluntarily directed to form multiple second
Doping region in embedding type also extends into described second and is voluntarily aligned in the substrate of trench bottom and lateral wall circumference.
4. the manufacture method of memory cell according to claim 3, it is characterised in that it also includes：
In firstth area, one first is formed being voluntarily aligned near described the second of the second doping region in embedding type on irrigation canals and ditches
Source contacts, it is electrically connected with first doping region in embedding type；And
In secondth area, one second is formed being voluntarily aligned near described the second of the second doping region in embedding type on irrigation canals and ditches
Source contacts, it is electrically connected with first doping region in embedding type.
5. the manufacture method of memory cell according to claim 1, it is characterised in that wherein described ion implantation technology is
One inclination angle ion implantation technology, wherein the normal that direction and the substrate is ion implanted of the inclination angle ion implantation technology
Angle be 0 degree to 35 degree.
6. a kind of memory cell, it is characterised in that it includes：
One substrate, including one first area, one second area and one the 3rd area, wherein the 3rd area be located at firstth area with it is described
Irrigation canals and ditches are voluntarily directed between secondth area and with multiple first；
One first doping region in embedding type, extend in a first direction, positioned at part firstth area, part secondth area and portion
Divide in the substrate in the 3rd area；
One second doping region in embedding type, extend in a second direction, trench bottom and side wall week are voluntarily directed at positioned at described first
In the substrate in the 3rd area enclosed, and first doping region in embedding type electrically connects with second doping region in embedding type
Connect, the first direction is different from the second direction；
Multiple control gates, extend in the second direction, the substrate positioned at the both sides of second doping region in embedding type
Top, and across first doping region in embedding type；
Multiple floating grids, each floating grid is between corresponding control gate and the substrate；
Multiple tunneling dielectric layers, each tunneling dielectric layer is between corresponding floating grid and the substrate；
Dielectric layer between multiple grid, dielectric layer is between corresponding floating grid and corresponding control gate between each grid；
Multiple first doped regions, in firstth area in the substrate of each control gate both sides；
Multiple second doped regions, in secondth area in the substrate of each control gate both sides；And
Multiple 3rd doped regions, in the substrate in the 3rd area, wherein
First doping region in embedding type is electrically connected with part first doped region, part through control gate lower section
Second doped region and multiple 3rd doped regions, and second doping region in embedding type is electrically connected with the 3rd doping
Area.
7. memory cell according to claim 6, it is characterised in that it also includes：
One first source contacts, in firstth area, positioned at first doping region in embedding type be electrically connected with and most lean on
On first doped region of nearly second doping region in embedding type；And
One second source contacts, in secondth area, positioned at first doping region in embedding type be electrically connected with and most lean on
On second doped region of nearly second doping region in embedding type.
8. memory cell according to claim 6, it is characterised in that wherein described first doping region in embedding type is electrically connected with
The second adjacent doped region of the first adjacent doped region of at least two rows, at least two rows and at least two the 3rd adjacent doping
Area, and also extend into multiple second in the substrate and be voluntarily aligned in the substrate of trench bottom and lateral wall circumference, wherein
Described second voluntarily be aligned irrigation canals and ditches the first direction extension be in a line, electrically connect positioned at first doping region in embedding type
Between the first adjacent doped region of at least two rows that connect, between the second doped region that at least two rows are adjacent and at least
Between two the 3rd adjacent doped regions.
9. memory cell according to claim 8, it is characterised in that it also includes：
One first source contacts, in firstth area near second doping region in embedding type described second voluntarily
It is aligned on irrigation canals and ditches, is electrically connected with first doping region in embedding type；And
One second source contacts, in secondth area near second doping region in embedding type described second voluntarily
It is aligned on irrigation canals and ditches, is electrically connected with first doping region in embedding type.
10. memory cell according to claim 8, it is characterised in that it also includes：
At least two first source contacts, in firstth area, it is electrically connected with positioned at first doping region in embedding type
And on described at least two the first adjacent doped regions of second doping region in embedding type；And
At least two one the second source contacts, in secondth area, electrically connect positioned at first doping region in embedding type
Connect and on described at least two the second adjacent doped regions of second doping region in embedding type.
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| TW201112360A (en) * | 2009-09-25 | 2011-04-01 | Eon Silicon Solution Inc | Manufacturing method of NOR flash memory array and the device thereof |
| TW201405716A (en) * | 2012-07-27 | 2014-02-01 | Eon Silicon Solution Inc | Non-volatile memory having discontinuous isolation structure and SONOS memory cells and operating method and manufacturing method thereof |
| CN103730424A (en) * | 2012-10-15 | 2014-04-16 | 宜扬科技股份有限公司 | Method for manufacturing non-volatile memory and structure thereof |
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| TW201112360A (en) * | 2009-09-25 | 2011-04-01 | Eon Silicon Solution Inc | Manufacturing method of NOR flash memory array and the device thereof |
| TW201405716A (en) * | 2012-07-27 | 2014-02-01 | Eon Silicon Solution Inc | Non-volatile memory having discontinuous isolation structure and SONOS memory cells and operating method and manufacturing method thereof |
| CN103730424A (en) * | 2012-10-15 | 2014-04-16 | 宜扬科技股份有限公司 | Method for manufacturing non-volatile memory and structure thereof |
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