JP2006286862A - Designing method and manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a lithographic technique with a high accuracy in an ion implantation process. <P>SOLUTION: In a method for designing a semiconductor device, a plurality of standard cells SCs contained in a plurality of semiconductor regions 16 and 18 with transistors formed therein are arranged in a plurality of lines in the semiconductor regions 16 and 18, and a plurality of buried cells 13 are arranged so as to bury the openings of the two standard cells adjacent in each line. In the method for designing the semiconductor device, a plurality of channel implanting regions 14 for adjusting the threshold voltages of the transistors are arranged in response to a plurality of the semiconductor regions 16 and 18, the two channel implanting regions are synthesized by using the buried cells 13 when minimum-space contraventions based on a design rule are generated in the two channel implanting regions adjacent in each line, and a mask 15 is prepared by using the shape of the synthesized channel implanting region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device design method and manufacturing method, and more particularly to a semiconductor device design method and manufacturing method including a standard cell.

  2. Description of the Related Art In recent years, the progress of semiconductor device manufacturing technology has been very remarkable, and the miniaturization of elements included in a semiconductor device has been advanced. Such miniaturization of semiconductor elements has been realized by rapid progress in fine pattern formation technology such as mask process technology, lithography technology, and etching technology.

  In an era when the pattern size is sufficiently large, the planar shape of the LSI pattern to be formed on the wafer is drawn as it is as a design pattern, and a pattern that conforms to the design pattern is formed on the substrate using a mask that is created faithfully to the design pattern. did it.

  However, as pattern miniaturization progresses, it becomes difficult to form a pattern faithfully in each process, and the final finished dimension may not be the same as the design pattern.

  In particular, in the lithography and etching processes that are most important for achieving microfabrication, other pattern layout environments arranged around the pattern to be formed greatly affect the dimensional accuracy of the pattern.

  Therefore, in order to reduce these influences, proximity effect correction (OPC: Optical Proximity Correction) which is a method of selectively changing the shape of the design pattern in advance so that the dimension after processing is formed into a desired pattern Need to do.

  However, in order to perform highly accurate correction by OPC, it is necessary to add many fine auxiliary patterns to the design pattern. As a result, an increase in design time or mask creation time becomes a problem.

  Incidentally, standard cells are used in the layout design of semiconductor devices. The plurality of standard cells are arranged adjacent to each other vertically and horizontally. Further, the threshold voltage of the transistors constituting the standard cell is not one type, and depending on the cell arrangement, standard cells having the same threshold voltage can be arranged close to each other and separated from each other.

  For example, when standard cells having the same threshold voltage are arranged close to each other and each channel implantation region shares the substrate contact region, a minimum spacing violation in the design rule may occur on the substrate contact region. is there.

  Therefore, in order to avoid such a design rule violation in advance, a threshold different from the channel implantation region that determines the threshold voltage of the corresponding standard cell is formed on the substrate contact region existing at the standard cell boundary. The channel implantation region is also arranged at the same time. Since the channel implantation regions having different threshold values exist only on the substrate contact region, the channel implantation region becomes an elongated region, and as a result, a high-precision lithography technique is required even in the ion implantation process.

As this type of related technology, a technology for designing an integrated circuit having a degree of integration close to manual design with the same effort and time as a conventional standard cell system is disclosed (see Patent Document 1).
Japanese Patent Laid-Open No. 4-186865

  An object of the present invention is to provide a semiconductor device design method and a semiconductor device manufacturing method capable of reducing high-precision lithography technology in an ion implantation process.

  According to a first aspect of the present invention, there is provided a semiconductor device design method in which a plurality of standard cells, each including a plurality of semiconductor regions in which transistors are formed, are arranged in a plurality of rows, and two standard cells adjacent in each row are arranged. A plurality of embedded cells are arranged so as to embed a gap, a plurality of channel implantation regions corresponding to the plurality of semiconductor regions and a transistor for adjusting a threshold voltage are arranged, and two adjacent rows in each row are arranged. When a minimum interval violation based on the design rule occurs in the channel implantation region, the corresponding two channel implantation regions are synthesized using the embedded cell, and a mask is created using the shape of the synthesized channel implantation region.

  According to a second aspect of the present invention, there is provided a method for designing a semiconductor device, wherein a substrate contact region having a first conductivity type and supplying power to a substrate is disposed, A plurality of standard cells including a first semiconductor region of a conductivity type and a second semiconductor region of a second conductivity type are disposed, and the first semiconductor region is disposed on the substrate contact region side, The embedded cells are arranged so as to be embedded between the two rows of the plurality of standard cells, and the threshold voltage of the transistor is adjusted so as to correspond to the first semiconductor region and overlap the substrate contact region. A plurality of channel implantation regions are arranged, and a minimum interval violation based on a design rule among the plurality of channel implantation regions occurs on the embedded cell. If the combines the two channel implantation region corresponding with the embedded cells, to create a mask using the shape of the synthesized channel implantation region.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a plurality of semiconductor regions that are respectively included in a plurality of standard cells and in which transistors are formed are formed in a plurality of rows, and the transistors are formed in the semiconductor regions. A plurality of channel implantation regions for adjusting the threshold voltage are formed by using a plurality of masks, and the plurality of masks cause a minimum interval violation based on the design rule in two adjacent channel implantation regions in each row 2 A mask having a shape obtained by synthesizing two channel implantation regions is included.

  ADVANTAGE OF THE INVENTION According to this invention, the design method of the semiconductor device which can reduce the highly accurate lithography technique in an ion implantation process, and the manufacturing method of a semiconductor device can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a flowchart showing a method for designing a semiconductor device according to the first embodiment of the present invention.

First, a substrate contact region 11 (also referred to as a body contact) which is a P ⁺ diffusion region for supplying the ground potential Vss to the substrate, and a substrate contact which is an N ⁺ diffusion region for supplying the power supply potential Vdd to the substrate. The regions 12-1 and 12-2 are arranged on the substrate (step S1a). FIG. 2 is a layout diagram showing a plurality of substrate contact regions.

  The substrate contact region 11 is connected to the ground potential Vss. The substrate contact regions 12-1 and 12-2 are connected to the power supply potential Vdd. The widths of these substrate contact regions are defined as design rules based on the threshold voltage of the transistor and the like.

  Next, a plurality of standard cells are arranged (step S1b). A standard cell is a set of basic gates such as a CMOS circuit and an AND circuit. For example, the standard cell has a constant width (a length in the Y direction in FIG. 3) and a different length (a length in the X direction in FIG. 3). The length of this standard cell varies depending on the type of CMOS circuit or AND circuit. The plurality of standard cells include a plurality of types of standard cells in which the threshold voltages of the transistors included in the standard cells are different.

  FIG. 3 is a layout diagram showing a plurality of standard cells. FIG. 3 shows six standard cells SC1 to SC6 as an example. Standard cells SC1 and SC5 have the same threshold voltage. Standard cells SC2, SC4, SC6 have different threshold voltages from standard cells SC1, SC5.

  Each standard cell includes a P-type well (P-type semiconductor region) in which an N-type MOS transistor is formed, and an N-type well (N-type semiconductor region) in which a P-type MOS transistor is formed. It has. The two P-type wells in the first row (consisting of standard cells SC1 to SC3) and the second row (consisting of standard cells SC4 to SC6) are arranged to face each other. FIG. 3 shows an example of the P-type well 16 and the N-type well 17 included in the standard cell SC1, and the P-type well 18 and the N-type well 19 included in the standard cell SC5.

  For example, when an N-type well and a P-type well are arranged in order, the substrate contact region 11 and the substrate contact region 12-1 must be arranged for one column. However, by disposing the two P-type wells in the first row and the second row so as to face each other, the substrate contact region 11 corresponding to these can be made one. Thereby, a circuit area can be reduced.

  Further, wells of the same conductivity type as the substrate contact region are arranged on both sides of the substrate contact region. By doing so, a channel implantation region described later can be formed so as to overlap the substrate contact region. Therefore, high-precision lithography for forming the channel implantation region is not necessary.

  The design process for arranging the standard cells is not limited to the above. As described above, the standard cells have the same width. Therefore, the standard cells may be arranged in a plurality of rows, and the region formed between each row may be designed as a substrate contact region.

  Next, an embedded cell 13 for embedding between a plurality of rows is arranged (step S1c). FIG. 4 is a layout diagram showing the embedded cell 13. The embedded cell 13 serves as a correction layer for avoiding a minimum violation of the design rule.

  Next, the source region and drain region of the P-type MOS transistor and the N-type MOS transistor included in the standard cell are arranged (step S1d).

  Next, a plurality of P-type and N-type channel implantation regions (or channel ion implantation regions), which are channel ion implantation diffusion regions for adjusting the threshold voltage of the transistor, are disposed (step S1e). This channel implantation region is disposed so as to surround the corresponding source region and drain region and to overlap with the adjacent substrate contact region. Thus, by implanting high-concentration impurities also onto the substrate contact region, the contact resistance of contact plugs and the like formed on the substrate contact region can be lowered.

  FIG. 5 is a layout diagram showing a channel implantation region. FIG. 5 shows a P-type channel implant region 14-1P and an N-type channel implant region 14-1N of the standard cell SC1, and a P-type channel implant region 14-2P and an N-type channel implant region 14-2N of the standard cell SC5. Is shown. In order to clarify the layout, only the P-type channel implantation regions 14-1P and 14-2P are hatched.

  Next, it is determined by DRC (Design Rule Check) whether or not a minimum interval violation of the channel implantation region has occurred (step S1f). This minimum spacing violation is determined for two adjacent channel implant regions having the same threshold voltage.

  Next, when a minimum interval violation is detected, the corresponding two channel implantation regions are synthesized using a part of the embedded cell 13 (step S1g). In FIG. 5, P-type channel implantation regions 14-1P and 14-2P cause a minimum interval violation. FIG. 6 is a diagram showing the shape of the synthesized channel implantation region 15. The series of design steps is performed using a data group (layer).

  Then, mask data is created using the synthesized data group (layer) of the channel implantation region, and a mask for forming the channel implantation region is created based on the mask data (step S1h).

  By using such a design method, it is possible to avoid the minimum interval violation of the channel implantation region. In addition, in order to avoid the violation of the minimum interval of the channel implantation region, it is not necessary to previously form elongated channel implantation regions corresponding to all threshold voltages between the rows of the standard cells. Thereby, since it is not necessary to perform highly accurate lithography, the manufacturing process of a semiconductor device can be simplified.

  In particular, in the lithography and etching processes that are most important for achieving microfabrication, other pattern layout environments arranged around the pattern to be formed greatly affect the dimensional accuracy of the pattern.

  Therefore, in order to reduce these influences, proximity effect correction (OPC), which is a method of selectively changing the shape of the design pattern in advance so that the dimension after processing is formed into a desired pattern, is performed. There is a need to do.

  However, if the above-described design method is used, fine processing can be reduced, so that the design time for creating a pattern can be reduced.

  Next, a method for manufacturing a semiconductor device will be described. FIG. 7 is a plan view schematically showing the semiconductor device.

First, the surface of the P-type semiconductor substrate 21 is etched to a predetermined depth so as to leave an active area AA in which standard cells and substrate contact areas are formed. Then, an insulating layer made of, for example, SiO ₂ is embedded in the etched region to form STI (Shallow Trench Isolation).

  Next, as shown in FIG. 8 (sectional view taken along line VIII-VIII shown in FIG. 7), P-type impurities are ion-implanted into the P-type semiconductor substrate 21 to form a P-type well 22. Also, N-type impurities are ion-implanted into the P-type semiconductor substrate 21 to form N-type wells 23 and 24.

Next, as shown in FIGS. 9 and 10 (cross-sectional view taken along the line XX shown in FIG. 7), high concentration P ⁺ -type impurities are ion-implanted into the semiconductor substrate 21, and the substrate contact region 11. Form. Similarly, high concentration N ⁺ -type impurities are ion-implanted into the semiconductor substrate 21 to form substrate contact regions 12-1 and 12-2.

  Next, P-type impurities are ion-implanted into the surface region of the semiconductor substrate 21 to form the channel implantation region 15. In the formation process of the channel implant region 15, the above-described mask is used. Similarly, N-type impurities are ion-implanted into the surface region of the semiconductor substrate 21 to form an N-type channel implantation region.

Next, as shown in FIGS. 11 and 12, a gate insulating film 25 made of, for example, SiO ₂ is formed on the semiconductor substrate 21. Next, a gate electrode 26 made of polysilicon is formed on the gate insulating film 25 by using a CVD (Chemical Vapor Deposition) method and an etching method.

  Next, P-type impurities are ion-implanted into the P-type well 22 using the gate electrode 26 as a mask to form halo. Further, N-type impurities are ion-implanted into the P-type well 22 using the gate electrode 26 as a mask to form extension regions 27 and 28.

  Further, Halo for P-type MOS transistors and extension regions 29 and 30 are formed in the N-type wells 23 and 24.

Next, as shown in FIGS. 13 and 14, sidewall insulating films 31 made of SiN are formed on both side surfaces of the gate electrode 26 by using the CVD method and the etching method. Then, a high concentration P ⁺ -type impurity is ion-implanted into the P-type well 22 using the sidewall insulating film 31 as a mask to form a source region 32 and a drain region 33.

  Next, an interlayer insulating film (not shown) made of, for example, BPSG (Boron Phosphorus Silicate Glass) is formed on the semiconductor substrate 21 by CVD. Next, a contact plug 34 is formed on the substrate contact region 11 by using the RIE (Reactive Ion Etching) method. In addition, contact plugs 36 are formed on the source region 32 and the drain region 33, respectively, using the RIE method. Then, metal wiring 37 is formed on the contact plugs 34 and 36.

  In the semiconductor device thus formed, it is not necessary to perform high-precision lithography when forming the substrate contact region 11. Thereby, the manufacturing process of the semiconductor device can be simplified.

(Second Embodiment)
The second embodiment shows a design method in the case where two standard cells having the same transistor threshold voltage are arranged in the same row.

  A method for designing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 15, a substrate contact region 51 which is a P ⁺ diffusion region for supplying the ground potential Vss to the substrate, and a substrate contact region which is an N ⁺ diffusion region for supplying the power supply potential Vdd to the substrate. 52 are arranged on the substrate.

  Next, a plurality of standard cells are arranged. For simplification, only two standard cells SC1 and SC2 are shown in FIG. The two standard cells SC1 and SC2 have the same threshold voltage.

  The standard cell SC1 includes a P-type well 53, which is a region where an N-type MOS transistor is formed, and an N-type well 54, which is a region where a P-type MOS transistor is formed. On the region 51 side, the N-type well 54 is disposed on the substrate contact region 52 side. The standard cell SC2 includes a P-type well 55 and an N-type well 56. The P-type well 55 is disposed on the substrate contact region 51 side, and the N-type well 56 is disposed on the substrate contact region 52 side.

  Here, there is a gap 57 between the standard cells SC1 and SC2. For example, in the layout design performed on the computer, the standard cell is mechanically arranged, and thus the gap 57 may be generated in this way.

  Next, as shown in FIG. 16, an embedded cell 62 for embedding the gap 57 generated between the standard cells is arranged. The embedded cell 62 has a role of a correction layer for avoiding a design rule minimum interval violation.

  Next, the source region and drain region of the P-type MOS transistor and N-type MOS transistor included in the standard cell are arranged. Next, P-type channel implantation regions 58 and 60 are disposed so as to surround the corresponding source region and drain region and overlap the adjacent substrate contact region 51. In addition, N-type channel implantation regions 59 and 61 are disposed so as to surround the corresponding source region and drain region and overlap the adjacent substrate contact region 52 (see FIG. 16).

  Next, it is determined whether or not a minimum interval violation of the channel implantation region has occurred by DRC. This minimum spacing violation is determined for two adjacent channel implant regions having the same threshold voltage.

  Next, when the minimum interval violation is detected, the corresponding two channel implantation regions are combined using the embedded cell. In FIG. 16, the P-type channel implant regions 58 and 60 cause a minimum distance violation. Further, the N-type channel implant regions 59 and 61 cause a minimum interval violation.

  FIG. 17 is a diagram showing the synthesized channel implantation region. The channel implantation region 63 is a combination of the channel implantation regions 58 and 60. The channel implantation region 64 is a combination of the channel implantation regions 59 and 61.

  Then, mask data is created using the combined data group (layer) of the channel implantation region, and a mask for forming the channel implantation region is created based on the mask data.

  By using such a design method, it is possible to avoid the minimum interval violation of the channel implantation region. Further, in order to avoid the minimum interval violation of the channel implantation region, it is not necessary to previously form elongated channel implantation regions corresponding to all threshold voltages in the gaps of the plurality of standard cells. Thereby, since it is not necessary to perform highly accurate lithography, the manufacturing process of a semiconductor device can be simplified. Other effects are the same as those of the first embodiment.

(Third embodiment)
The third embodiment shows a design method in the case where a gap is generated between standard cells in the same row and a minimum interval violation occurs in the channel implantation region of the standard cells included in two adjacent rows.

  A method for designing a semiconductor device according to the third embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 18, a substrate contact region 11 which is a P ⁺ diffusion region for supplying the ground potential Vss to the substrate, and a substrate contact region which is an N ⁺ diffusion region for supplying the power supply potential Vdd to the substrate. 12-1 and 12-2 are arranged on the substrate.

  Next, a plurality of standard cells are arranged. FIG. 18 shows six standard cells SC1 to SC6 as an example. Standard cells SC1 and SC5 have the same threshold voltage. Standard cells SC2, SC4, SC6 have different threshold voltages from standard cells SC1, SC5.

  Each standard cell includes a P-type well, which is a region where an N-type MOS transistor is formed, and an N-type well, which is a region where a P-type MOS transistor is formed. The two P-type wells in the first row and the second row are arranged to face each other.

  Here, there are a plurality of gaps between the plurality of standard cells. Next, as shown in FIG. 19, an embedded cell for embedding a gap generated between the standard cells is arranged. Separate embedded cells are arranged in the gap between the N-type wells and the gap between the P-type wells. In FIG. 19, embedded cells 71-1 to 71-3 are arranged in the gaps between the P-type wells. Embedded cells 72-1 to 72-4 are arranged in the gaps between the N-type wells.

  Next, the source region and drain region of the P-type MOS transistor and N-type MOS transistor included in the standard cell are arranged.

  Next, a plurality of channel implantation regions are arranged. This channel implantation region is disposed so as to surround the corresponding source region and drain region and to overlap with the adjacent substrate contact region.

  FIG. 20 is a layout diagram showing a channel implantation region. FIG. 20 shows a P-type channel implant region 14-1P and an N-type channel implant region 14-1N of the standard cell SC1, and a P-type channel implant region 14-2P and an N-type channel implant region 14-2N of the standard cell SC5. Is shown. In order to clarify the layout, only the P-type channel implantation regions 14-1P and 14-2P are hatched.

  Next, it is determined whether or not a minimum interval violation of the channel implantation region has occurred by DRC. This minimum spacing violation is determined for two adjacent channel implant regions having the same threshold voltage.

  Next, when the minimum interval violation is detected, the corresponding two channel implantation regions are combined using the embedded cell. In FIG. 20, P-type channel implantation regions 14-1P and 14-2P cause a minimum interval violation. Therefore, the P-type channel implantation regions 14-1P and 14-2P and the embedded cell 71-2 are combined to generate one new channel implantation region. FIG. 21 is a diagram showing the shape of the synthesized channel implantation region 73.

  Then, mask data is created using the combined data group (layer) of the channel implantation region, and a mask for forming the channel implantation region is created based on the mask data.

  By using such a design method, it is possible to avoid the minimum interval violation of the channel implantation region. Other effects are the same as those of the first embodiment.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

3 is a flowchart showing a method for designing a semiconductor device according to the first embodiment of the present invention. 1 is a layout diagram for explaining a method for designing a semiconductor device according to a first embodiment of the present invention; FIG. 3 is a layout diagram for explaining a semiconductor device design method following FIG. 2; FIG. 4 is a layout diagram for explaining a semiconductor device design method following FIG. 3; FIG. 5 is a layout diagram for explaining a semiconductor device design method following FIG. 4. The figure which shows the shape of the synthetic | combination channel implant area | region 15. 1 is a plan view schematically showing a semiconductor device according to a first embodiment of the present invention. Sectional drawing along the VIII-VIII line for demonstrating the manufacturing method of the semiconductor device shown in FIG. Sectional drawing for demonstrating the manufacturing method following FIG. Sectional drawing in alignment with the XX line for demonstrating the manufacturing method of the semiconductor device shown in FIG. Sectional drawing for demonstrating the manufacturing method following FIG. Sectional drawing for demonstrating the manufacturing method following FIG. Sectional drawing for demonstrating the manufacturing method following FIG. Sectional drawing for demonstrating the manufacturing method following FIG. FIG. 6 is a layout diagram for explaining a method for designing a semiconductor device according to a second embodiment of the present invention. FIG. 16 is a layout diagram for explaining the semiconductor device design method following FIG. 15; The figure which shows the shape of the synthetic | combination channel implantation area | region 63,64. FIG. 9 is a layout diagram for explaining a semiconductor device design method according to a third embodiment of the present invention. FIG. 19 is a layout diagram for explaining the semiconductor device design method following FIG. 18; FIG. 20 is a layout diagram for describing the semiconductor device design method following FIG. 19. The figure which shows the shape of the synthesized channel implantation area | region 73. FIG.

Explanation of symbols

  SC ... Standard cell 11, 12, 1, 12-2, 51, 52 ... Substrate contact region 13, 62, 71-1, 71-2, 71-3, 72-1, 72-2, 72-3 , 72-4... Embedded cell, 14-1P, 14-2P, 58... P type channel implantation region, 14-1N, 14-2N, 59... N type channel implantation region, 15, 63, 64, 73. Channel implant region, 16, 18, 22, 53, 55 P-type well, 17, 19, 23, 54, 56 N-type well, 21 P-type semiconductor substrate, 25 gate insulating film, 26 gate electrode 27, 28, 29, 30 ... extension region, 31 ... sidewall insulating film, 32 ... source region, 33 ... drain region, 34, 36 ... contact plug, 37 ... metal wiring, 57 ... gap.

Claims (5)

A plurality of standard cells each including a plurality of semiconductor regions in which transistors are formed are arranged in a plurality of rows,
A plurality of embedded cells are arranged so as to embed a gap between two adjacent standard cells in each row,
A plurality of channel implantation regions corresponding to the plurality of semiconductor regions and for adjusting a threshold voltage of the transistor,
When a minimum interval violation based on a design rule occurs in two adjacent channel implantation regions in each row, the corresponding two channel implantation regions are synthesized using the embedded cell,
Create a mask using the shape of the synthesized channel implantation region,
A method for designing a semiconductor device. The plurality of standard cells each include a plurality of first semiconductor regions of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type,
2. The semiconductor device according to claim 1, wherein the plurality of channel implantation regions include a plurality of first channel implantation regions of a first conductivity type and a plurality of second channel implantation regions of a second conductivity type. Design method. A substrate contact region having a first conductivity type and supplying power to the substrate;
A plurality of standard cells including a first conductive type first semiconductor region and a second conductive type second semiconductor region are disposed on both sides of the substrate contact region, and the first semiconductor region is disposed on the substrate contact region side. Arranged,
An embedded cell is disposed on the substrate contact region so as to be embedded between two rows of the plurality of standard cells,
A plurality of channel implantation regions for adjusting a threshold voltage of the transistor so as to correspond to the first semiconductor region and overlap the substrate contact region;
When a minimum interval violation based on a design rule occurs among the plurality of channel implantation regions on the embedded cell, the corresponding two channel implantation regions are synthesized using the embedded cell,
Create a mask using the shape of the synthesized channel implantation region,
A method for designing a semiconductor device.   4. The method of designing a semiconductor device according to claim 1, wherein the two channel implantation regions where the minimum interval violation has occurred have the same threshold voltage. Forming a plurality of semiconductor regions, which are respectively included in a plurality of standard cells and in which transistors are formed, in a plurality of rows;
In the semiconductor region, a plurality of channel implantation regions for adjusting the threshold voltage of the transistor are formed using a plurality of masks, and the plurality of masks conforms to design rules in two channel implantation regions adjacent to each row. A mask having a shape that is a composite of two channel implant regions where a minimum spacing violation has occurred,
A method for manufacturing a semiconductor device.

Images