KR20040079057A - Method of manufacturing NAND flash memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a NAND flash memory device is provided to increase a punch-through voltage and reduce an off-leakage current by obtaining a desired threshold voltage by only one masking process for targeting the threshold voltage of a channel region of a select transistor. CONSTITUTION: Cell transistor threshold voltage ion implantation regions(22) are formed in a cell transistor region and a select transistor region of a semiconductor substrate(21). A plurality of gates(25C) of cell transistors and a plurality of gates(25S) of select transistors are formed. Photoresist is formed on the resultant structure. The photoresist in the cell transistor region and the select transistor region is exposed by using a cell source/drain mask. The exposed photoresist is developed wherein a predetermined thickness of the photoresist is left between the gates of the cell transistors. A halo ion implantation process is slantingly performed on a side of the gate of the select transistor to form a halo ion implantation region(24L,24R) under the gate of the select transistor. The photoresist left between the gates of the cell transistors are eliminated by a descum process. After a source/drain junction part(26) is formed by a cell source/drain ion implantation process, a photoresist strip process is performed.

Description

Method of manufacturing NAND flash memory device {Method of manufacturing NAND flash memory device}

The present invention relates to a method for manufacturing a NAND flash memory device, and more particularly, to a method for manufacturing a NAND flash memory device capable of improving the characteristics of a select transistor included in a cell array.

NAND flash memory devices include select transistors in a cell array. The selection transistor is formed between a block composed of a plurality of cell transistors and a block, and selects a block for a program operation, an erase operation, and a read operation of the cell, or blocks a block that is not selected. As the gate transistor becomes narrower and the gate length becomes shorter due to the high integration of the device, the select transistor has the biggest problems such as the threshold voltage target (Vt target) and the off-leakage current. It is becoming.

1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a conventional NAND flash memory device.

Referring to FIG. 1A, a threshold voltage ion implantation region 12 of a cell transistor is formed on a semiconductor substrate 11 on which a well formation process is performed. The threshold voltage ion implantation region 12 of the cell transistor is subjected to a cell transistor threshold voltage ion implantation masking process so that the cell transistor region and the select transistor region are opened, and then a threshold voltage ion implantation process and a photoresist strip process are performed. Is formed. The threshold voltage ion implantation process is performed considering that the threshold voltage of the cell transistor is about 0.3V.

Referring to FIG. 1B, the photoresist pattern 13 having the selection transistor region opened by the selection transistor threshold voltage ion implantation masking process is formed on the semiconductor substrate 11 on which the threshold voltage ion implantation region 12 is formed. In the voltage ion implantation process, the threshold voltage ion implantation region 14 of the selection transistor is formed. The threshold voltage ion implantation region 14 of the selection transistor overlaps the threshold voltage ion implantation region 12 of the previously formed cell transistor, and the ion implantation process is performed considering that the threshold voltage of the selection transistor is about 0.55V.

Referring to FIG. 1C, the gate oxide film forming process, the device isolation film forming process, and the gate forming process are sequentially performed, so that the gates 15C of the plurality of cell transistors in the cell transistor region and the gates of the two select transistors in the select transistor region. 15S is formed. After performing the cell source / drain ion implantation masking process in which the cell transistor region and the select transistor region are opened, the source / drain junction 16 is formed by the cell source / drain ion implantation process and the photoresist strip process. . The threshold voltage ion implantation region 12 under the gate 15C of the cell transistor becomes the channel region 120 of the cell transistor, and the threshold voltage ion implantation region 14 under the gate 15S of the select transistor is formed of the selection transistor. Channel region 140.

Through the above process steps, a cell transistor and a selection transistor are formed. Since the channel region 140 of the selection transistor has to go through two masking processes and two ion implantation processes for threshold voltage targeting, a punch-through voltage is required. (punchthrough voltage) is reduced, off-leakage current (off-leakage current) is increased, the threshold voltage fluctuation (Vt fluctuation) is a problem occurs, causing a cell malfunction. This problem is further exacerbated by a transistor having a gate width of 0.115 μm and a gate length of 0.18 μm as the gate width becomes shorter and the gate length becomes shorter due to high integration of the device.

Accordingly, the present invention enables the desired threshold voltage to be obtained even after applying the masking process only once for the target voltage targeting of the channel region of the select transistor, thereby increasing the punch-through voltage, reducing the off-leakage current, and reducing the threshold voltage. It is an object of the present invention to provide a method for manufacturing a NAND flash memory device capable of reducing fluctuations.

1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a conventional NAND flash memory device.

2A to 2E are cross-sectional views of a device for explaining a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

3 is a graph showing a decrease in leakage current in a device to which a halo ion implantation process is applied.

4 is a graph showing the improvement of current uniformity in a device to which a halo ion implantation process is applied.

<Explanation of symbols for the main parts of the drawings>

11, 21: semiconductor substrate

12, 22: threshold voltage ion implantation region of the cell transistor

13, 23: photoresist

14: threshold voltage ion implantation region of the select transistor

24L, 24R: halo ion implantation region 15C, 25C: gate of cell transistor

15S, 25S: Gates 16 and 26 of select transistors: source / drain junction

120, 220: channel region of the cell transistor

140, 240: channel region of a select transistor

According to an aspect of the present invention, there is provided a method of manufacturing a NAND flash memory device, the method including: forming a cell transistor threshold voltage ion implantation region in a cell transistor region and a selection transistor region of a semiconductor substrate; Forming gates of a plurality of cell transistors and gates of select transistors; Applying a photoresist over the entire structure; Exposing a photoresist of said cell transistor region and said selection transistor region using a cell source / drain mask; Developing the exposed photoresist, leaving the photoresist at a predetermined thickness between gates of the cell transistor; Performing halo ion implantation inclined in one direction of the gate of the selection transistor to form a halo ion implantation region in a portion under the gate of the selection transistor; Removing photoresist remaining between gates of the cell transistor by a descom process; Forming a source / drain junction by a cell source / drain ion implantation process, and then performing a photoresist strip process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.

2A to 2E are cross-sectional views of devices for explaining a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

Referring to FIG. 2A, a threshold voltage ion implantation region 22 of a cell transistor is formed in a semiconductor substrate 21 in which a well formation process is performed. The threshold voltage ion implantation region 22 of the cell transistor is subjected to a cell transistor threshold voltage ion implantation masking process so that the cell transistor region and the select transistor region are opened, and then a threshold voltage ion implantation process and a photoresist strip process are performed. Is formed. The threshold voltage ion implantation process is performed considering that the threshold voltage of the cell transistor is about 0.3V.

Referring to FIG. 2B, the gate oxide film forming process, the device isolation film forming process, and the gate forming process are sequentially performed on the semiconductor substrate 21 on which the threshold voltage ion implantation region 22 is formed, and thus a plurality of cell transistors are formed in the cell transistor region. The gate 25C of the two select transistors is formed in the select transistor region. The photoresist 23 is applied over the entire structure on which the gates 25C and 25S are formed, and the photoresist 23 of the cell transistor region and the selected transistor region is exposed using a cell source / drain mask, and then developed. The photoresist 23 remains at a predetermined thickness between the gates 25C of the cell transistors, and is completely removed between the gates 25S of the select transistors.

In the above, the photoresist 23 uses an i-line photoresist. The photoresist 23 left between the gate 25Cs of the cell transistors by the developing process remains at a thickness of 500 to 1000 Å because the step of the gates 25C of the cell transistors is about 0.6 mu m. This is because the space between (25C) is about 0.115 mu m, so that the boundary is defined only to a depth limited to the eye-line wavelength. On the other hand, since the space between the gates 25S of the select transistor is about 0.45 탆, the photoresist 23 is completely removed. On the other hand, the conventional NAND flash memory device lays out the space with the gate 25C of the cell transistor adjacent to the gate 25S of the selection transistor at 0.18 mu m. In the present invention, the photoresist 23 is also secured in this portion. Layout is reduced to 0.115㎛ to remain.

Referring to FIG. 2C, a first halo ion implantation region 24L is first applied to a portion of the gate 25S of the select transistor positioned on the left side by performing halo ion implantation inclined in the right direction of the gate 25S of the select transistor. Is formed.

Referring to FIG. 2D, the second halo ion implantation region 24R is applied to the gate 25S portion of the select transistor positioned on the right side by performing halo ion implantation in an inclined direction from the left side of the gate 25S of the select transistor. Is formed.

In the above, the halo ion implantation process for forming the first and second halo ion implantation regions 24L and 24R is carried out under the conditions of the ion implantation energy of 15 KeV, the dose amount of 4E12 and the incidence angle of 20 to 50 degrees only in direction. do. The photoresist 23 serves as an ion implantation prevention film during the halo ion implantation process.

Referring to FIG. 2E, a cell source / drain ion implantation masking process in which the photoresist 23 remaining in the cell transistor region is completely removed by a descum process, thereby completely opening the cell transistor region and the selected transistor region. Is complete. Thereafter, the source / drain junction 26 is formed by a cell source / drain ion implantation process and a photoresist strip process. The threshold voltage ion implantation region 22 under the gate 25C of the cell transistor becomes the channel region 220 of the cell transistor, and the threshold voltage ion implantation region 22 and halo ion implantation under the gate 25S of the selection transistor. The region 24L or 24R becomes the channel region 240 of the select transistor.

As can be seen from the graphs of FIGS. 3 and 4, if the halo ion implantation conditions described above, the channel region 240 of the selection transistor has a threshold of about 0.25V since the halo ion implantation region 24L or 24R is formed at one side. There is a voltage increase, and 0.55 V, which is a desired threshold voltage of the selection transistor, can be obtained.

As described above, the present invention enables the desired threshold voltage to be obtained even after applying the masking process only once for the target voltage targeting of the channel region of the selection transistor, thereby increasing the punch-through voltage and reducing the off-leakage current. Fluctuation in the threshold voltage can be reduced, thereby improving device reliability.

Claims (5)

Forming a cell transistor threshold voltage ion implantation region in a cell transistor region and a selection transistor region of a semiconductor substrate; Forming gates of a plurality of cell transistors and gates of select transistors; Applying a photoresist over the entire structure; Exposing a photoresist of said cell transistor region and said selection transistor region using a cell source / drain mask; Developing the exposed photoresist, leaving the photoresist at a predetermined thickness between gates of the cell transistor; Performing halo ion implantation inclined in one direction of the gate of the selection transistor to form a halo ion implantation region in a portion under the gate of the selection transistor; Removing photoresist remaining between gates of the cell transistor by a descom process; And forming a source / drain junction in a cell source / drain ion implantation process, and then performing a photoresist strip process. The method of claim 1, wherein the photoresist uses an eye-line photoresist. The method of claim 1, wherein the photoresist left between the gates of the cell transistors is left to a thickness of 500 to 1000 Å. The NAND flash memory device manufacturing method according to claim 1, wherein the halo ion implantation process is performed under conditions of an ion implantation energy of 15 KeV, a dose amount of 4E12, and an incident angle of 20 to 50 degrees. The method of claim 1, wherein the channel region of the selection transistor comprises a threshold voltage ion implantation region and a halo ion implantation region.