CN104011863A - 具有与容纳区处于热平衡的沟道区的忆阻器 - Google Patents

具有与容纳区处于热平衡的沟道区的忆阻器 Download PDF

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CN104011863A
CN104011863A CN201280065140.6A CN201280065140A CN104011863A CN 104011863 A CN104011863 A CN 104011863A CN 201280065140 A CN201280065140 A CN 201280065140A CN 104011863 A CN104011863 A CN 104011863A
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channel region
district
memristor
contact zone
hold
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苗峰
杨建华
约翰·保罗·斯特罗恩
易伟
吉尔贝托·梅代罗斯·里贝罗
R·斯坦利·威廉姆斯
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Hewlett Packard Enterprise Development LP
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/24Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/041Modification of switching materials after formation, e.g. doping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/041Modification of switching materials after formation, e.g. doping
    • H10N70/043Modification of switching materials after formation, e.g. doping by implantation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/24Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/821Device geometry
    • H10N70/826Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/821Device geometry
    • H10N70/828Current flow limiting means within the switching material region, e.g. constrictions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/883Oxides or nitrides
    • H10N70/8833Binary metal oxides, e.g. TaOx
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B63/00Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays

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  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)
  • Semiconductor Memories (AREA)
  • Micromachines (AREA)

Abstract

一种具有与容纳区处于热平衡的沟道区的忆阻器。该沟道区具有可变浓度的移动离子。由化学计量晶体材料制成的容纳区容纳沟道区且与沟道区处于热平衡。

Description

具有与容纳区处于热平衡的沟道区的忆阻器
背景技术
当前诸如DRAM(动态随机存取存储器)、SRAM(静态RAM)和NAND闪存之类的存储器技术正接近其扩展性极限。对能够满足未来存储器应用的增长性能需求的新存储器技术存在逐渐增长的需求。忆阻器技术具有满足此需求的潜力。忆阻器依赖于移动电荷在施加电场时的漂移。忆阻器包括设置在两个接触区之间的导电沟道。可以在交叉(crossbar)结构中制造大量忆阻器。忆阻器提供非易失性的及多状态的数据存储。它们可以在三个维度上堆叠,并且与CMOS技术兼容。由像钽的氧化物这样的材料制造的忆阻器已显示出高耐用性,在一些情况下超过1012个开关循环。
附图说明
附图不是按比例绘制的。它们通过示例说明本公开。
图1是具有与容纳区处于热平衡的沟道区的忆阻器的示例的透视图。
图2是沿图1的线2-2的剖面图。
图3是具有与容纳区处于热平衡的沟道区的忆阻器的另一示例的剖面图。
图4是具有与容纳区处于热平衡的沟道区的忆阻器的电流-电压(I-V)曲线。
图5是忆阻器的交叉结构的透视图,每个忆阻器具有与容纳区处于热平衡的沟道区。
图6是具有与容纳区处于热平衡的圆柱形沟道区的忆阻器的示例的透视图。
图7是示出制造具有与容纳区处于热平衡的沟道区的忆阻器的方法的示例的流程图。
具体实施方式
说明性示例和细节在附图中和在本说明书中使用,但是其它配置可以存在且可以体现自己。诸如电压、温度、尺寸以及组件值之类的参数是近似的。诸如上、下、顶部及底部之类的方向术语仅用于方便表示组件相对于彼此的空间关系,并且除另有说明以外,相对于外部轴线的方向不是重要的。为了清楚,未详细地描述一些已知的方法和结构。由权利要求限定的方法可以包括除所列出的那些以外的步骤,并且除权利要求本身中另有说明以外,这些步骤可以以所给出的顺序不同的另一顺序执行。因此,限定仅由权利要求实施,而非由附图或本说明书实施。
忆阻器制造遭受在小尺寸下的相对低产率及大可变性。这不利地影响这些设备的制造的扩展性和可控性。
图1和图2示出包括沟道区101及容纳区103的忆阻器,沟道区101具有可变浓度的移动离子,容纳区103具有化学计量晶体材料、容纳沟道区并且与沟道区处于热平衡。在此示例中,沟道区101被示出为大体圆柱形的形状,并且容纳区103被示出为大体矩形。然而,如将在此讨论的,这些形状不是关键的。
“热平衡”意味着沟道区和容纳区相对于彼此是热力学稳定的。换句话说,即使在升高的温度下,它们也不与彼此发生化学反应。
沟道区可以由作为忆阻器系统中的导电沟道工作的任意材料形成。沟道区可以包括芯以及梯度区。在一些示例中,沟道区包括双稳金属氧化物固溶体(bistablemetal-oxide solid solution)和非晶氧化物相(amorphous oxide phase)。
容纳区可以由与沟道区处于热平衡的任意绝缘相组成。
在包括钽的忆阻器的示例中,沟道区101包括Ta(O)金属氧化物固溶体以及非晶氧化物TaOx,并且容纳区包括化学计量晶体Ta2O5。可以使用其它材料系统。由铪制造的忆阻器的示例包括具有Hf(O)金属氧化物固溶体和非晶氧化物HfOx的沟道区,以及与沟道区处于热平衡的具有化学计量晶体HfO2的容纳区。
图3示出具有导电区301和容纳区303的忆阻器的另一示例,容纳区303包围沟道区301且与沟道区301处于热平衡。忆阻器被制造在基板305上。绝缘层307与基板相邻,第一接触区309与绝缘层相邻。第二接触区311与第一接触区309间隔开,并且容纳区303被设置在接触区之间。在一些示例中,可以比其它组件更薄的贴附层313被设置在绝缘层307和第一接触区309之间。
在一些示例中,基板305包括硅,绝缘层307包括二氧化硅。第一接触区309可以包括铂,第二接触区311可以包括钽。如果使用贴附层313,则其可以包括钛。
尺寸不是关键的,且可以被选择为适合于制造中设备。在一个示例中,忆阻器约100微米宽。接触区各自约100至400纳米厚,容纳区和沟道区介于小于7纳米至约18纳米厚之间,绝缘层约200纳米厚,并且贴附层(如果使用)约一个纳米厚。
图4示出说明忆阻器的活动(例如具有沟道区以及与沟道区处于热平衡的容纳区的忆阻器的活动)的电流VS电压的图。
图5示出交叉忆阻器结构的示例,其中多个第一接触区501彼此间隔开且彼此大体地平行,并且多个第二接触区503彼此间隔开且彼此大体地平行。第二接触区大体地以直角覆盖在第一接触区上。具有包围沟道区507的容纳区505的忆阻器形成在第一接触区和第二接触区的交叉位置—即在第二接触区中的一个跨过第一接触区中的一个的地方。位于这种交叉位置的单独的忆阻器可以通过对限定交叉位置的那些接触区施加适当的控制电压或电流来访问。
如上所述,图中描绘的示例的形状不是关键的。容纳区不需要是矩形的,并且沟道区不需要是圆形的。图6示出具有包围圆柱形沟道区603的容纳区601的示例。圆柱形沟道区603具有中空的内部605。为方便,可以使用容纳区、沟道区或者容纳区和沟道区的其它形状。
图7中示出制造具有与容纳区处于热平衡的沟道区的忆阻器的方法的示例。该方法包括:在支撑结构上沉积第一接触区(701),在第一接触区上沉积容纳区(703),在容纳区上沉积第二接触区(705),以及形成在接触区之间的且与容纳区处于热平衡的沟道区(707)。在一些示例中,形成沟道区包括跨接触区施加电势,以产生穿过容纳区的电场。在其它示例中,形成沟道区包括使容纳区暴露于电子束或离子束,或对容纳区进行真空退火,或去除粗糙工艺。在一些示例中,形成沟道区包括在容纳区中注入杂质(沟道种子)。
具有受容纳区保护的、与容纳区处于热平衡的沟道区的忆阻器,提供提高的扩展性、耐久性以及可控性。与用其它技术制造的现有忆阻器相比,这样的忆阻器将更好地实现大大改进的存储器系统的潜力。

Claims (15)

1.一种具有与容纳区处于热平衡的沟道区的忆阻器,所述忆阻器包括:
沟道区,具有可变浓度的移动离子;以及
具有化学计量晶体材料的容纳区,容纳所述沟道区且与所述沟道区处于热平衡。
2.根据权利要求1所述的忆阻器,其中所述沟道区包括芯和梯度区。
3.根据权利要求2所述的忆阻器,其中所述沟道区包括双稳金属氧化物固溶体和非晶氧化物相。
4.根据权利要求3所述的忆阻器,其中所述沟道区包括Ta(O)和TaOx,所述容纳区包括Ta2O5
5.根据权利要求3所述的忆阻器,其中所述沟道区包括Hf(O)和HfOx,所述容纳区包括HfO2
6.一种具有与容纳区处于热平衡的沟道区的忆阻器,所述忆阻器包括:
基板;
绝缘层,与所述基板相邻;
第一接触区,与所述绝缘层相邻;
第二接触区,与所述第一接触区间隔开;
容纳区,被设置在接触区之间;以及
沟道区,由所述容纳区、所述第一接触区以及所述第二接触区包围,所述沟道区具有可变浓度的移动离子且与所述容纳区处于热平衡。
7.根据权利要求6所述的忆阻器,其中所述沟道区包括芯和梯度区。
8.根据权利要求7所述的忆阻器,其中所述沟道区包括金属氧化物固溶体和非晶氧化物相。
9.根据权利要求8所述的忆阻器,其中所述沟道区包括Ta(O)和TaOx,所述容纳区包括Ta2O5
10.根据权利要求9所述的忆阻器,其中所述沟道区包括Hf(O)和HfOx,所述容纳区包括HfO2
11.根据权利要求6所述的忆阻器,进一步包括位于所述绝缘层与所述第一接触区之间的贴附层。
12.一种制造忆阻器的方法,所述方法包括:
在支撑结构上沉积第一接触区;
在所述第一接触区上沉积容纳区;
在所述容纳区上沉积第二接触区;以及
形成在接触区之间的且与所述容纳区处于热平衡的沟道区。
13.根据权利要求12所述的方法,其中形成沟道区包括跨接触区施加电势,以产生穿过所述容纳区的电场。
14.根据权利要求12所述的方法,其中形成沟道区包括使所述容纳区暴露于离子束和电子束中的一个。
15.根据权利要求12所述的方法,其中形成沟道区包括对所述容纳区进行真空退火。
CN201280065140.6A 2012-02-29 2012-02-29 具有与容纳区处于热平衡的沟道区的忆阻器 Pending CN104011863A (zh)

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CN103733338A (zh) * 2011-06-24 2014-04-16 惠普发展公司,有限责任合伙企业 高可靠性高速忆阻器

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