CN103995387B - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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CN103995387B
CN103995387B CN201410208869.5A CN201410208869A CN103995387B CN 103995387 B CN103995387 B CN 103995387B CN 201410208869 A CN201410208869 A CN 201410208869A CN 103995387 B CN103995387 B CN 103995387B
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永山和由
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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Abstract

本发明涉及显示技术领域，公开了一种阵列基板，包括形成在衬底基板上的栅线、数据线及两者交叉形成的若干像素单元，每个像素单元包括薄膜晶体管，离阵列基板的栅极驱动一侧越远，薄膜晶体管的有源层与薄膜晶体管的源极重叠面积呈增大的趋势。本发明通过改变有源层与源极重叠区域的大小，增大栅极和源极之间的介电系数，从而增大栅源电容Cgs，Cgs增大导致ΔVp增大，这样使得公共电极电压趋于稳定，避免了显示时发生的串扰。

Description

阵列基板及显示装置
技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及显示装置。
背景技术
由于显示面板尺寸的原因，不同位置栅极延迟(Gate delay，也称RC delay)的不同，因此公共电极电压Vcom在不同位置也是不同的。如图1所示，栅线离栅极驱动(图中Y PCB)越远，栅极延迟越大，第②点的公共电极电压Vcom大于第①点的Vcom，即离栅极驱动越远，公共电极电压Vcom会呈增大的趋势。因此对于每个像素，公共电极电压Vcom不是稳定的，这在显示时会导致串扰。实际上，Vcom＝V－ΔVp，其中，ΔVp为由于栅线关断引起的像素电压Vp的跳变电压，V为实际输入的公共电压，可见可以增大ΔVp来达到使公共电极电压Vcom趋于稳定的目的。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是：如何增大ΔVp，以使公共电极电压Vcom趋于稳定。
(二)技术方案
为解决上述技术问题，本发明提供了一种阵列基板，包括形成在衬底基板上的栅线、数据线及两者交叉形成的若干像素单元，每个像素单元包括薄膜晶体管，离阵列基板的栅极驱动一侧越远，薄膜晶体管的有源层与薄膜晶体管的源极重叠面积呈增大的趋势。
其中，按列将像素单元分成n组，1＜n≤N，N为总列数，靠近阵列基板的栅极驱动一侧的第一列像素起，第i+1组像素单元的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积比第i组像素单元的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积大ΔSi，1≤i≤n－1，同组中的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积相同。
其中，每组像素单元的列数相等。
其中，离阵列基板的栅极驱动一侧越远，所述薄膜晶体管的有源层与漏极重叠面积呈减小的趋势。
其中，按列将像素单元分成m组，1＜m≤N，N为总列数，靠近阵列基板的栅极驱动一侧的第一列像素起，第j+1组像素单元的薄膜晶体管的有源层与数据线重叠面积比第j组像素单元的薄膜晶体管的有源层与数据线重叠面积小ΔSj，1≤j≤m－1，同组中的薄膜晶体管的有源层与数据线重叠面积相同。
其中，每组像素单元的列数相等。
其中，m＝n。
其中，ΔSi＝ΔSj。
其中，所述有源层材料为氧化物半导体。
本发明还提供了一种显示装置，包括上述任一项所述的阵列基板。
(三)有益效果
本发明通过改变有源层与源极重叠区域的大小，增大栅极和源极之间的介电系数，从而增大栅源电容Cgs，Cgs增大导致ΔVp增大，这样使得公共电极电压趋于稳定，避免了显示时发生的串扰。
附图说明
图1是Vcom在显示面板不同位置的曲线图；
图2是本发明实施例的一种阵列基板(只示出了同一行不同位置的两个像素的简单结构)结构示意图；
图3是阵列基板中一个像素结构的等效电路图；
图4是本发明实施例的另一种阵列基板结构示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
本发明实施例的阵列基板，包括形成在衬底基板上的栅线210、数据线220及两者交叉形成的若干像素单元，每个像素单元包括薄膜晶体管。为了使公共电极电压Vcom趋于稳定，如图2所示，离阵列基板的栅极驱动一侧越远，薄膜晶体管的有源层230与薄膜晶体管的源极240重叠面积呈增大的趋势。
ΔVp由于馈入特性(馈入即产生ΔVp的过程，是显示器中由Gate电压的跳变引起的)的原因，会较理论值有比较大的偏移，而引起这一波动最大的影响因素就是栅源电容Cgs，Cgs对ΔVp的影响如图3及以下公式(1)所示，故控制Cgs电压对维持ΔVp的稳定有很重要的影响。而众所周知，Cgs的产生是由Gate层和源极层交叠引起。由公式C＝εS/d，其中S是平行板正对面积，ε是介质的介电系数，d是平行板间的距离，本实施例通过改变ε的大小来控制电容的大小。
ΔVp = C gs C all ( V gh - V gl ) - - - ( 1 )
其中，Call为图3中电路的电容总和(即等效电容)，Vgh和Vgl分别为栅极的高低电平电压。由于离阵列基板的栅极驱动一侧越远，薄膜晶体管的有源层与薄膜晶体管的源极重叠面积呈增大的趋势，有源层通常为半导体材料(如：氧化物半导体，栅极和源极之间通常间隔有栅绝缘层和有源层，氧化物有源层的介电系数大于栅绝缘层的介电系数)，所以栅极和源极之间的介电材料的平均介电系数ε会增大，Cgs增大，从而使得ΔVp增大。即离阵列基板的栅极驱动一侧越远，像素的ΔVp呈增大的趋势，因此根据Vcom＝V－ΔVp，ΔVp增大导致离阵列基板的栅极驱动一侧越远处的公共电极电压Vcom成减小的趋势，使图1中公共电极电压离阵列基板的栅极驱动一侧越远处呈增大趋势的现象得到改善，即通过改善ΔVp使图1中的Vcom曲线趋于水平，可以使Vcom趋于稳定。
为了方便阵列基板的制作和布局，按列将像素单元分成n组，1＜n≤N，N为总列数，靠近阵列基板的栅极驱动一侧的第一列像素起，第i+1组像素单元的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积比第i组像素单元的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积大ΔSi，1≤i≤n－1，同组中的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积相同。优选地，每组像素单元的列数相等。
进一步地，如图4所示，有源层230右端(和源极240重叠的一端)增大的同时通过减小有源层230的左端(和漏极重叠的一端，图2中漏极和数据线220一体设计)与漏极的重叠面积的大小来改变电容，由于，栅极和漏极之间的有源层面积减小，相对于之间的介电系数ε减小，从而栅极和漏极之间电容减小，使得上述公式(1)中的Call减小，ΔVp增大。
同理，为了方便阵列基板的制作和布局，按列将像素单元分成m组，1＜m≤N，N为总列数，靠近阵列基板的栅极驱动一侧的第一列像素起，第j+1组像素单元的薄膜晶体管的有源层与数据线重叠面积比第j组像素单元的薄膜晶体管的有源层与数据线重叠面积小ΔSj，1≤j≤m－1，同组中的薄膜晶体管的有源层与数据线重叠面积相同。优选地，每组像素单元的列数相等，且使得m＝n。
有源层右端增大与源极的重叠面积的同时有源层左端减小与漏极重叠面积，可以理解为相对于现有技术，有源层整个向右发生位移，即在制作时保证有源层大小不变，使其向右移动一段距离即可，此时，在m＝n，i＝j的情况下，ΔSi＝ΔSj。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (9)

1.一种阵列基板，包括形成在衬底基板上的栅线、数据线及两者交叉形成的若干像素单元，每个像素单元包括薄膜晶体管，其特征在于，离阵列基板的栅极驱动一侧越远，薄膜晶体管的有源层与薄膜晶体管的源极重叠面积呈增大的趋势，按列将像素单元分成n组，1＜n≤N，N为总列数，靠近阵列基板的栅极驱动一侧的第一列像素起，第i+1组像素单元的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积比第i组像素单元的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积大ΔSi，1≤i≤n－1，同组中的薄膜晶体管的有源层与薄膜晶体管的源极重叠面积相同。
2.如权利要求1所述的阵列基板，其特征在于，每组像素单元的列数相等。
3.如权利要求2所述的阵列基板，其特征在于，离阵列基板的栅极驱动一侧越远，所述薄膜晶体管的有源层与漏极重叠面积呈减小的趋势。
4.如权利要求3所述的阵列基板，其特征在于，按列将像素单元分成m组，1＜m≤N，N为总列数，靠近阵列基板的栅极驱动一侧的第一列像素起，第j+1组像素单元的薄膜晶体管的有源层与数据线重叠面积比第j组像素单元的薄膜晶体管的有源层与数据线重叠面积小ΔSj，1≤j≤m－1，同组中的薄膜晶体管的有源层与数据线重叠面积相同。
5.如权利要求4所述的阵列基板，其特征在于，每组像素单元的列数相等。
6.如权利要求4所述的阵列基板，其特征在于，m＝n。
7.如权利要求6所述的阵列基板，其特征在于，当i＝j时，ΔSi＝ΔSj。
8.如权利要求1～7中任一项所述的阵列基板，其特征在于，所述有源层材料为氧化物半导体。
9.一种显示装置，其特征在于，包括如权利要求1～8中任一项所述的阵列基板。
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CN103995387B (zh) * 2014-05-16 2015-05-13 京东方科技集团股份有限公司 阵列基板及显示装置
CN107577098A (zh) * 2017-09-22 2018-01-12 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
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