CN103974539B - 集成电路贴片及其制造方法 - Google Patents

集成电路贴片及其制造方法 Download PDF

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Publication number
CN103974539B
CN103974539B CN201310355909.4A CN201310355909A CN103974539B CN 103974539 B CN103974539 B CN 103974539B CN 201310355909 A CN201310355909 A CN 201310355909A CN 103974539 B CN103974539 B CN 103974539B
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connection pad
semiconductor device
group
circuit board
paster
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CN103974539A (zh
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林进生
郭政嘉
林志成
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Mxtran Inc
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Mxtran Inc
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • G06K19/0727—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs the arrangement being a circuit facilitating integration of the record carrier with a hand-held device such as a smart phone of PDA
    • G—PHYSICS
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    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
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    • G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
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    • G06K7/10237—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves the reader and the record carrier being capable of selectively switching between reader and record carrier appearance, e.g. in near field communication [NFC] devices where the NFC device may function as an RFID reader or as an RFID tag
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Abstract

本发明公开了一种集成电路贴片及其制造方法。集成电路贴片包括：一电路板，具有一电路路线；一第一组接垫，设置在电路板的一第一表面上并被设计成适用于ISO7816标准；以及一半导体装置，配置于电路板上用以与第一组接垫的至少一个通讯。第一组接垫是被排列成两列，且半导体装置是配置于电路板上位于两列的接垫之间的一空间中。

Description

集成电路贴片及其制造方法
技术领域
本发明大致上是有关于一种集成电路贴片及其制造方法，且特别是有关于一种用以被装设在一智能卡上的集成电路贴片及其制造方法。
背景技术
移动通讯装置广泛被人们使用在日常生活中。利用移动通讯装置作为用以执行商业交易的工具将来是一种趋势。通过移动电话达到商业交易功能有两个主要方法。一种是通过从移动电话的因特网软件银行下载相关软件，而另一种是通过应用一个具有一对应功能的SIM(用户识别模块)卡。
这两种方法对使用者而言都是不方便的。
发明内容
本发明是有关于一种集成电路贴片及其制造方法。依据本发明的一个实施例的集成电路贴片的厚度不大于300μm并可被装设在一智能卡上。集成电路贴片具有一个半导体装置及一电路板；电路板可以与半导体装置与智能卡电性连接。
根据本发明的第一方面，提出一种集成电路贴片。集成电路贴片包括：一电路板，其具有一电路路线(circuit route)；一第一组接垫，设置在电路板的一第一表面上并被设计成适用于ISO7816标准；以及一个半导体装置，配置于电路板上，用以与第一组接垫的至少一个通讯。第一组接垫排列成两列，且半导体装置配置于电路板上位于两列的接垫之间的一空间中。
根据本发明的第二方面，提出一种集成电路贴片的制造方法。此方法包括下述步骤：提供一具有一电路路线的电路板；形成一第一组接垫，设置在电路板的一第一表面并被设计成适用于ISO7816标准；以及将一个半导体装置配置在电路板上，用以与第一组接垫的至少一个通讯。第一组接垫排列成两列，且半导体装置是配置于电路板上位于两列的接垫之间的一空间中。
本发明的上述及其他实施样态将关于下述较佳但非限制实施例的详细说明而变得更佳理解。以下参考附图作出下述说明。
附图说明
图1A通过显示一第一表面绘示依据本发明的一实施例的一集成电路贴片。
图1B绘示集成电路贴片，其通过显示其的一第二表面来绘示。
图2A与图2B分别从两个不同侧显示集成电路贴片与SIM卡。
图3A至图3D显示一种利用一COF封装技术将半导体装置107配置在电路板103上的方法。
图4A与图4B显示集成电路贴片及一标准SIM卡的连接。
图5显示将装设有标准SIM卡的集成电路贴片配置在一通讯装置的一卡插槽中。
图6A至图6F显示一种利用一种WLCSP封装技术将半导体装置107配置在电路板103上的方法。
图7A与图7B显示供具有8个接点之Micro-SIM卡用的一集成电路贴片的一个例子。
图8A与图8B显示供具有6个接点之Micro/Nano SIM卡用的一集成电路贴片的一个例子。
图9A与图9B分别从两个不同侧显示集成电路贴片与Micro/NanoSIM卡。
图10A与图10B分别从两个不同侧显示一集成电路贴片与Nano-SIM卡。
【符号说明】
C6：接垫
H1：厚度
H2：厚度
10：晶片
50：晶片
100A：接垫
101：集成电路贴片
102：信号接垫
102a：接垫
103：电路板
103A：第一表面
103B：第二表面
104：凸块
105：第一组接垫
106：导电胶
107：半导体装置
108：绝缘层
109：电路路线
111：第二组接垫
200：标准SIM卡
220a：外轮廓
220b：内轮廓
240：移动电话
501：绝缘层
502a：接垫
503：重新分配层(RDL)
504：凸块
506：填胶层
701：集成电路贴片
801：集成电路贴片
802b：第二组接垫
900：Micro/Nano SIM卡
902：信号接垫
1000：Nano-SIM卡
1001：集成电路贴片
1002：信号接垫
1002b：第二组接垫
2402：卡插槽
具体实施方式
图1A通过显示一第一表面103A绘示依据本发明的一实施例的一集成电路贴片101。集成电路贴片101包括一电路板103(譬如一软性电路板)、一第一组接垫105以及一个半导体装置107。电路板103具有一电路路线109。第一组接垫105是被设置在电路板103的第一表面103A上并被设计成用以适用于ISO7816标准。半导体装置107是配置于电路板103上，用以与第一组接垫105的至少一个通讯。第一组接垫105排列成两列，且半导体装置107配置于电路板103上位在接垫105的两列之间的一空间中。
ISO7816标准为一种关于具有多个接点的电子识别卡(特别是智能卡)的国际标准，其由国际标准化组织(International Organization for Standardization，ISO)与国际电工委员会(International Electrotechnical Commission，IEC)联合管理。当集成电路贴片101与智能卡一起被使用在一电子装置时，具有上述半导体装置107的集成电路贴片101可改善智能卡的功能。电子装置譬如是一通讯装置，而智能卡为一用户识别模块(subscriber-identity-module，SIM)卡。
图1B绘示集成电路贴片101，其通过显示其的一第二表面103B来绘示。集成电路贴片101更包括一第二组接垫111，其被设置在电路板103的第二表面103B上并具有与半导体装置107与第一组接垫105的任何一个连接的至少一接垫。半导体装置107与第一组接垫105中的何者连接至第二组接垫111的至少一接垫，是由集成电路贴片101的功能或应用所决定。
虽然所显示的半导体装置107是配置于图1A的电路板的第一表面103A中，基于集成电路贴片101的功能或应用半导体装置107亦可配置于第二表面103B。第一组接垫105譬如是用来与通讯装置接触，而第二组接垫111是用来与SIM卡接触。
再者，半导体装置107可在单线连接协议(SWP)通讯协议之下，与通讯装置与SIM卡的任何一个通讯。半导体装置107可以与第一组接垫105的至少一个及第二组接垫111的至少一个连接，与半导体装置107可包括一供近场通讯(NFC)功能用的控制器。上述第一组接垫105的至少一个譬如是在ISO7816标准之下被命名为C6的接垫。第一组接垫105的接垫C6是用以在SWP通讯协议之下进行通讯。
图2A与图2B分别从两个不同侧显示集成电路贴片101与SIM卡200。SIM卡200譬如是标准SIM卡200(标准尺寸)。供一标准SIM卡200用的集成电路贴片101具有大约24.5mm的长度及大约14.5mm的宽度。因此，集成电路贴片101可具有不大于24.5mm的长度，不大于14.5mm的宽度以及不大于0.3mm的厚度。
请参考图2A及图2B，当集成电路贴片101装设至标准SIM卡200时，配置在第二表面103B上的第二组接垫111是用以与标准SIM卡200的信号接垫102电性连接。集成电路贴片101的第一表面103A是用以与通讯装置(未显示于图2A中)电性连接。
请参考图1A及图1B，一种集成电路贴片101的制造方法包括下述步骤。首先，提供具有电路路线109的电路板103。然后，形成设置在电路板103的第一表面103A上并被设计成适用于ISO7816标准的第一组接垫105。接着，将半导体装置107配置于电路板103上，用以与第一组接垫105的至少一个通讯。将第一组接垫105排列成两列，且将半导体装置107配置于电路板103上位于两列的接垫105之间的一空间中。
半导体装置107可利用一种COF(Chip-On-Film，贴片覆晶)封装技术而被配置于电路板103上。一种利用COF封装技术将半导体装置107配置在电路板103上的方法是显示于图3A至图3D中。首先，准备一晶片10，如图3A所示。晶片10可被分割成多个半导体装置107。半导体装置107包括至少一接垫100A，如图3B所示。接着，至少一凸块(bump)104是在半导体装置107的至少一接垫100A上形成。此至少一凸块104譬如是金凸块。半导体装置107的厚度不大于100μm。然后，准备具有至少一凸块104的半导体装置107以与电路板103整合。
集成电路贴片101包括至少一接垫102a，用以与半导体装置107连接(第一组接垫105未显示于图3B～图3D，及图4A与图4B中)。至少一接垫102a从第一表面103A突出，而第二组接垫111从第二表面103B突出。可使用第二组接垫111的其中一个来传送SWP信号以供近场通讯及/或RF非接触通讯用。
请参考图3C，将一导电胶(conductive adhesive)106配置在第一表面103A上，且利用导电胶106将至少一凸块104连接至电路板103。导电胶106可以是一异方性导电膜、一异方性导电膏或一异方性导电胶。
请参考图3D，一绝缘层108是形成于半导体装置107上，并覆盖半导体装置107、导电胶106与至少一接垫102a。绝缘层108可包括一环氧树脂。接着，形成集成电路贴片101。
集成电路贴片101的厚度H1不大于约300μm。半导体装置107的厚度不大于约200μm。
于一实施例中，绝缘层108覆盖半导体装置107的一上表面及一侧表面，且半导体装置107的上表面上的绝缘层108的厚度不大于50μm。
于一实施例中，第一组接垫105或第二组接垫111包括一凹坑形状部分或一隆起形状部分，与凹坑形状部分或隆起形状部分分别从第一表面103A或第二表面103B突出一段至少50μm的距离。
图4A与图4B显示集成电路贴片101及一标准SIM卡200的连接。当将集成电路贴片101装设至标准SIM卡200时，第二表面103B上的第二组接垫111是与标准SIM卡200电性连接。
图5显示将装设有标准SIM卡200的集成电路贴片101配置在一通讯装置(譬如一移动电话240)的一卡插槽2402中。因为集成电路贴片101具有不大于300μm的厚度，所以装设有标准SIM卡200的集成电路贴片101可被嵌合至移动电话240中。此外，因为集成电路贴片101具有配置在半导体装置107上用以保护半导体装置107的绝缘层108，所以可延长半导体装置107的寿命。
或者，依据本发明的另一实施例，亦可利用一WLCSP(Wafer Level Chip ScalePackage，晶片级芯片尺寸封装)封装技术将半导体装置107配置于电路板103上。一种利用WLCSP封装技术将半导体装置107配置在电路板103上的方法是显示于图6A至图6F中。于图6A中，准备一晶片50。晶片50可被分割成多个半导体装置107。如图6B所示，半导体装置107具有一重新分配层(redistribution layer，RDL)503、多个凸块504以及一绝缘层501。绝缘层501覆盖半导体装置107的上表面。绝缘层501可包括环氧树脂。RDL503系形成于半导体装置107的下表面上，而凸块504是形成于RDL503上。凸块504譬如是焊球。半导体装置107的厚度不大于150μm。
如图6C所示，电路板103包括多个接垫502a，用以与半导体装置107连接(第一组接垫105未显示于图6A至图6F中)。接垫502a是被配置在第一表面103A上并从第一表面103A突出。
请参考图6D，接垫502a是被接触至半导体装置107的凸块504，且接垫502a是通过表面黏着技术(surface mount technology，SMT)而电性连接至半导体装置107上的凸块504。
请参考图6E，一填胶层(underfill layer)506是形成于电路板103的第一表面103A上，用以覆盖半导体装置107是下表面。特别地，填胶层506系形成于电路板103的第一表面103A上，且在半导体装置107上是接垫502a与凸块504之间。RDL503是设于半导体装置107与电路板103之间，以与其连接，且RDL503是与半导体装置107一起封装。
然后，如图6F所示，集成电路贴片101是被形成并可被装设至一标准SIM200。半导体装置107的上表面上的绝缘层501的实质上的厚度是至少15μm且不大于20μm。集成电路贴片101的厚度H2不大于约300μm。半导体装置107的厚度不大于约200μm。
集成电路贴片101并未被限定成装设在一标准SIM卡上。集成电路贴片101的尺寸可被设计以匹配一SIM卡，其可以是SIM、USIM(Universal Subscriber Identity Module，万用用户识别模块)、UIM(User Identity Module，用户识别模块)、RUIM(Removable UserIdentity Module，可移除用户识别模块)、Micro-SIM以及Nano-SIM卡的其中一个。集成电路贴片101可被设计成匹配一标准尺寸、一Micro(微等级)尺寸以及一Nano(奈等级)尺寸SIM卡以符合不同的市场需求。集成电路贴片101的长宽比可被设计成对应至所选择的SIM卡的一长宽比。
基于上述，依据本发明的实施例的集成电路贴片具有不大于300μm的厚度且可被嵌合至大部分的SIM卡与通讯装置中。此外，因为集成电路贴片具有一配置在半导体装置上的绝缘层，用以保护半导体装置，所以可延长半导体装置的寿命。
图7A与图7B显示供具有8个接点的Micro-SIM卡用的一集成电路贴片701的一个例子。供一Micro-SIM卡用的集成电路贴片701具有大约15mm的长度及大约11.8mm的宽度。
图8A与图8B显示供具有6个接点的Micro/Nano SIM卡用的一集成电路贴片801的一个例子。图9A与图9B分别从两个不同侧显示集成电路贴片801与Micro/Nano SIM卡900。请参考图8A，集成电路贴片801的外轮廓220a是对应至一Micro-SIM卡并具有大约15mm的长度及大约11.8mm的宽度。集成电路贴片801的内轮廓220b是对应至一Nano-SIM卡并具有大约12.3mm的长度及大约8.8mm的宽度。集成电路贴片801与Micro/Nano SIM卡900可通过集成电路贴片801上的第二组接垫802b与Micro/Nano SIM卡900上的信号接垫902而被电性连接。
图10A与图10B分别从两个不同侧显示一集成电路贴片1001与Nano-SIM卡1000。集成电路贴片1001是被设计成用以与一Nano-SIM卡一起被使用。集成电路贴片1001与Nano-SIM卡1000可通过集成电路贴片1001上的第二组接垫1002b与Nano-SIM卡1000上的信号接垫1002而被电性连接。
将装设有一SIM卡的集成电路贴片701、集成电路贴片801与集成电路贴片1001配置在一通讯装置的一卡插槽中的方法是类似于图5所显示者。于此将不重述。集成电路贴片701(供Micro-SIM卡用)、集成电路贴片801(供Micro/Nano SIM卡用)，与集成电路贴片1001(供Nano-SIM卡用)可被选择以匹配待被装设在其上的一对应的Micro-SIM卡或Nano-SIM卡。
依据本发明的本实施例的集成电路贴片可以与通讯装置和SIM卡整合，并可被应用来达到商业交易功能。通过将集成电路贴片配置在通讯装置与SIM卡之间，通讯装置可在不需要修改任何软件的情况下具有额外功能，例如一信息安全功能。因此，依据本发明的本实施例的集成电路贴片可以在不需要考虑电信营运商、通讯装置的型式或SIM卡的型式以及遵从市场需求的情况下，增加SIM卡与通讯装置之间的适应性。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视随附的权利要求范围所界定的为准。

Claims (14)

1.一种集成电路贴片，包括：
一电路板，具有一电路路线；
一第一组接垫，设置在该电路板的一第一表面上并被设计成适用于ISO 7816标准；
一第二组接垫，设置在该电路板的一第二表面上，并具有至少一接垫与一半导体装置及该第一组接垫的任何一个连接；以及
该半导体装置，配置于该电路板上，用以与该第一组接垫的至少一个通讯；
其中该第一组接垫和该第二组接垫是被排列成两列，该半导体装置是配置于该第一表面及该第二表面的任何一个上，且该半导体装置是配置于该电路板上位于该两列的接垫之间的一空间中，且该第一组接垫是用来与一通讯装置接触，而该第二组接垫是用来与一客户识别模块SIM卡接触，其中在一单线连接协议SWP通讯协议之下，该半导体装置与该通讯装置及该客户识别模块卡中的任何一个通讯。
2.根据权利要求1所述的贴片，其中该半导体装置包括至少一接垫并利用一贴片覆晶COF封装技术配置于该电路板上，于其中至少一凸块是在该半导体装置的该至少一接垫上形成以与该电路板连接，并利用一导电胶与该电路板连接。
3.根据权利要求1所述的贴片，其中该半导体装置是利用一晶片级芯片尺寸封装WLCSP封装技术而配置于该电路板上，于其中一重新分配层RDL是设于该半导体装置与该电路板之间以与其连接，且其中该RDL是与该半导体装置一起被封装，且该半导体装置是经由多个焊球而连接至该电路板。
4.根据权利要求1所述的贴片，其中该第一组接垫的该至少一个是在该ISO 7816标准之下被命名为C6的一接垫。
5.根据权利要求1所述的贴片，其中该半导体装置与该第一组接垫的至少一个及该第二组接垫的至少一个连接，并包括一个供近场通讯NFC功能用的控制器。
6.根据权利要求1所述的贴片，其中该集成电路贴片的厚度不大于300μm。
7.根据权利要求1所述的集成电路贴片，其中该SIM卡为普通SIM、万用用户识别模块USIM、用户识别模块UIM、可移除用户识别模块RUIM、Micro-SIM及Nano-SIM卡的其中一个。
8.一种集成电路贴片的制造方法，包括：
提供一具有一电路路线的电路板；
形成一第一组接垫，其被设置在该电路板的一第一表面上并被设计成适用于ISO 7816标准；
形成一第二组接垫，其被设置在该电路板的一第二表面上，其中该第二组接垫具有至少一接垫与一半导体装置及该第一组接垫的任何一个连接；以及
将该半导体装置配置在该电路板上，用以与该第一组接垫的至少一个通讯；
其中该第一组接垫和该第二组接垫是被排列成两列，该半导体装置是配置于该第一表面及该第二表面的任何一个上，且该半导体装置是配置于该电路板上位于在该两列的接垫之间的一空间中，且该第一组接垫是用来与一通讯装置接触，而该第二组接垫是用来与一SIM卡接触，在一SWP通讯协议之下，该半导体装置与该通讯装置及该SIM卡中的任何一个通讯。
9.根据权利要求8所述的方法，其中该半导体装置包括至少一接垫并利用一COF封装技术而配置于该电路板上，于其中至少一凸块是在该至少一接垫上形成以与该电路板连接，并利用一导电胶与该电路板连接。
10.根据权利要求8所述的方法，其中该半导体装置是利用一WLCSP封装技术而配置于该电路板上，于其中一RDL是设于该半导体装置与该电路板之间以与其连接，且其中该RDL是与该半导体装置一起被封装，且该半导体装置是经由多个焊球而连接至该电路板。
11.根据权利要求8所述的方法，其中该第一组接垫的该至少一个是在该ISO 7816标准之下被命名为C6的一接垫。
12.根据权利要求8所述的方法，其中该半导体装置与该第一组接垫的至少一个及该第二组接垫的至少一个连接，并包括一供NFC功能用的控制器。
13.根据权利要求8所述的方法，其中该集成电路贴片的厚度不大于300μm。
14.根据权利要求8所述的方法，其中该SIM卡为普通SIM、USIM、UIM、RUIM、Micro-SIM及Nano-SIM卡的其中一个。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI526940B (zh) * 2013-07-23 2016-03-21 The card structure of smart card and its manufacturing method
EP3168788A1 (en) * 2015-11-11 2017-05-17 Mastercard International Incorporated Integrated circuit card
DE102016110780A1 (de) * 2016-06-13 2017-12-14 Infineon Technologies Austria Ag Chipkartenmodul und Verfahren zum Herstellen eines Chipkartenmoduls
CN109948767A (zh) * 2018-02-01 2019-06-28 华为技术有限公司 存储卡和终端
TWI708533B (zh) * 2019-07-02 2020-10-21 華泰電子股份有限公司 半導體封裝件及其製法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326683B1 (en) * 1996-05-17 2001-12-04 Siemens Aktiengesellschaft Carrier element for a semiconductor chip
CN101894290A (zh) * 2010-04-06 2010-11-24 上海复旦微电子股份有限公司 非接触通信装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4007221A1 (de) * 1990-03-07 1991-09-12 Gao Ges Automation Org Pruefkopf fuer kontaktflaechen von wertkarten mit eingelagertem halbleiterchip
JP4298068B2 (ja) 1998-08-18 2009-07-15 セイコーエプソン株式会社 電気光学装置およびそれらを備えた電子機器並びに電気光学装置の製造方法
US7336973B2 (en) 2002-10-30 2008-02-26 Way Systems, Inc Mobile communication device equipped with a magnetic stripe reader
JP5078915B2 (ja) 2006-02-17 2012-11-21 ケーティーフリーテル・カンパニー・リミテッド Ｉｃカード、ｉｃカードが搭載された端末機及びその初期化方法
US20080099559A1 (en) * 2006-10-31 2008-05-01 Macronix International Co., Ltd. Dual Interface SIM Card Adapter with Detachable Antenna
FR2923633B1 (fr) 2007-11-13 2010-06-18 Oberthur Card Syst Sa Carte a microprocesseur, telephone comprenant une telle carte et procede d'execution d'une commande dans une telle carte.
KR20100106363A (ko) 2007-12-10 2010-10-01 르네사스 일렉트로닉스 가부시키가이샤 Ｓｉｍ 어댑터 및 ｓｉｍ 카드
TWM366130U (en) * 2009-05-27 2009-10-01 Phytrex Technology Corp Dual-chip signal converter
WO2011011901A1 (en) 2009-07-31 2011-02-03 Gemalto Sa Contactless adaptor device
TWM416148U (en) 2010-08-12 2011-11-11 Mxtran Inc Integrated circuit film for smart card and mobile communication device
US8644025B2 (en) 2009-12-22 2014-02-04 Mxtran Inc. Integrated circuit film for smart card
US8355670B2 (en) 2010-06-22 2013-01-15 At&T Mobility Ii Llc Near field communication adapters
CN102063635B (zh) 2010-10-15 2013-01-23 武汉天喻信息产业股份有限公司 多接口移动支付智能卡及其控制方法
FR2968430B1 (fr) 2010-12-07 2014-09-05 Oberthur Technologies Adaptateur nfc pour carte a microcircuit, par exemple pour carte de telephonie
EP2472730A1 (en) 2010-12-28 2012-07-04 Gemalto SA Contactless adaptor device
TWM427626U (en) 2011-05-20 2012-04-21 Mxtran Inc Smart card and integrated circuit film for smart card
TWM425346U (en) * 2011-05-20 2012-03-21 Mxtran Inc Integrated circuit film for smart card and mobile communication device
US9077571B2 (en) 2011-09-09 2015-07-07 Nxp B.V. Adaptive equalizer and/or antenna tuning
CN103379732A (zh) * 2012-04-13 2013-10-30 鸿富锦精密工业（深圳）有限公司 焊盘加固印刷电路板

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326683B1 (en) * 1996-05-17 2001-12-04 Siemens Aktiengesellschaft Carrier element for a semiconductor chip
CN101894290A (zh) * 2010-04-06 2010-11-24 上海复旦微电子股份有限公司 非接触通信装置

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