CN103972161B - SiCoNi etching method for through-silicon-via morphology correction - Google Patents
SiCoNi etching method for through-silicon-via morphology correction Download PDFInfo
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- CN103972161B CN103972161B CN201410192806.5A CN201410192806A CN103972161B CN 103972161 B CN103972161 B CN 103972161B CN 201410192806 A CN201410192806 A CN 201410192806A CN 103972161 B CN103972161 B CN 103972161B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Abstract
The invention provides a SiCoNi etching method for through-silicon-via morphology correction. After a through hole with a silicon dioxide insulating layer formed on the side wall is formed in a semiconductor substrate of a wafer in a Bosch etching mode, the following steps are sequentially executed: (1) an etching agent is generated in a reaction cavity, wherein the semiconductor substrate is arranged on the initial etching position in the reaction cavity; (2) etching is conducted on the silicon dioxide insulating layer formed at the side wall of the through hole by using the generated etching agent in the reaction cavity; (3) the wafer is made to enter the heating position in the reaction cavity; (4) the wafer is heated at the temperature above 100 DEG C so as to conduct annealing treatment on the wafer; (5) gas in the reaction cavity is removed after annealing processing is conducted; (6) plasma treatment is conducted on the wafer by using oxygen; (7) the wafer returns to the initial etching position in the reaction cavity.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of be used for silicon hole pattern amendment
SiCoNi engraving methods.
Background technology
With the raising of the integrated level of integrated circuit, using Modern Electronic Packaging Technology realize it is highdensity it is integrated (including
2.5D, 3D integrated technology), as the important technology approach that IC system level is integrated.In numerous encapsulation technologies, silicon hole
Focus of (Through-Silicon-Via, the TSV) technology as research at present, many advantages of TSV technology, for example：Interconnection length
Logic module equal with chip thickness, to be distributed using the logic module substitution level of vertical stacking can be shortened to；Significantly
Reduce RC retardation ratio and inductive effect etc..TSV technology includes following critical process：Semiconductor substrate, the semiconductor lining are provided
Basal surface could be formed with chip；Through hole is formed in the Semiconductor substrate, the technique of the formation through hole is plasma quarter
Etching technique；Insulating barrier is formed in the side wall of the through hole；In side, wall is formed with the through hole deposit diffusion barriers of insulating barrier；In side
Wall is formed with insulating barrier and the through hole of diffusion impervious layer inserts conductive materials；The thinning Semiconductor substrate simultaneously carries out correspondence heap
It is folded.
The most key in TSV technology is etching, the i.e. formation of TSV through hole.Semi-conductor silicon chip substrate is generally very thick
(700um or so), the conventional technology of current industry is the assorted etching technics of ripple (Bosch process), and the assorted etching of ripple can be formed
The at a relatively high vertical through hole of depth-to-width ratio.But, due to alternately using two steps containing different plasma in technical process
Perform etching, therefore the through-hole side wall for being formed is rough, it is rough and uneven in surface, it is similar to wave, also referred to as scallop pattern
(scalloping or roughness) 100, as shown in Figure 1.This will cause the follow-up insulating barrier formed in through-hole side wall
Technique is extremely difficult.In addition, can also be to the conformal covering band of subsequent oxidation silicon insulating barrier, copper barrier layer and copper seed layer
Come difficult.And then the property of interconnections of the whole TSV of influence, so that whole component failure.
SiCoNi etching techniques are generally used for the prerinse before metal deposit, and its effect is the silica for removing surface, drop
Low contact resistance.Maximum the characteristics of be SiO2/Si etching selection ratio it is very high (>20：1).The wafer substrate of SiCoNi reaction chambers
(Pedestal) general temperature is maintained at 35 DEG C or so, and displaying head (Showerhead) above wafer has heating function, temperature
Degree is maintained at 180C or so.The course of reaction of SiCoNi etching processes can be sketched as three etching agents of key step 1. are formed；
2. etched under low temperature (etch by-products for being formed are solid-state, can be covered in surface barrier and further etch)；3. vaporization at high temperature
Removal etch by-products.
But, because SiCoNi etching techniques are very low to the etch rate of silicon, cannot be used directly for TSV through hole side wall
Etching.
The content of the invention
The technical problems to be solved by the invention are directed to and there is drawbacks described above in the prior art, there is provided a kind of logical for silicon
The SiCoNi engraving methods of hole pattern amendment, can eliminate or reduce the scallop knot that the assorted etching technics of ripple is formed in TSV through hole
Structure, obtains smooth through-silicon via sidewall.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided a kind of SiCoNi for silicon hole pattern amendment
Engraving method, wherein being formed with silicon dioxide insulator side wall is formed in the Semiconductor substrate of wafer by the assorted etching mode of ripple
Following step is performed successively after the through hole of layer：First step, for producing etching agent, wherein Semiconductor substrate in the reactor chamber
Arrangement etching initial position in the reactor chamber；Second step, for the etching agent produced by utilization in the reactor chamber to through hole
The silicon dioxide insulating layer that side wall is formed is performed etching；Third step, for the heating location for wafer is entered in reaction chamber；
Four steps, for performing annealing process with to wafer to wafer heating at a temperature of more than 100 DEG C；
5th step, for taking the gas in reaction chamber away after an anneal process；6th step, for utilizing oxygen pair
Wafer performs plasma treatment；7th step, for the etching initial position for making wafer be back in reaction chamber.
Preferably, the semiconductor substrate surface is formed with chip.
Preferably, first step produces etching agent by following chemical reactions：
Preferably, second step is performed etching by chemical reaction：
NH4F+SiO2→(NH4)2SiF6(solid)+H2O or
NH4F.HF+SiO2→(NH4)2SiF6(solid)+H2O。
Preferably, four steps carries out annealing process by chemical reaction：
(NH4)2SiF6(solid)→SiF4(g)+NH3(g)+HF(g)。
Preferably, four steps performs annealing process to wafer heating at a temperature of 160-200 DEG C with to wafer.
Silicon can be gradually reduced or eliminate according to the SiCoNi engraving methods for silicon hole pattern amendment proposed by the present invention
Scallop structure on through-hole side wall, realizes the planarization of through-silicon via sidewall.Thus, it is used for silicon hole shape the invention provides one kind
The SiCoNi engraving methods of looks amendment, can eliminate or reduce the scallop structure that the assorted etching technics of ripple is formed in TSV through hole, obtain
To smooth through-silicon via sidewall.
Brief description of the drawings
With reference to accompanying drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 schematically shows the scallop pattern formed according to the silicon hole technique of prior art.
Fig. 2 schematically shows the SiCoNi etchings for silicon hole pattern amendment according to the preferred embodiment of the invention
The flow chart of method.
Fig. 3 is schematically shown according to invention preferred embodiment for silicon hole pattern amendment
The silicon hole pattern that SiCoNi engraving methods are obtained.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings to of the invention interior
Appearance is described in detail.
The present invention proposes a kind of SiCoNi engraving methods for silicon hole pattern amendment, increases in SiCoNi etch process
Oxygen plasma treatment step, forms the circulation of oxide etch-through-hole side wall oxidation-oxide etch, consumes repeatedly
The silicon atom of scallop body structure surface on through-hole side wall, obtains more smooth through-silicon via sidewall.It is exhausted that this is beneficial to subsequent oxidation silicon
The conformal covering of edge layer, copper barrier layer and copper seed layer, the final property of interconnections and product reliability for improving silicon hole.
Fig. 2 schematically shows the SiCoNi etchings for silicon hole pattern amendment according to the preferred embodiment of the invention
The flow chart of method.
SiCoNi engraving methods for silicon hole pattern amendment according to the preferred embodiment of the invention are included in by ripple
Assorted etching mode forms side wall in the Semiconductor substrate (semiconductor substrate surface could be formed with chip) of wafer and is formed
Have after the through hole of silicon dioxide insulating layer and perform following step successively：
First step S1, for producing etching agent, wherein Semiconductor substrate arrangement quarter in the reactor chamber in the reactor chamber
Erosion initial position；Etching agent for example can be produced by following chemical reactions：
Second step S2, the silica formed to through-hole side wall in the reactor chamber for the etching agent produced by utilization is exhausted
Edge layer is performed etching；Can for example be performed etching by chemical reaction：
NH4F+SiO2→(NH4)2SiF6(solid)+H2O or
NH4F.HF+SiO2→(NH4)2SiF6(solid)+H2O。
Third step S3, for the heating location for wafer is entered in reaction chamber；
Four steps S4, for heating wafer with to crystalline substance at the temperature (preferably, 160-200 DEG C) more than 100 DEG C
Circle performs annealing process；For example annealing process can be carried out by chemical reaction：
(NH4)2SiF6(solid)→SiF4(g)+NH3(g)+HF(g)。
5th step S5, for taking the gas in reaction chamber away after an anneal process；
6th step S6, for performing plasma treatment to wafer using oxygen；
7th step S7, the etching initial position that wafer can hereafter be back in reaction chamber.
As can be seen that technical method proposed by the present invention is, after vaporization at high temperature removal etch by-products, increase by a step
Oxygen gas plasma treatment, its effect is the scallop shape face for aoxidizing through-silicon via sidewall.The process can form 1-5nm or so
Thin layer of silicon oxide (time is more long, and thickness is thicker, but oxidation rate with thickness increases can be more and more slower).Then, wafer drop
Initial position is returned to, etching process is repeated.Such iterative cycles, can be gradually reduced the scallop structure on through-silicon via sidewall, directly
To the planarization of side wall.Fig. 3 shows the structural representation of silicon hole after oxidation.Due to scallop top in reacting gas contact angle more
Greatly, so either in oxidizing process or etching process, the Si consumption at top can all be more than scallop bottom.So often pass through
Once oxidation-etching process, scallop can all become smaller.That is side wall becomes more flat.
For example, a wafer for having formed silicon hole can be provided, wherein silicon hole is formed by the assorted etching mode of ripple.
For example, via depth is 100um, top diameter is 10um.In order to realize the planarization of TSV through hole side wall, can be general
SiCoNi etching processing procedures the inside increases an O2 plasma-treating technology step.The step is pumped it in gaseous byproduct
Afterwards, before wafer is reduced to initial position.For specific process parameter, for example, can be that oxygen flow is 1000-
10000sccm, gas pressure is 1-10Torr, and the time is 10-20S.In such a situa-tion, through-hole side wall surface will generate 2-
The thin layer of silicon oxide of 5nm, the silica at the top of scallop will be thicker, and then wafer rolls back low position, enter into next quarter
Erosion process.The height of usual scallop shape is 50nm or so.Each etches-aoxidizes flow and can reduce the scallop of 1-2nm highly.
If so to be wholly absent scallop shape, it is necessary to tens etching-oxidation cycles.Generally only need to be reduced to scallop shape
To a certain degree, it is possible to be set to the etching inside processing procedure-oxidation cycle number of times 20-30 times.
Furthermore, it is necessary to explanation, unless stated otherwise or points out, term " first " otherwise in specification, " the
Two ", description such as " 3rd " is used only for distinguishing each component, element, step in specification etc., without being intended to indicate that each
Logical relation or ordinal relation between component, element, step etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment and being not used to
Limit the present invention.For any those of ordinary skill in the art, technical solution of the present invention ambit is not being departed from
Under, many possible variations and modification, or modification are all made to technical solution of the present invention using the technology contents of the disclosure above
It is the Equivalent embodiments of equivalent variations.Therefore, every content without departing from technical solution of the present invention, according to technology reality of the invention
Verify any simple modification, equivalent variation and modification made for any of the above embodiments, still fall within technical solution of the present invention protection
In the range of.
Claims (6)
1. a kind of SiCoNi engraving methods for silicon hole pattern amendment, it is characterised in that by the assorted etching mode of ripple in crystalline substance
Formed in round Semiconductor substrate after side wall is formed with the through hole of silicon dioxide insulating layer and perform following step successively：
First step, for producing etching agent in the reactor chamber, wherein Semiconductor substrate arrangement etching in the reactor chamber is initial
Position；
Second step, enters to the silicon dioxide insulating layer that through-hole side wall is formed in the reactor chamber for the etching agent produced by utilization
Row etching；
Third step, for the heating location for wafer is entered in reaction chamber；
Four steps, for performing annealing process with to wafer to wafer heating at a temperature of more than 100 DEG C；
5th step, for taking the gas in reaction chamber away after an anneal process；
6th step, for performing plasma treatment to wafer using oxygen；
7th step, for the etching initial position for making wafer be back in reaction chamber, to repeat being circulated throughout for etching-oxidation
Journey, until through-hole side wall is planarized.
2. SiCoNi engraving methods for silicon hole pattern amendment according to claim 1, it is characterised in that described half
Conductor substrate surface is formed with chip.
3. SiCoNi engraving methods for silicon hole pattern amendment according to claim 1 and 2, it is characterised in that
One step produces etching agent by following chemical reactions：
4. SiCoNi engraving methods for silicon hole pattern amendment according to claim 1 and 2, it is characterised in that
Two steps are performed etching by chemical reaction：
NH4F+SiO2→(NH4)2SiF6(solid)+H2O or
NH4F.HF+SiO2→(NH4)2SiF6(solid)+H2O。
5. SiCoNi engraving methods for silicon hole pattern amendment according to claim 1 and 2, it is characterised in that
Four steps carries out annealing process by chemical reaction：
(NH4)2SiF6(solid)→SiF4(g)+NH3(g)+HF(g)。
6. SiCoNi engraving methods for silicon hole pattern amendment according to claim 1 and 2, it is characterised in that
Four steps performs annealing process to wafer heating at a temperature of 160-200 DEG C with to wafer.
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| CN201410192806.5A CN103972161B (en) | 2014-05-08 | 2014-05-08 | SiCoNi etching method for through-silicon-via morphology correction |
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| CN104269371B (en) * | 2014-09-01 | 2017-05-17 | 上海华力微电子有限公司 | Etching device and method |
| CN104992903B (en) * | 2015-07-30 | 2018-06-22 | 上海华力集成电路制造有限公司 | A kind of high quality gate oxide forming method |
| CN115692309A (en) * | 2021-07-26 | 2023-02-03 | 腾讯科技（深圳）有限公司 | Through silicon via structure, through silicon via interconnection structure, preparation method and electronic equipment |
| CN115881621A (en) * | 2023-01-10 | 2023-03-31 | 广州粤芯半导体技术有限公司 | Shallow trench isolation structure and preparation method thereof, semiconductor structure and chip |
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| CN102792426A (en) * | 2010-03-10 | 2012-11-21 | 应用材料公司 | Apparatus and methods for cyclical oxidation and etching |
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| US6846746B2 (en) * | 2002-05-01 | 2005-01-25 | Applied Materials, Inc. | Method of smoothing a trench sidewall after a deep trench silicon etch process |
| US8871650B2 (en) * | 2011-10-28 | 2014-10-28 | Applied Materials, Inc. | Post etch treatment (PET) of a low-K dielectric film |
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