CN106128996A - A kind of forming method of seamless polysilicon plug - Google Patents
A kind of forming method of seamless polysilicon plug Download PDFInfo
- Publication number
- CN106128996A CN106128996A CN201610475620.XA CN201610475620A CN106128996A CN 106128996 A CN106128996 A CN 106128996A CN 201610475620 A CN201610475620 A CN 201610475620A CN 106128996 A CN106128996 A CN 106128996A
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- Prior art keywords
- polysilicon plug
- oxide
- contact hole
- seamless
- forming method
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of seamless polysilicon plug, can be applicable in the preparation technology of 3D NAND structure, by forming the oxide layer with up big and down small tapered opening in the contact hole, and utilize oxide to be filled up completely with this tapered opening, make the polysilicon plug deposited later will not produce gap, and then improve threshold voltage and sub-threshold slope.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of seamless polysilicon plug (seam free
Poly plug) forming method.
Background technology
Storage element, with its small size, Large Copacity as starting point, is used three by three-dimensional data type memory technology (3D-NAND)
Dimensional pattern stacked in multi-layers highly integrated for design concept, produces high unit are memory density, efficient storage unit performance
Memorizer, have become as emerging memory design and produce prevailing technology.
At present, in the preparation technology of 3D NAND structure, as shown in figs. la-ld, initially with ald
The method of (Atomic Layer Deposition is called for short ALD) is full of oxide 5 in contact hole (channel hole) 4,
Next returns and carves (Recess etch back) this oxide 5, is exposed with the partial sidewall by this contact hole 4, afterwards in connecing
In contact hole 4, deposit polycrystalline silicon (poly) is to form polysilicon plug (poly plug) 6；Wherein, 1 be dielectric layer, 2 for sacrifice layer,
3 is sull.As shown in Fig. 2 a～2c, owing to the longitudinal section of contact hole 4 is typically bending (bowing profile),
This can cause producing in oxide 5 gap (seam), and dry etching removes (Dry etch recess) partial oxide 5
Technique can be aggravated (enhance) and be produced gap, and this can cause the polysilicon plug 6 deposited later to produce gap, and then affect threshold
Threshold voltage and sub-threshold slope, this is that those skilled in the art undesirably see.
Summary of the invention
For the problem of above-mentioned existence, the invention discloses the forming method of a kind of seamless polysilicon plug, including:
Step S1, it is provided that one is formed with the semiconductor structure of contact hole；
Step S2, forms the oxide covering described contact hole sidewall in described contact hole, and returns described oxide at quarter
To form oxide layer in described contact hole, and described oxide layer has the opening that Xray films is up big and down small；
Step S3, on described semiconductor structure, deposition oxide is to be full of described contact hole；
Step S4, returns the partial sidewall carving described oxide to expose described contact hole；
Step S5, continues on described semiconductor structure deposit polycrystalline silicon to form described polysilicon plug.
The forming method of above-mentioned seamless polysilicon plug, wherein, described method is applied to the preparation work of 3DNAND structure
In skill.
The forming method of above-mentioned seamless polysilicon plug, wherein, described step S2 includes:
Described oxide is deposited to be full of described contact hole on described semiconductor structure；
Etch described oxide to form the oxide layer of middle opening；
Continue the top of described oxide layer is performed etching technique, described in being formed, there is described up big and down small opening
Oxide layer, and bottom and the sidewall thereof of described contact hole all covered by described oxide layer.
The forming method of above-mentioned seamless polysilicon plug, wherein, in described step S2 and step S3, uses atomic layer deposition
Long-pending method deposition oxide on described semiconductor structure.
The forming method of above-mentioned seamless polysilicon plug, wherein, described etching technics is plasma etching industrial.
The forming method of above-mentioned seamless polysilicon plug, wherein, uses NH3 to carry out described plasma etching industrial.
The forming method of above-mentioned seamless polysilicon plug, wherein, described oxide is silicon dioxide.
The forming method of above-mentioned seamless polysilicon plug, wherein, the Xray films of described contact hole is bending.
The forming method of above-mentioned seamless polysilicon plug, wherein, in described step S4, uses dry etch process to return quarter
Described oxide is to expose the partial sidewall of described contact hole.
The forming method of above-mentioned seamless polysilicon plug, wherein, in described step S5, use chemical vapour deposition technique in
On described semiconductor structure, deposit polycrystalline silicon is to form described polysilicon plug.
Foregoing invention has the advantage that or beneficial effect:
The invention discloses the forming method of a kind of seamless polysilicon plug, can be applicable to the preparation technology of 3DNAND structure
In, by forming the oxide layer with up big and down small tapered opening in the contact hole, and utilize oxide to be filled up completely with this cone
Shape opening so that the polysilicon plug deposited later will not produce gap, and then improve threshold voltage (Vth) and subthreshold value is oblique
Rate (SS).
Accompanying drawing explanation
By the detailed description non-limiting example made with reference to the following drawings of reading, the present invention and feature thereof, outward
Shape and advantage will become more apparent.The part that labelling instruction identical in whole accompanying drawings is identical.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is illustrate the purport of the present invention.
Fig. 1 a～1d is the flowage structure schematic diagram of the forming method of polysilicon plug in conventional art of the present invention；
Fig. 2 a is the Electronic Speculum schematic diagram of Fig. 1 b；
Fig. 2 b is the Electronic Speculum schematic diagram of Fig. 1 c；
Fig. 2 c is the Electronic Speculum schematic diagram of Fig. 1 d；
Fig. 3 is the flow chart of the forming method of polysilicon plug in the embodiment of the present invention；
Fig. 4 a～4f is the flowage structure schematic diagram of the forming method of polysilicon plug in the embodiment of the present invention.
Fig. 5 a is the Electronic Speculum schematic diagram of Fig. 4 c；
Fig. 5 b is the Electronic Speculum schematic diagram of Fig. 4 d.
Detailed description of the invention
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
Fixed.
As it is shown on figure 3, the present embodiment relates to the forming method of a kind of seamless polysilicon plug, can be applicable to 3D NAND knot
In the preparation technology of structure, concrete, the method comprises the steps:
Step one, it is provided that one is formed with the semiconductor structure of contact hole 104, in an embodiment of the present invention, this contact hole
The Xray films of 104 is bending；Concrete, this semiconductor structure includes substrate (not shown), overlapping is arranged at lining
Dielectric layer 101 at the end and sacrifice layer 102, and this dielectric layer 101 and sacrifice layer 102 form stacked arrangement, is formed at heap
Sull 103 on stack structure and run through the contact hole 104 in this sull 103 to stacked structure；Enter one
Step, this semiconductor structure also includes other film layer, the emphasis improved due to this semiconductor structure non-invention, the most right
Its concrete film layer and preparation technology are not repeated；Structure as shown in fig. 4 a.
Step 2, forms oxide 105 (now oxide 105 shape covering contact hole 104 sidewall in contact hole 104
Become cover contact hole 104 sidewall side wall (spacer), and return carve oxide 105 with in contact hole 104 formed oxide layer, and
Oxide layer has the up big and down small opening of Xray films, and (such as this opening is up big and down small, tapered the opening of Xray films
Mouth (taper profile))；Structure as shown in Fig. 4 c and 5a.
In one preferred embodiment of the present invention, above-mentioned steps two specifically includes: first, uses the side of ald
Method on semiconductor structure deposition oxide 105 with full contact hole 104；Secondly etching oxide is to form middle opening
Oxide layer；Structure as shown in Figure 4 b；Continue the top to oxide layer afterwards and carry out plasma etching industrial, with formed have on
The oxide layer of opening little under great, and bottom and the sidewall thereof of contact hole 104 all covered by oxide layer；Such as Fig. 4 c and 5a institute
The structure shown.
Preferably, NH3 is used to carry out above-mentioned plasma etching industrial.
Concrete, make oxidation using NH3 to carry out above-mentioned plasma etching industrial with the oxide 105 removing part
During layer forms tapered profiles opening, plasma bias power (The HDP bias power) is about 1000W, etching
The power of instrument (the etch tool) is 5000～10000W, and now plasma may damage and be positioned at bottom contact hole
Silicon, but due to NF3 reaction will not produce polymer (polymer), cause damage thus without to silicon.
The reaction equation of NF3 reaction is NF3→N2+F
F+SiO2→O2+SiF4
Step 3, uses method deposition oxide 106 on semiconductor structure of ald to connect to be completely filled with
Contact hole 104；Structure as shown in Fig. 4 d and 5b.
The present invention by adjust the thickness of oxide 105 as side wall and plasma etching processing procedure formed have upper greatly
Under the oxide layer of little tapered opening be beneficial to the oxide 106 of second time atomic layer deposition and be completely filled with contact hole 104,
Make the polysilicon plug formed later seamless.
Step 4, returns oxide at quarter and (includes partial oxide 105 and partial oxide 106, generally, oxide layer
105 and oxide 106 be oxide of the same race, be such as silicon dioxide etc.) to expose the partial sidewall of contact hole 104；Such as figure
Structure shown in 4e.
In one preferred embodiment of the present invention, in above-mentioned steps four, use dry etch process return quarter oxide with
Expose the partial sidewall of contact hole 104.
Step 5, continues at deposit polycrystalline silicon on semiconductor structure and is full of (overfill) contact hole 104 to be formed
Polysilicon plug 107.
In one preferred embodiment of the present invention, in step 5, use chemical vapour deposition technique in semiconductor structure it
Upper deposit polycrystalline silicon is full of the polysilicon plug 107 of contact hole 104 to be formed.
It should be appreciated by those skilled in the art that those skilled in the art are combining prior art and above-described embodiment is permissible
Realize change case, do not repeat at this.Such change case has no effect on the flesh and blood of the present invention, does not repeats them here.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, the equipment and the structure that do not describe in detail the most to the greatest extent are construed as giving reality with the common mode in this area
Execute；Any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, may utilize the disclosure above
Method and technology contents technical solution of the present invention is made many possible variations and modification, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the present invention
In the range of technical scheme protection.
Claims (10)
1. the forming method of a seamless polysilicon plug, it is characterised in that including:
Step S1, it is provided that one is formed with the semiconductor structure of contact hole；
Step S2, in described contact hole formed cover described contact hole sidewall oxide, and return carve described oxide with in
Described contact hole is formed oxide layer, and described oxide layer has the opening that Xray films is up big and down small；
Step S3, on described semiconductor structure, deposition oxide is to be full of described contact hole；
Step S4, returns the partial sidewall carving described oxide to expose described contact hole；
Step S5, continues on described semiconductor structure deposit polycrystalline silicon to form described polysilicon plug.
The forming method of seamless polysilicon plug the most as claimed in claim 1, it is characterised in that described method is applied to 3D
In the preparation technology of NAND structure.
The forming method of seamless polysilicon plug the most as claimed in claim 1, it is characterised in that described step S2 includes:
On described semiconductor structure, deposition oxide is to be full of described contact hole；
Etch described oxide to form the oxide layer of middle opening；
Continue the top of described oxide layer is performed etching technique, to have the oxidation of described up big and down small opening described in formation
Layer, and bottom and the sidewall thereof of described contact hole all covered by described oxide layer.
The forming method of seamless polysilicon plug the most as claimed in claim 3, it is characterised in that described step S2 and step S3
In, use method deposition oxide on described semiconductor structure of ald.
The forming method of seamless polysilicon plug the most as claimed in claim 3, it is characterised in that described etching technics for wait from
Sub-etching technics.
The forming method of seamless polysilicon plug the most as claimed in claim 5, it is characterised in that use NH3 to carry out described etc.
Ion etch process.
The forming method of seamless polysilicon plug the most as claimed in claim 1, it is characterised in that described oxide is titanium dioxide
Silicon.
The forming method of seamless polysilicon plug the most as claimed in claim 1, it is characterised in that the longitudinal section of described contact hole
Profile is bending.
The forming method of seamless polysilicon plug the most as claimed in claim 1, it is characterised in that in described step S4, uses
Dry etch process returns the partial sidewall carving described oxide to expose described contact hole.
The forming method of seamless polysilicon plug the most as claimed in claim 1, it is characterised in that in described step S5, uses
Chemical vapour deposition technique on described semiconductor structure deposit polycrystalline silicon to form described polysilicon plug.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610475620.XA CN106128996A (en) | 2016-06-24 | 2016-06-24 | A kind of forming method of seamless polysilicon plug |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610475620.XA CN106128996A (en) | 2016-06-24 | 2016-06-24 | A kind of forming method of seamless polysilicon plug |
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| CN106128996A true CN106128996A (en) | 2016-11-16 |
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| CN201610475620.XA Pending CN106128996A (en) | 2016-06-24 | 2016-06-24 | A kind of forming method of seamless polysilicon plug |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107591335A (en) * | 2016-07-08 | 2018-01-16 | 北大方正集团有限公司 | The preparation method and IC chip of electric connection structure |
| CN107731830A (en) * | 2017-08-29 | 2018-02-23 | 长江存储科技有限责任公司 | A kind of polysilicon plug forming method for improving depth consistency |
| CN109727908A (en) * | 2018-11-26 | 2019-05-07 | 长江存储科技有限责任公司 | The forming method of conductive plunger and 3D nand memory part in 3D nand memory part |
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| CN107731830A (en) * | 2017-08-29 | 2018-02-23 | 长江存储科技有限责任公司 | A kind of polysilicon plug forming method for improving depth consistency |
| CN109727908A (en) * | 2018-11-26 | 2019-05-07 | 长江存储科技有限责任公司 | The forming method of conductive plunger and 3D nand memory part in 3D nand memory part |
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Application publication date: 20161116 |