CN107591335A - The preparation method and IC chip of electric connection structure - Google Patents
The preparation method and IC chip of electric connection structure Download PDFInfo
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- CN107591335A CN107591335A CN201610536973.6A CN201610536973A CN107591335A CN 107591335 A CN107591335 A CN 107591335A CN 201610536973 A CN201610536973 A CN 201610536973A CN 107591335 A CN107591335 A CN 107591335A
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Abstract
The invention provides a kind of preparation method of electric connection structure and IC chip, wherein, preparation method includes：After the insulation mask structure covered is formed above multiple current-carrying sub-districts and current-carrying sub-district on substrate successively, contact hole is formed in the mask structure that insulate；The polysilicon contact block of ion doping is formed in the contact hole；Metal connecting line is formed above the polysilicon contact block of ion doping, to complete the preparation of electric connection structure.By technical scheme, reduce causes the possibility of loose contact because aluminium silicon dissolves each other, and then reduces the possibility of integrated circuit open circuit, improves the reliability of the circuit connection of integrated circuit.
Description
Technical field
The present invention relates to semiconductor chip manufacturing technology field, in particular to a kind of preparation side of electric connection structure
Method and a kind of IC chip.
Background technology
At present, miniaturization is essentially consisted according to guide of the Moore's Law to semicon industry, the research direction of integrated circuit
With it is integrated, in order to improve the reliability of integrated circuit, the mode of directly filling metal connects two in generally use contact hole
Conduction region, but filling metal there may be many defects in the contact hole：
(1) metal in contact hole contacts with the silica-base material of bottom, may produce aluminium silicon and dissolve each other phenomenon, namely is formed
Metal silicide grain, metal silicide grain may increase the membrane stress of integrated circuit, cause film roll to stick up or out-of-flatness
Etc. fault of construction；
(2) metal in contact hole is generally formed in the form of metallic atom, and generation type is usually metal sputtering, evaporation
With plating etc., the metal level that metallic atom is formed may be discontinuous, and so as to cause the open circuit of integrated circuit, this has a strong impact on non-defective unit
Rate and reliability.
Therefore, how to improve the reliability of the electric connection structure of integrated circuit turns into technical problem urgently to be resolved hurrily.
The content of the invention
The present invention is based at least one above-mentioned technical problem, it is proposed that a kind of side of the preparation method of electric connection structure
Case, by forming the polysilicon contact block of ion doping in the contact hole, and it is square on the polysilicon contact block of ion doping
Into metal connecting line, so as to form the electrical contact of bottom current-carrying sub-district and top metal line, and avoid metallic atom
Be filled in contact hole, so avoid it is metal filled caused by aluminium silicon dissolve each other and other structures defect, improve integrated circuit
Reliability and yields.
Above-mentioned purpose is realized, embodiment according to the first aspect of the invention, there is provided a kind of preparation of electric connection structure
Method, including：After forming above multiple current-carrying sub-districts and current-carrying sub-district the insulation mask structure covered on substrate successively, exhausted
Contact hole is formed in edge mask structure；The polysilicon contact block of ion doping is formed in the contact hole；In the polycrystalline of ion doping
Metal connecting line is formed above silicon contact block, to complete the preparation of electric connection structure.
In the technical scheme, by forming the polysilicon contact block of ion doping in the contact hole, and in ion doping
Polysilicon contact block above formed metal connecting line, connect so as to form bottom current-carrying sub-district and the electricity of top metal line
Touch, and avoid and metallic atom is filled in contact hole, so avoid it is metal filled caused by aluminium silicon dissolve each other and other knots
Structure defect, improve the reliability and yields of integrated circuit.
Wherein, substrate can be monocrystalline silicon substrate, silicon carbide substrate, glass substrate or SOI (Silicon on
Isolation) substrate etc., current-carrying sub-district refer to the ion doped region for possessing conductive capability or the metal area with free electron,
In ic manufacturing process, in order to avoid the short circuit of circuit, generally use insulation mask structure parcel current-carrying sub-district, to realize
Isolation between different current-carrying sub-districts, and only by the contact hole etched in the mask structure that insulate, and filled in contact hole
Conductive contact block realizes conducting for the current-carrying sub-district of multiple isolation.
It is worth it is emphasized that the conducting resistance in the polysilicon contact hole of ion doping is low, using ion implantation technology
It can be achieved, boron series elements or nitrogen series elements can be used to be usually arranged as 50~200keV as injection ion, Implantation Energy,
Implantation dosage is usually arranged as 1013~1016/cm2。
In the above-mentioned technical solutions, it is preferable that formed above multiple current-carrying sub-districts and current-carrying sub-district and covered on substrate successively
After the insulation mask structure of lid, contact hole is formed in the mask structure that insulate, specifically includes following steps：Formed on substrate more
After individual current-carrying sub-district, oxide layer is formed using chemical vapor deposition method and/or thermal oxidation technology, and/or using chemical gaseous phase
Depositing technics forms nitration case, to be used as insulating barrier；Etching is patterned to insulating barrier, to form insulation mask structure.
In the technical scheme, it is used as insulating barrier by forming nitration case and/or oxide layer, realizes multiple current-carrying sub-districts
Between electric isolation, reduce the short-circuit possibility of integrated circuit, improve device reliability.
In the above-mentioned technical solutions, it is preferable that form shape above multiple current-carrying sub-districts and current-carrying sub-district on substrate successively
Into after the insulation mask structure of covering, contact hole is formed in the mask structure that insulate, it is specific further comprising the steps of：Covered in insulation
When membrane structure is oxide layer, dry etching and/or wet etching are carried out to oxide layer using fluorine system element and/or chlorine series elements.
In the technical scheme, by the metathesis of fluorine system element and/or chlorine series elements to the oxygen element in oxide layer,
For example with SF6、CHF3Dry etching is carried out Deng gas, realizes that the decomposition to oxide layer to form contact hole in designated area, is adopted
Mainly include timed etch (time etching) and triggering etching (endpoint etching) with the mode of dry etching, it is fixed
When etching be that etch period is preset, triggering etching is use aura Cleaning Principle, tactile when etch product changes
Sculpture in human hair erosion terminates, it is therefore apparent that dry etching is beneficial to the degree of accuracy of control etching, but easily causes ion dam age, etching speed
Degree is slow, and wet etching oxide layer generally use hydrofluoric acid solution, wet etching speed is fast, but the poor controllability of etching process.
In the above-mentioned technical solutions, it is preferable that form shape above multiple current-carrying sub-districts and current-carrying sub-district on substrate successively
Into after the insulation mask structure of covering, contact hole is formed in the mask structure that insulate, it is specific further comprising the steps of：Covered in insulation
When membrane structure is nitration case, dry etching is carried out to nitration case using fluorine system element, and/or nitration case is entered using phosphoric acid solution
Row wet etching.
In the technical scheme, dry etching is carried out to nitration case by using fluorine system element, for example with SF6、CHF3Deng
Gas carries out dry etching, and/or carries out wet etching to nitration case using phosphoric acid solution, realize decomposition to nitration case with
Designated area forms contact hole, and timed etch (time etching) and triggering etching are mainly included by the way of dry etching
(endpoint etching), timed etch is that etch period is preset, and triggering etching is to use aura Cleaning Principle,
When etch product changes, triggering etching terminates, it is therefore apparent that dry etching is beneficial to the degree of accuracy of control etching, but holds
Ion dam age is easily caused, etching speed is slow, and wet etching nitration case generally use phosphoric acid solution, wet etching speed is fast, etching
Than excellent.
In the above-mentioned technical solutions, it is preferable that form the polysilicon contact block of ion doping in the contact hole, specifically also wrap
Include following steps：After contact hole is formed, polysilicon layer is formed using chemical vapor deposition method；Ion is carried out to polysilicon layer
Injection, to form the polysilicon layer of ion doping；Quarter processing is carried out back to the polysilicon layer of ion doping, contact is removed to complete
Untill polysilicon layer outside hole, to form the polysilicon contact block being filled in contact hole.
In the technical scheme, by carrying out ion implanting to polysilicon layer, to form the polysilicon layer of ion doping, and
Quarter processing is carried out back to the polysilicon layer of ion doping, untill the polysilicon layer outside contact hole is removed completely, to form filling
In the polysilicon contact block in contact hole, with low-resistance polysilicon contact block filling contact hole, the contact of aluminium silicon and gold are avoided
Breaking problem after category filling, wherein, especially for the smaller situation of the line width of contact hole, in particular by metal sputtering work
Skill needs to be strict with the wafer of substrate and sputtering plates face, metal when minimum alignment error may all cause metal filled
Line disconnects, and especially metal connecting line is extremely difficult to adhere in contact hole side wall, is easily come off by membrane stress, and metal filled is reliable
Property is poor, and yields is low.
And fill polysilicon in the contact hole by the way of vapor deposition, polysilicon layer is more equably attached to contact
The madial wall in hole, the productivity ratio of usual side wall are the 70% of bottom wall productivity ratio, therefore, polysilicon are determined according to the groove width of contact hole
Growth thickness, you can realize being filled up completely with for contact hole, in addition, by return quarter processing can realize the flat of device surface
Change, reduce the membrane stress of subsequent thin film growth.
In the above-mentioned technical solutions, it is preferable that also include：After the polysilicon layer outside contact hole is removed completely, to contact
The polysilicon contact block filled in hole is made annealing treatment.
In the technical scheme, by being made annealing treatment to polysilicon contact hole, realize to polysilicon contact hole
Ion-activated, annealing can be RTA (Rapid Thermal Anneal, rapid thermal annealing) technique, and RTA processing is non-
Whole silicon chip is heated to 400~1300 DEG C in the often short time, has heat budget few, impurity motion is small in silicon and the time is short etc.
Feature, or using furnace anneal, polysilicon contact block is annealed using 900~1100 DEG C of temperature environments, annealing time
It is longer, but process costs are relatively low.
In the above-mentioned technical solutions, it is preferable that metal connecting line is formed above the polysilicon contact block of ion doping, with complete
It is specific further comprising the steps of into the preparation of electric connection structure：Using in metal sputtering processes, electroplating technology and evaporation process
At least one technique, metal level is formed above the polysilicon contact block of ion doping；Image conversion etching is carried out to metal level, with
Form metal connecting line.
In the technical scheme, by using at least one of metal sputtering processes, electroplating technology and evaporation process work
Skill, metal level is formed above the polysilicon contact block of ion doping, and image conversion etching is carried out to metal level, to form metal
Line, being electrically connected between multiple current-carrying sub-districts is realized, improves the reliability and yields of device.
According to the second aspect of the invention, it is also proposed that a kind of IC chip, including：Substrate, provided with multiple separation
Current-carrying sub-district；Insulate mask structure, is covered on multiple current-carrying sub-districts, corresponding with there is current-carrying sub-district in insulation mask structure
Region formed with contact hole；Electric connection structure, using the preparation of the electric connection structure described in any one technical scheme as described above
Method is prepared, and electric connection structure includes：Contact hole；The polysilicon contact block for the ion doping being filled in contact hole；Gold
Belong to line, the top of the polysilicon contact block of ion doping is formed at, to form the electrical connection between multiple current-carrying sub-districts.
In the technical scheme, by forming the polysilicon contact block of ion doping in the contact hole, and in ion doping
Polysilicon contact block above formed metal connecting line, connect so as to form bottom current-carrying sub-district and the electricity of top metal line
Touch, and avoid and metallic atom is filled in contact hole, so avoid it is metal filled caused by aluminium silicon dissolve each other and other knots
Structure defect, improve the reliability and yields of integrated circuit.
Wherein, substrate can be monocrystalline silicon substrate, silicon carbide substrate, glass substrate or SOI (Silicon on
Isolation) substrate etc., current-carrying sub-district refer to the ion doped region for possessing conductive capability or the metal area with free electron,
In ic manufacturing process, in order to avoid the short circuit of circuit, generally use insulation mask structure parcel current-carrying sub-district, to realize
Isolation between different current-carrying sub-districts, and only by the contact hole etched in the mask structure that insulate, and filled in contact hole
Conductive contact block realizes conducting for the current-carrying sub-district of multiple isolation.
It is worth it is emphasized that the conducting resistance in the polysilicon contact hole of ion doping is low, using ion implantation technology
It can be achieved, boron series elements or nitrogen series elements can be used to be usually arranged as 50~200keV as injection ion, Implantation Energy,
Implantation dosage is usually arranged as 1013~1016/cm2。
In the above-mentioned technical solutions, it is preferable that the growth thickness of the polysilicon contact block of ion doping, which is more than or equal to, to be connect
The half of the groove width of contact hole.
In the technical scheme, polysilicon is filled in the contact hole by using the mode of vapor deposition, polysilicon layer compared with
To be equably attached to the madial wall of contact hole, the productivity ratio of usual side wall is the 70% of bottom wall productivity ratio, therefore, according to contact
The groove width in hole determines the growth thickness of polysilicon, you being filled up completely with for contact hole is realized, in addition, can be real by returning quarter processing
The planarization of existing device surface, reduce the membrane stress of subsequent thin film growth.
Therefore, the groove width of contact hole is more than or equal to by the growth thickness for the polysilicon contact block for setting ion doping
Half, the reliability of polysilicon filling contact hole is improved, reduce contact hole inner structure defect.
In the above-mentioned technical solutions, it is preferable that the scope of the square resistance of the polysilicon contact block of ion doping be 10~
50Ω/□。
In the technical scheme, the scope of the square resistance of the polysilicon contact block by setting ion doping is 10~50
Ω/, ensure that polysilicon contact hole can realize it is low-resistance be electrically connected, improve device reliability.
By above technical scheme, by forming the polysilicon contact block of ion doping in the contact hole, and mixed in ion
Metal connecting line is formed above miscellaneous polysilicon contact block, is connect so as to form bottom current-carrying sub-district and the electricity of top metal line
Touch, and avoid and metallic atom is filled in contact hole, so avoid it is metal filled caused by aluminium silicon dissolve each other and other knots
Structure defect, the reliability and yields of integrated circuit are improved, is partly led in addition, the preparation method of electric connection structure is compatible with standard
Body technology, suitable for batch production.
Brief description of the drawings
Fig. 1 shows the schematic flow diagram of the preparation method of electric connection structure according to an embodiment of the invention；
Fig. 2 to Fig. 6 shows the diagrammatic cross-section of the process of electric connection structure according to an embodiment of the invention.
Embodiment
It is below in conjunction with the accompanying drawings and specific real in order to be more clearly understood that the above objects, features and advantages of the present invention
Mode is applied the present invention is further described in detail.It should be noted that in the case where not conflicting, the implementation of the application
Feature in example and embodiment can be mutually combined.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still, the present invention may be used also
To be different from other modes described here using other to implement, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Fig. 1 shows the schematic flow diagram of the preparation method of electric connection structure according to an embodiment of the invention.
As shown in figure 1, the preparation method of electric connection structure according to an embodiment of the invention, including：Step 102, successively
After the insulation mask structure covered is formed above multiple current-carrying sub-districts and current-carrying sub-district on substrate, the shape in the mask structure that insulate
Into contact hole；Step 104, the polysilicon contact block of ion doping is formed in the contact hole；Step 106, in the more of ion doping
Metal connecting line is formed above crystal silicon contact block, to complete the preparation of electric connection structure.
In the technical scheme, by forming the polysilicon contact block of ion doping in the contact hole, and in ion doping
Polysilicon contact block above formed metal connecting line, connect so as to form bottom current-carrying sub-district and the electricity of top metal line
Touch, and avoid and metallic atom is filled in contact hole, so avoid it is metal filled caused by aluminium silicon dissolve each other and other knots
Structure defect, improve the reliability and yields of integrated circuit.
Wherein, substrate can be monocrystalline silicon substrate, silicon carbide substrate, glass substrate or SOI (Silicon on
Isolation) substrate etc., current-carrying sub-district refer to the ion doped region for possessing conductive capability or the metal area with free electron,
In ic manufacturing process, in order to avoid the short circuit of circuit, generally use insulation mask structure parcel current-carrying sub-district, to realize
Isolation between different current-carrying sub-districts, and only by the contact hole etched in the mask structure that insulate, and filled in contact hole
Conductive contact block realizes conducting for the current-carrying sub-district of multiple isolation.
It is worth it is emphasized that the conducting resistance in the polysilicon contact hole of ion doping is low, using ion implantation technology
It can be achieved, boron series elements or nitrogen series elements can be used to be usually arranged as 50~200keV as injection ion, Implantation Energy,
Implantation dosage is usually arranged as 1013~1016/cm2。
In the above-mentioned technical solutions, it is preferable that formed above multiple current-carrying sub-districts and current-carrying sub-district and covered on substrate successively
After the insulation mask structure of lid, contact hole is formed in the mask structure that insulate, specifically includes following steps：Formed on substrate more
After individual current-carrying sub-district, oxide layer is formed using chemical vapor deposition method and/or thermal oxidation technology, and/or using chemical gaseous phase
Depositing technics forms nitration case, to be used as insulating barrier；Etching is patterned to insulating barrier, to form insulation mask structure.
In the technical scheme, it is used as insulating barrier by forming nitration case and/or oxide layer, realizes multiple current-carrying sub-districts
Between electric isolation, reduce the short-circuit possibility of integrated circuit, improve device reliability.
In the above-mentioned technical solutions, it is preferable that form shape above multiple current-carrying sub-districts and current-carrying sub-district on substrate successively
Into after the insulation mask structure of covering, contact hole is formed in the mask structure that insulate, it is specific further comprising the steps of：Covered in insulation
When membrane structure is oxide layer, dry etching and/or wet etching are carried out to oxide layer using fluorine system element and/or chlorine series elements.
In the technical scheme, by the metathesis of fluorine system element and/or chlorine series elements to the oxygen element in oxide layer,
For example with SF6、CHF3Dry etching is carried out Deng gas, realizes that the decomposition to oxide layer to form contact hole in designated area, is adopted
Mainly include timed etch (time etching) and triggering etching (endpoint etching) with the mode of dry etching, it is fixed
When etching be that etch period is preset, triggering etching is use aura Cleaning Principle, tactile when etch product changes
Sculpture in human hair erosion terminates, it is therefore apparent that dry etching is beneficial to the degree of accuracy of control etching, but easily causes ion dam age, etching speed
Degree is slow, and wet etching oxide layer generally use hydrofluoric acid solution, wet etching speed is fast, but the poor controllability of etching process.
In the above-mentioned technical solutions, it is preferable that form shape above multiple current-carrying sub-districts and current-carrying sub-district on substrate successively
Into after the insulation mask structure of covering, contact hole is formed in the mask structure that insulate, it is specific further comprising the steps of：Covered in insulation
When membrane structure is nitration case, dry etching is carried out to nitration case using fluorine system element, and/or nitration case is entered using phosphoric acid solution
Row wet etching.
In the technical scheme, dry etching is carried out to nitration case by using fluorine system element, for example with SF6、CHF3Deng
Gas carries out dry etching, and/or carries out wet etching to nitration case using phosphoric acid solution, realize decomposition to nitration case with
Designated area forms contact hole, and timed etch (time etching) and triggering etching are mainly included by the way of dry etching
(endpoint etching), timed etch is that etch period is preset, and triggering etching is to use aura Cleaning Principle,
When etch product changes, triggering etching terminates, it is therefore apparent that dry etching is beneficial to the degree of accuracy of control etching, but holds
Ion dam age is easily caused, etching speed is slow, and wet etching nitration case generally use phosphoric acid solution, wet etching speed is fast, etching
Than excellent.
In the above-mentioned technical solutions, it is preferable that form the polysilicon contact block of ion doping in the contact hole, specifically also wrap
Include following steps：After contact hole is formed, polysilicon layer is formed using chemical vapor deposition method；Ion is carried out to polysilicon layer
Injection, to form the polysilicon layer of ion doping；Quarter processing is carried out back to the polysilicon layer of ion doping, contact is removed to complete
Untill polysilicon layer outside hole, to form the polysilicon contact block being filled in contact hole.
In the technical scheme, by carrying out ion implanting to polysilicon layer, to form the polysilicon layer of ion doping, and
Quarter processing is carried out back to the polysilicon layer of ion doping, untill the polysilicon layer outside contact hole is removed completely, to form filling
In the polysilicon contact block in contact hole, with low-resistance polysilicon contact block filling contact hole, the contact of aluminium silicon and gold are avoided
Breaking problem after category filling, wherein, especially for the smaller situation of the line width of contact hole, in particular by metal sputtering work
Skill needs to be strict with the wafer of substrate and sputtering plates face, metal when minimum alignment error may all cause metal filled
Line disconnects, and especially metal connecting line is extremely difficult to adhere in contact hole side wall, is easily come off by membrane stress, and metal filled is reliable
Property is poor, and yields is low.
And fill polysilicon in the contact hole by the way of vapor deposition, polysilicon layer is more equably attached to contact
The madial wall in hole, the productivity ratio of usual side wall are the 70% of bottom wall productivity ratio, therefore, polysilicon are determined according to the groove width of contact hole
Growth thickness, you can realize being filled up completely with for contact hole, in addition, by return quarter processing can realize the flat of device surface
Change, reduce the membrane stress of subsequent thin film growth.
In the above-mentioned technical solutions, it is preferable that also include：After the polysilicon layer outside contact hole is removed completely, to contact
The polysilicon contact block filled in hole is made annealing treatment.
In the technical scheme, by being made annealing treatment to polysilicon contact hole, realize to polysilicon contact hole
Ion-activated, annealing can be RTA (Rapid Thermal Anneal, rapid thermal annealing) technique, and RTA processing is non-
Whole silicon chip is heated to 400~1300 DEG C in the often short time, has heat budget few, impurity motion is small in silicon and the time is short etc.
Feature, or using furnace anneal, polysilicon contact block is annealed using 900~1100 DEG C of temperature environments, annealing time
It is longer, but process costs are relatively low.
In the above-mentioned technical solutions, it is preferable that metal connecting line is formed above the polysilicon contact block of ion doping, with complete
It is specific further comprising the steps of into the preparation of electric connection structure：Using in metal sputtering processes, electroplating technology and evaporation process
At least one technique, metal level is formed above the polysilicon contact block of ion doping；Image conversion etching is carried out to metal level, with
Form metal connecting line.
In the technical scheme, by using at least one of metal sputtering processes, electroplating technology and evaporation process work
Skill, metal level is formed above the polysilicon contact block of ion doping, and image conversion etching is carried out to metal level, to form metal
Line, being electrically connected between multiple current-carrying sub-districts is realized, improves the reliability and yields of device.
Have with reference to Fig. 2 to Fig. 6 to electric connection structure according to an embodiment of the invention and IC chip
Body explanation.
As shown in Fig. 2 the insulation covered above multiple current-carrying sub-districts 202 and current-carrying sub-district 202 is formed on substrate successively
After mask structure 204, as shown in figure 3, forming contact hole 206 in the mask structure 204 that insulate, as shown in Figure 4 and Figure 5, connecing
The polysilicon contact block 208 of ion doping is formed in contact hole 206, as shown in Figure 6 on the polysilicon contact block 208 of ion doping
It is square into metal connecting line 210, to complete the preparation of electric connection structure.
In the technical scheme, by contact hole 206 formed ion doping polysilicon contact block 208, and from
The top of polysilicon contact block 208 of son doping forms metal connecting line 210, so as to form bottom current-carrying sub-district 202 and top-gold
Belong to the electrical contact of line 210, and avoid and metallic atom is filled in contact hole 206, and then avoid metal filled make
Into aluminium silicon dissolve each other and other structures defect, improve the reliability and yields of integrated circuit.
Wherein, substrate can be monocrystalline silicon substrate, silicon carbide substrate, glass substrate or SOI (Silicon on
Isolation) substrate etc., current-carrying sub-district 202 refer to the ion doped region for possessing conductive capability or the metal with free electron
Area, in ic manufacturing process, in order to avoid the short circuit of circuit, generally use insulation mask structure 204 wraps up current-carrying sub-district
202, to realize the isolation between different current-carrying sub-districts 202, and the contact hole only by being etched in the mask structure 204 that insulate
Conductive contact block is filled in 206, and contact hole 206 to realize conducting for the current-carrying sub-district 202 of multiple isolation.
It is worth it is emphasized that the conducting resistance of the contact hole 206 of polysilicon 208 of ion doping is low, is noted using ion
Entering technique to can be achieved, boron series elements or nitrogen series elements can be used as injection ion, Implantation Energy is usually arranged as 50~
200keV, implantation dosage are usually arranged as 1013~1016/cm2。
As shown in Figure 2, it is preferable that formed above multiple current-carrying sub-districts 202 and current-carrying sub-district 202 and covered on substrate successively
Insulation mask structure 204 after, in the mask structure 204 that insulate formed contact hole 206, specifically include following steps：In substrate
After the upper multiple current-carrying sub-districts 202 of formation, oxide layer is formed using chemical vapor deposition method and/or thermal oxidation technology, and/or adopt
Nitration case is formed with chemical vapor deposition method, to be used as insulating barrier；Etching is patterned to insulating barrier, is covered with forming insulation
Membrane structure 204.
In the technical scheme, it is used as insulating barrier by forming nitration case and/or oxide layer, realizes multiple current-carrying sub-districts
Electric isolation between 202, the short-circuit possibility of integrated circuit is reduced, improves device reliability.
As shown in Figure 3, it is preferable that formed above multiple current-carrying sub-districts 202 and current-carrying sub-district 202 and formed on substrate successively
After the insulation mask structure 204 of covering, contact hole 206 is formed in the mask structure 204 that insulate, it is specific further comprising the steps of：
When the mask structure 204 that insulate be oxide layer, oxide layer is carried out using fluorine system element and/or chlorine series elements dry etching with/
Or wet etching.
In the technical scheme, by the metathesis of fluorine system element and/or chlorine series elements to the oxygen element in oxide layer,
For example with SF6、CHF3Dry etching is carried out Deng gas, realizes the decomposition to oxide layer to form contact hole in designated area
206, timed etch (time etching) and triggering etching (endpoint are mainly included by the way of dry etching
Etching), timed etch is that etch period is preset, and triggering etching is to use aura Cleaning Principle, is sent out in etch product
During changing, triggering etching terminates, it is therefore apparent that dry etching is beneficial to the degree of accuracy of control etching, but easily causes ion
Damage, etching speed is slow, and wet etching oxide layer generally use hydrofluoric acid solution, wet etching speed is fast, but etching process
Poor controllability.
As shown in Figure 3, it is preferable that formed above multiple current-carrying sub-districts 202 and current-carrying sub-district 202 and formed on substrate successively
After the insulation mask structure 204 of covering, contact hole 206 is formed in the mask structure 204 that insulate, it is specific further comprising the steps of：
When the mask structure 204 that insulate is nitration case, dry etching is carried out to nitration case using fluorine system element, and/or it is molten using phosphoric acid
Liquid carries out wet etching to nitration case.
In the technical scheme, dry etching is carried out to nitration case by using fluorine system element, for example with SF6、CHF3Deng
Gas carries out dry etching, and/or carries out wet etching to nitration case using phosphoric acid solution, realize decomposition to nitration case with
Designated area forms contact hole 206, and timed etch (time etching) and triggering are mainly included by the way of dry etching
Etch (endpoint etching), timed etch is that etch period is preset, and triggering etching is former using aura detection
Reason, when etch product changes, triggering etching terminates, it is therefore apparent that and dry etching is beneficial to the degree of accuracy of control etching, but
It is to easily cause ion dam age, etching speed is slow, and wet etching nitration case generally use phosphoric acid solution, wet etching speed is fast,
Etching ratio is excellent.
Preferably, the polysilicon contact block 208 of ion doping is formed in contact hole 206, it is specific further comprising the steps of：
As shown in figure 4, after contact hole 206 is formed, polysilicon layer 208 is formed using chemical vapor deposition method；To polysilicon layer 208
Ion implanting is carried out, to form the polysilicon layer 208 of ion doping；As shown in figure 5, the polysilicon layer 208 of ion doping is entered
Go back and handle at quarter, untill the polysilicon 208 outside contact hole 206 is removed completely, to form the polycrystalline being filled in contact hole 206
Silicon contact block 208.
In the technical scheme, by carrying out ion implanting to polysilicon layer 208, to form the polysilicon layer of ion doping
208, and quarter processing is carried out back to the polysilicon layer 208 of ion doping, it is to the polysilicon 208 outside contact hole 206 is removed completely
Only, to form the polysilicon contact block 208 being filled in contact hole 206, filled and contacted with low-resistance polysilicon contact block 208
Hole 206, the breaking problem after aluminium silicon contacts and is metal filled is avoided, wherein, it is smaller especially for the line width of contact hole 206
Situation, need to be strict with wafer and the sputtering plates face of substrate, minimum alignment in particular by metal sputtering processes
Metal connecting line 210 disconnects when error may all cause metal filled, and especially metal connecting line 210 is extremely difficult in the side wall of contact hole 206
Attachment, is easily come off by membrane stress, metal filled poor reliability, and yields is low.
And polysilicon 208 is filled in contact hole 206 by the way of vapor deposition, polysilicon layer 208 is more equably
The madial wall of contact hole 206 is attached to, the productivity ratio of usual side wall is the 70% of bottom wall productivity ratio, therefore, according to contact hole 206
Groove width W determine the growth thickness T of polysilicon 208, you can realize being filled up completely with for contact hole 206, handled at quarter in addition, passing through and returning
The planarization of device surface can be realized, reduces the membrane stress of subsequent thin film growth.
In the above-mentioned technical solutions, it is preferable that also include：It is right after the polysilicon 208 outside contact hole 206 is removed completely
The polysilicon contact block 208 of filling is made annealing treatment in contact hole 206.
In the technical scheme, by being made annealing treatment to the contact hole 206 of polysilicon 208, realize to polysilicon 208
Contact hole 206 it is ion-activated, annealing can be RTA (Rapid Thermal Anneal, rapid thermal annealing) technique,
RTA processing is that whole silicon chip is heated into 400~1300 DEG C within the very short time, has heat budget few, impurity is transported in silicon
The features such as dynamic small and time is short, or using furnace anneal, using 900~1100 DEG C of temperature environments to polysilicon contact block 208
Annealed, annealing time is longer, but process costs are relatively low.
As shown in Figure 6, it is preferable that metal connecting line 210 is formed above the polysilicon contact block 208 of ion doping, with complete
It is specific further comprising the steps of into the preparation of electric connection structure：Using in metal sputtering processes, electroplating technology and evaporation process
At least one technique, metal level is formed above the polysilicon contact block 208 of ion doping；Image conversion quarter is carried out to metal level
Erosion, to form metal connecting line 210.
In the technical scheme, by using at least one of metal sputtering processes, electroplating technology and evaporation process work
Skill, metal level is formed above the polysilicon contact block 208 of ion doping, and image conversion etching is carried out to metal level, to be formed
Metal connecting line 210, being electrically connected between multiple current-carrying sub-districts 202 is realized, improves the reliability and yields of device.
As shown in fig. 6, IC chip according to an embodiment of the invention, including：Substrate (not shown), is provided with
The current-carrying sub-district 202 of multiple separation；Insulate mask structure 204, is covered on multiple current-carrying sub-districts 202, and insulate mask structure
With having 202 corresponding region of current-carrying sub-district formed with contact hole 206 in 204；Electric connection structure, using any one technology as described above
The preparation method of electric connection structure described in scheme is prepared, and electric connection structure includes：Contact hole 206；It is filled in contact hole
The polysilicon contact block 208 of ion doping in 206；Metal connecting line 210, it is formed at the polysilicon contact block 208 of ion doping
Top, to form the electrical connection between multiple current-carrying sub-districts 202.
In the technical scheme, by contact hole 206 formed ion doping polysilicon contact block 208, and from
The top of polysilicon contact block 208 of son doping forms metal connecting line 210, so as to form bottom current-carrying sub-district 202 and top-gold
Belong to the electrical contact of line 210, and avoid and metallic atom is filled in contact hole 206, and then avoid metal filled make
Into aluminium silicon dissolve each other and other structures defect, improve the reliability and yields of integrated circuit.
Wherein, substrate can be monocrystalline silicon substrate, silicon carbide substrate, glass substrate or SOI (Silicon on
Isolation) substrate etc., current-carrying sub-district 202 refer to the ion doped region for possessing conductive capability or the metal with free electron
Area, in ic manufacturing process, in order to avoid the short circuit of circuit, generally use insulation mask structure 204 wraps up current-carrying sub-district
202, to realize the isolation between different current-carrying sub-districts 202, and the contact hole only by being etched in the mask structure 204 that insulate
Conductive contact block is filled in 206, and contact hole 206 to realize conducting for the current-carrying sub-district 202 of multiple isolation.
It is worth it is emphasized that the conducting resistance of the contact hole 206 of polysilicon 208 of ion doping is low, is noted using ion
Entering technique to can be achieved, boron series elements or nitrogen series elements can be used as injection ion, Implantation Energy is usually arranged as 50~
200keV, implantation dosage are usually arranged as 1013~1016/cm2。
In the above-mentioned technical solutions, it is preferable that the growth thickness T of the polysilicon contact block 208 of ion doping is more than or waited
In the groove width W of contact hole 206 half.
In the technical scheme, polysilicon 208, polycrystalline are filled in contact hole 206 by using the mode of vapor deposition
Silicon layer 208 is more equably attached to the madial wall of contact hole 206, and the productivity ratio of usual side wall is the 70% of bottom wall productivity ratio,
Therefore, the growth thickness T of polysilicon 208 is determined according to the groove width W of contact hole 206, you can realize filling out completely for contact hole 206
Fill, in addition, the planarization of device surface can be realized by returning quarter processing, reduce the membrane stress of subsequent thin film growth.
Therefore, contact hole 206 is more than or equal to by the growth thickness T for the polysilicon contact block 208 for setting ion doping
Groove width W half, improve the reliability of the filling contact hole 206 of polysilicon 208, reduce the inner structure of contact hole 206
Defect.
In the above-mentioned technical solutions, it is preferable that the scope of the square resistance of the polysilicon contact block 208 of ion doping is 10
~50 Ω/.
In the technical scheme, the scope of the square resistance of the polysilicon contact block 208 by setting ion doping is 10
~50 Ω/, ensure that the contact hole 206 of polysilicon 208 can realize it is low-resistance be electrically connected, improve device reliability.
Technical scheme is described in detail above in association with accompanying drawing, the present invention proposes a kind of system of electric connection structure
Preparation Method and a kind of IC chip, by forming the polysilicon contact block of ion doping in the contact hole, and mixed in ion
Metal connecting line is formed above miscellaneous polysilicon contact block, is connect so as to form bottom current-carrying sub-district and the electricity of top metal line
Touch, and avoid and metallic atom is filled in contact hole, so avoid it is metal filled caused by aluminium silicon dissolve each other and other knots
Structure defect, improve the reliability and yields of integrated circuit.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (10)
- A kind of 1. preparation method of electric connection structure, it is characterised in that including：After forming above multiple current-carrying sub-districts and the current-carrying sub-district insulation mask structure covered on substrate successively, described Contact hole is formed in insulation mask structure；The polysilicon contact block of ion doping is formed in the contact hole；Metal connecting line is formed above the polysilicon contact block of the ion doping, to complete the preparation of the electric connection structure.
- 2. the preparation method of electric connection structure according to claim 1, it is characterised in that formed successively on substrate multiple Above current-carrying sub-district and the current-carrying sub-district after the insulation mask structure of covering, contact is formed in the insulation mask structure Hole, specifically include following steps：After forming multiple current-carrying sub-districts on the substrate, using chemical vapor deposition method and/or thermal oxidation technology shape Nitration case is formed into oxide layer, and/or using chemical vapor deposition method, to be used as insulating barrier；Etching is patterned to the insulating barrier, to form the insulation mask structure.
- 3. the preparation method of electric connection structure according to claim 2, it is characterised in that formed successively on substrate multiple After forming the insulation mask structure of covering above current-carrying sub-district and the current-carrying sub-district, formed and connect in the insulation mask structure Contact hole, it is specific further comprising the steps of：When the insulation mask structure is oxide layer, the oxide layer is done using fluorine system element and/or chlorine series elements Method etches and/or wet etching.
- 4. the preparation method of electric connection structure according to claim 2, it is characterised in that formed successively on substrate multiple After forming the insulation mask structure of covering above current-carrying sub-district and the current-carrying sub-district, formed and connect in the insulation mask structure Contact hole, it is specific further comprising the steps of：When the insulation mask structure is nitration case, dry etching is carried out to the nitration case using fluorine system element, and/or adopt Wet etching is carried out to the nitration case with phosphoric acid solution.
- 5. the preparation method of electric connection structure according to claim 4, it is characterised in that formed in the contact hole from The polysilicon contact block of son doping, it is specific further comprising the steps of：After the contact hole is formed, polysilicon layer is formed using chemical vapor deposition method；Ion implanting is carried out to the polysilicon layer, to form the polysilicon layer of ion doping；Quarter processing is carried out back to the polysilicon layer of the ion doping, is to the polysilicon layer removed completely outside the contact hole Only, the polysilicon contact block being filled in formation in the contact hole.
- 6. the preparation method of electric connection structure according to claim 5, it is characterised in that also include：After the polysilicon layer outside the contact hole is removed completely, the polysilicon contact block filled in the contact hole is moved back Fire processing.
- 7. the preparation method of electric connection structure according to any one of claim 1 to 6, it is characterised in that it is described from Son doping polysilicon contact block above formed metal connecting line, to complete the preparation of the electric connection structure, specifically also include with Lower step：Using at least one of metal sputtering processes, electroplating technology and evaporation process technique, in the polycrystalline of the ion doping Metal level is formed above silicon contact block；Image conversion etching is carried out to the metal level, to form the metal connecting line.
- A kind of 8. IC chip, it is characterised in that including：Substrate, the current-carrying sub-district provided with multiple separation；Insulate mask structure, is covered on the multiple current-carrying sub-district, has carrier with described in the insulation mask structure Region is formed with contact hole corresponding to area；Electric connection structure, using the preparation method preparation of the electric connection structure as any one of claims 1 to 7 Into the electric connection structure includes：The contact hole；The polysilicon contact block for the ion doping being filled in the contact hole；Metal connecting line, be formed at the top of the polysilicon contact block of the ion doping, with formed the multiple current-carrying sub-district it Between electrical connection.
- 9. IC chip according to claim 8, it is characterised in thatThe growth thickness of the polysilicon contact block of the ion doping is more than or equal to the half of the groove width of the contact hole.
- 10. the preparation method of electric connection structure according to claim 8 or claim 9, it is characterised in thatThe scope of the square resistance of the polysilicon contact block of the ion doping is 10~50 Ω/.
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