CN103928528A - Junction terminal structure of transverse high-voltage power semiconductor device - Google Patents
Junction terminal structure of transverse high-voltage power semiconductor device Download PDFInfo
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- CN103928528A CN103928528A CN201410175873.6A CN201410175873A CN103928528A CN 103928528 A CN103928528 A CN 103928528A CN 201410175873 A CN201410175873 A CN 201410175873A CN 103928528 A CN103928528 A CN 103928528A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
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Abstract
The invention relates to the technical field of semiconductor power devices, in particular to a junction terminal structure of a transverse high-voltage power semiconductor device. According to the junction terminal structure, by reducing the total area of a P-type substrate and an N-type shift region, at the position of a curvature junction terminal, of the device, the device is prevented from being used up in advance in the region of the P-type substrate, and the withstand voltage of the device at the position of the curvature junction terminal is guaranteed. The junction terminal structure of the transverse high-voltage power semiconductor device has the advantages that the influences on the withstand voltage of the whole device from the curvature junction terminal can be obviously reduced, the electric field, in a transitional region, of the device cannot be too high, the withstand voltage of the device is optimized by changing the area of the shift region or the area of the P-type substrate, and the withstand voltage of the device is guaranteed accordingly. The junction terminal structure of the transverse high-voltage power semiconductor device is particularly suitable for junction structures of transverse high-voltage semiconductor devices.
Description
Technical field
The present invention relates to semiconductor power device technology field, relate to specifically a kind of junction termination structures of horizontal high-voltage power semiconductor device.
Background technology
Along with industrial motorized degree improves day by day, more and more higher to the requirement of high-voltage large current device.In order to improve the withstand voltage of device, occurred that various junction termination structures are to meet the requirement of withstand voltage of device.
The development of high-voltage power integrated circuit be unable to do without horizontal high-voltage power semiconductor device that can be integrated.Laterally high-voltage power semiconductor device is generally closing structure, comprises the structures such as circle, racetrack and interdigitated.For closed racetrack structure and interdigitated configuration, in bend part and finger tip, partly there will be small curve terminal, electric field line easily occurs at small curvature radius place to concentrate, thereby causes device higher at small curvature radius place electric field, and avalanche breakdown occurs in advance.And employing straight line junction termination structures and the racetrack terminal structure of curvature junction termination structures institute combination and the design that includes the terminal structure of elbow structure, can avoid device to puncture in advance in curvature knot end, improve the withstand voltage of device, but due at curvature terminal structure place, the equipotential lines of device can be concentrated than being easier to respect to straight line terminal structure, therefore cause electric field higher than other place, occur to puncture in advance, reduce the withstand voltage of device; And high voltage power device is at curvature junction termination structures place, and being mainly used to bear withstand voltage drift region can be less with respect to the drift region of straight line end, and this can cause exhausting in advance in the drift region at curvature terminal place, affects the withstand voltage of device.
Summary of the invention
Problem to be solved by this invention, to exhaust in advance exactly for the horizontal high-voltage power semiconductor device of above-mentioned tradition in the drift region at curvature terminal place, proposes a kind of junction termination structures of horizontal high-voltage power semiconductor device.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of junction termination structures of horizontal high-voltage power semiconductor device, as shown in Figure 5, comprises straight line junction termination structures and curvature junction termination structures; Described straight line junction termination structures, with laterally high-voltage power active area of semiconductor device structure is identical, comprises drain electrode N
+contact zone 1, N-type drift region 2, P type substrate 3, grid polycrystalline silicon 4, gate oxide 5, P-well district 6, source electrode N
+contact zone 7, source electrode P
+contact zone 8; P-well district 6 and N-type drift region 2 are positioned at the upper strata of P type substrate 3, in the middle of wherein P-well district 6 is positioned at, and ShiNXing drift region, both sides 2, and P-well district 6 is connected with N-type drift region 2; Both sides away from P-well district 6 in N-type drift region 2 are drain electrode N
+contact zone 1; Drain electrode N
+contact zone 1 is greater than the transverse width near curvature junction termination structures one end away from the transverse width of curvature junction termination structures one end; The upper strata in P-well district 6 has the source electrode N being connected with metallizing source
+contact zone 7 and source electrode P
+contact zone 8, wherein source electrode P
+in the middle of contact zone 8 is positioned at, source electrode N
+contact zone 7 is positioned at source electrode P
+8 both sides, contact zone; Source electrode N
+6 surfaces, P-well district between contact zone 7 and N-type drift region 2 are gate oxides 5, and the surface of gate oxide 5 is grid polycrystalline silicons 4;
Described curvature junction termination structures comprises drain electrode N
+contact zone 1, N-type drift region 2, P type substrate 3, grid polycrystalline silicon 4, gate oxide 5, P-well district 6, source electrode P
+contact zone 8; 6 surfaces, P-well district are gate oxides 5, and the surface of gate oxide 5 is grid polycrystalline silicons 4; N in curvature junction termination structures
+contact zone 1, N-type drift region 2, gate oxide 5 and grid polycrystalline silicon 4 respectively with straight line junction termination structures in N
+contact zone 1, N-type drift region 2, gate oxide 5 and grid polycrystalline silicon 4 are connected and form loop configuration; Wherein, the annular N in curvature junction termination structures
+contact zone 1 surrounds annular N-type drift region 2, and the annular N-type drift region 2 in curvature junction termination structures surrounds grid polycrystalline silicon 4 and gate oxide 5; Different from " the P-well district 6 in straight line junction termination structures is connected with N-type drift region 2 ", the P-well district 6 in curvature junction termination structures is not connected with N-type drift region 2.
Beneficial effect of the present invention is, can significantly reduce the impact of curvature knot terminal on whole device withstand voltage, make the device can be not excessive at the electric field of transition region, and by changing the area of drift region or P type substrate, make the withstand voltage optimization that reaches of device, guarantee the withstand voltage of device, compare with existing various knot terminal technology simultaneously, the present invention does not have additionally to introduce some new terminal structures, therefore can, in the situation that not increasing processing step and cost, improve device in the problem of withstand voltage of curvature knot end.
Accompanying drawing explanation
Fig. 1 is the laterally junction termination structures schematic diagram of high-voltage power semiconductor device of tradition;
Fig. 2 is the laterally junction termination structures vertical view of high-voltage power semiconductor device of tradition;
Fig. 3 is along the device schematic cross-section of AA` line in Fig. 2;
Fig. 4 is along the device schematic cross-section of BB` line in Fig. 2;
Fig. 5 is the junction termination structures schematic diagram of horizontal high-voltage power semiconductor device of the present invention;
Fig. 6 is the junction termination structures vertical view of horizontal high-voltage power semiconductor device of the present invention;
Fig. 7 is along the device schematic cross-section of AA` line in Fig. 6;
Fig. 8 is along the device schematic cross-section of BB` line in Fig. 6;
Fig. 9 is along the device schematic cross-section of CC` line in Fig. 6;
Figure 10 is the device architecture schematic diagram of embodiment 1;
Figure 11 is the device architecture schematic diagram of embodiment 2;
Figure 12 is the device architecture schematic diagram of embodiment 3;
Figure 13 is the device architecture schematic diagram of embodiment 4;
Figure 14 is the device architecture schematic diagram of embodiment 5;
Figure 15 is the device architecture schematic diagram of embodiment 6.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
The present invention is directed to a kind of horizontal high-voltage power semiconductor device that traditional line junction termination structures and curvature junction termination structures form, propose new curvature terminal structure, further improve device in the problem of withstand voltage of curvature knot end; And technique is simple, be easy to realize.The present invention's main technical schemes adopting of dealing with problems is by the change of device curvature junction termination structures place drain terminal structure having been increased to the gross area of device in curvature knot end P type substrate and N-type drift region, corresponding different devices and doping content can prevent that device from occurring to exhaust in advance at P type substrate zone or N-type drift region by changing the area of P type substrate and N-type drift region, make device reach optimum the withstand voltage of curvature knot end, assurance device is withstand voltage curvature knot end.
As depicted in figs. 1 and 2, be the junction termination structures of traditional horizontal high-voltage power semiconductor device, comprise straight line junction termination structures and curvature junction termination structures; As shown in Figure 3, straight line junction termination structures, with laterally high-voltage power active area of semiconductor device structure is identical, comprises drain electrode N
+contact zone 1, N-type drift region 2, P type substrate 3, grid polycrystalline silicon 4, gate oxide 5, P-well district 6, source electrode N
+contact zone 7, source electrode P
+contact zone 8; P-well district 6 and N-type drift region 2 are positioned at the upper strata of P type substrate 3, in the middle of wherein P-well district 6 is positioned at, and ShiNXing drift region, both sides 2, and P-well district 6 is connected with N-type drift region 2; Both sides away from P-well district 6 in N-type drift region 2 are drain electrode N
+contact zone 1, the upper strata in P-well district 6 has the source electrode N being connected with metallizing source
+contact zone 7 and source electrode P
+contact zone 8, wherein source electrode P
+in the middle of contact zone 8 is positioned at, source electrode N
+contact zone 7 is positioned at source electrode P
+8 both sides, contact zone; Source electrode N
+6 surfaces, P-well district between contact zone 7 and N-type drift region 2 are gate oxides 5, and the surface of gate oxide 5 is grid polycrystalline silicons 4;
As shown in Figure 4, curvature junction termination structures comprises drain electrode N
+contact zone 1, N-type drift region 2, P type substrate 3, grid polycrystalline silicon 4, gate oxide 5, P-well district 6, source electrode P
+contact zone 8; 6 surfaces, P-well district are gate oxides 5, and the surface of gate oxide 5 is grid polycrystalline silicons 4; N in curvature junction termination structures
+contact zone 1, N-type drift region 2, gate oxide 5 and grid polycrystalline silicon 4 respectively with straight line junction termination structures in N
+contact zone 1, N-type drift region 2, gate oxide 5 and grid polycrystalline silicon 4 are connected and form loop configuration; Wherein, the annular N in curvature junction termination structures
+contact zone 1 surrounds annular N-type drift region 2, and the annular N-type drift region 2 in curvature junction termination structures surrounds grid polycrystalline silicon 4 and gate oxide 5; Different from " the P-well district 6 in straight line junction termination structures is connected with N-type drift region 2 ", the P-well district 6 in curvature junction termination structures is not connected with N-type drift region 2 and mutual spacing is L
psub; The length of N-type drift region 2 is L
ndrift.
As shown in Figure 5 and Figure 6, be the junction termination structures of horizontal high-voltage power semiconductor device of the present invention, as Figure 7-9, the place that structure of the present invention is different from traditional structure is, drain electrode N of the present invention
+contact zone 1 is greater than the transverse width near curvature junction termination structures one end away from the transverse width of curvature junction termination structures one end, thereby traditional structure is by reducing drain terminal N relatively
+the area of contact zone, has increased the drift region at curvature junction termination structures place and the gross area of substrate, device is born higher withstand voltage.
Embodiment 1:
As shown in figure 10, this example comprises straight line junction termination structures and curvature junction termination structures; Described straight line junction termination structures, with laterally high-voltage power active area of semiconductor device structure is identical, comprises drain electrode N
+contact zone 1, N-type drift region 2, P type substrate 3, grid polycrystalline silicon 4, gate oxide 5, P-well district 6, source electrode N
+contact zone 7, source electrode P
+contact zone 8; P-well district 6 and N-type drift region 2 are positioned at the upper strata of P type substrate 3, in the middle of wherein P-well district 6 is positioned at, and ShiNXing drift region, both sides 2, and P-well district 6 is connected with N-type drift region 2; Both sides away from P-well district 6 in N-type drift region 2 are drain electrode N
+contact zone 1; Drain electrode N
+contact zone 1 is greater than the transverse width near curvature junction termination structures one end away from the transverse width of curvature junction termination structures one end; The upper strata in P-well district 6 has the source electrode N being connected with metallizing source
+contact zone 7 and source electrode P
+contact zone 8, wherein source electrode P
+in the middle of contact zone 8 is positioned at, source electrode N
+contact zone 7 is positioned at source electrode P
+8 both sides, contact zone; Source electrode N
+6 surfaces, P-well district between contact zone 7 and N-type drift region 2 are gate oxides 5, and the surface of gate oxide 5 is grid polycrystalline silicons 4;
Described curvature junction termination structures comprises drain electrode N
+contact zone 1, N-type drift region 2, P type substrate 3, grid polycrystalline silicon 4, gate oxide 5, P-well district 6, source electrode P
+contact zone 8; 6 surfaces, P-well district are gate oxides 5, and the surface of gate oxide 5 is grid polycrystalline silicons 4; N in curvature junction termination structures
+contact zone 1, N-type drift region 2, gate oxide 5 and grid polycrystalline silicon 4 respectively with straight line junction termination structures in N
+contact zone 1, N-type drift region 2, gate oxide 5 and grid polycrystalline silicon 4 are connected and form loop configuration; Wherein, the annular N in curvature junction termination structures
+contact zone 1 surrounds annular N-type drift region 2, and the annular N-type drift region 2 in curvature junction termination structures surrounds grid polycrystalline silicon 4 and gate oxide 5; Different from " the P-well district 6 in straight line junction termination structures is connected with N-type drift region 2 ", the P-well district 6 in curvature junction termination structures is not connected with N-type drift region 2 and mutual spacing is L
psub; The length of N-type drift region 2 is L
ndriftt+ Δ L.P-well district 6 in its mean curvature junction termination structures and the spacing L of N-type drift region 2
psublength L with N-type drift region 2
ndrifttotal length at several microns between tens of micron.
N in this routine cathetus junction termination structures
+contact zone 1 to curvature junction termination structures near time transverse width dwindle gradually, thereby reduced N
+contact zone 1 area makes N in curvature junction termination structures simultaneously
+the relative traditional structure of area of contact zone 1 also greatly dwindles, the gross area of curvature knot end P type substrate 3 and N-type drift region 2 is increased, by the change to P type substrate and N-type drift region area, can prevent that device from occurring to exhaust in advance at P type substrate zone or N-type drift region, assurance device is withstand voltage curvature knot end.This example is at the original L of retainer member curvature knot end
psubthe constant situation of length under, increased L
ndrifttlength, become L
ndrift+ Δ L, thereby the area of increase N-type drift region, when substrate doping is higher, by the area of suitable increase N-type drift region, can guarantee that the withstand voltage of P type substrate and N-type drift region reaches maximum like this.
Embodiment 2:
As shown in figure 11, the place that this example is different from embodiment 1 is, retainer member is at the original L of curvature knot end
ndrifttthe constant situation of length under, increased L
psublength, become L
psub+ Δ L, thereby the area of increase P type substrate zone, when substrate doping is lower, depletion region will be extended to P type substrate zone very soon, and the area that now increases P type substrate zone can prevent that P type substrate zone from exhausting in advance, and assurance device is withstand voltage curvature knot end.
Embodiment 3:
As shown in figure 12, the place that this example is different from embodiment 1 is, increases L simultaneously
psublength and L
ndriftlength, make it become L
psub+ Δ L
1and L
ndrift+ Δ L
2, Δ L wherein
1with Δ L
2sum equals Δ L, thereby increases the area of P type substrate zone and N-type drift region simultaneously, makes the withstand voltage of device can reach optimization.
Embodiment 4:
As shown in figure 13, the place that this example is different from embodiment 1 is, the N in curvature junction termination structures
+contact zone 1 does not form annular, but forms the rectangle that corner is arc, has further increased the gross area of P type substrate 3 and N-type drift region 2 in curvature junction termination structures, has further improved the resistance to pressure of device.This example is at the original L of retainer member curvature knot end
psubthe constant situation of length under, increased L
ndrifttlength, become L
ndrift+ Δ L, thereby the area of increase N-type drift region, when substrate doping is higher, by the area of suitable increase N-type drift region, can guarantee that the withstand voltage of P type substrate and N-type drift region reaches maximum like this.
Embodiment 5:
As shown in figure 14, the place that this example is different from embodiment 4 is, retainer member is at the original L of curvature knot end
ndrifttthe constant situation of length under, increased L
psublength, become L
psub+ Δ L, thereby the area of increase P type substrate zone, when substrate doping is lower, depletion region will be extended to P type substrate zone very soon, and the area that now increases P type substrate zone can prevent that P type substrate zone from exhausting in advance, and assurance device is withstand voltage curvature knot end.
Embodiment 6:
As shown in figure 15, the place that this example is different from embodiment 4 is, increases L simultaneously
psublength and L
ndriftlength, thereby increase the area of P type substrate zone and N-type drift region simultaneously, make the withstand voltage of device can reach optimization.
Claims (1)
1. a junction termination structures for horizontal high-voltage power semiconductor device, comprises straight line junction termination structures and curvature junction termination structures; Described straight line junction termination structures, with laterally high-voltage power active area of semiconductor device structure is identical, comprises drain electrode N
+contact zone (1), N-type drift region (2), P type substrate (3), grid polycrystalline silicon (4), gate oxide (5), P-well district (6), source electrode N
+contact zone (7), source electrode P
+contact zone (8); P-well district (6) and N-type drift region (2) are positioned at the upper strata of P type substrate (3), in the middle of wherein P-well district (6) are positioned at, and ShiNXing drift region, both sides (2), and P-well district (6) are connected with N-type drift region (2); Both sides away from P-well district (6) in N-type drift region (2) are drain electrode N
+contact zone (1); The upper strata in P-well district (6) has the source electrode N being connected with metallizing source
+contact zone (7) and source electrode P
+contact zone (8), wherein source electrode P
+in the middle of contact zone (8) is positioned at, source electrode N
+contact zone (7) is positioned at source electrode P
+both sides, contact zone (8); Source electrode N
+surface, P-well district (6) between contact zone (7) and N-type drift region (2) is gate oxide (5), and the surface of gate oxide (5) is grid polycrystalline silicon (4);
Described curvature junction termination structures comprises drain electrode N
+contact zone (1), N-type drift region (2), P type substrate (3), grid polycrystalline silicon (4), gate oxide (5), P-well district (6), source electrode P
+contact zone (8); Surface, P-well district (6) is gate oxide (5), and the surface of gate oxide (5) is grid polycrystalline silicon (4); N in curvature junction termination structures
+contact zone (1), N-type drift region (2), gate oxide (5) and grid polycrystalline silicon (4) respectively with straight line junction termination structures in N
+contact zone (1), N-type drift region (2), gate oxide (5) and grid polycrystalline silicon (4) are connected and form loop configuration; Wherein, the annular N in curvature junction termination structures
+contact zone (1) surrounds annular N-type drift region (2), and the annular N-type drift region (2) in curvature junction termination structures surrounds grid polycrystalline silicon (4) and gate oxide (5); Different from " the P-well district (6) in straight line junction termination structures is connected with N-type drift region (2) ", the P-well district (6) in curvature junction termination structures is not connected with N-type drift region (2);
It is characterized in that drain electrode N
+contact zone (1) is greater than the transverse width near curvature junction termination structures one end away from the transverse width of curvature junction termination structures one end.
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CN104638013A (en) * | 2015-01-30 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Isolated NLDMOS (N type Laterally Diffused Metal Oxide Semiconductor) device |
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CN106098755A (en) * | 2016-08-25 | 2016-11-09 | 电子科技大学 | The laterally junction termination structures of high voltage power device |
CN106252393A (en) * | 2016-08-25 | 2016-12-21 | 电子科技大学 | The laterally junction termination structures of high voltage power device |
CN106298874A (en) * | 2016-08-25 | 2017-01-04 | 电子科技大学 | The laterally junction termination structures of high voltage power device |
CN106252393B (en) * | 2016-08-25 | 2019-04-12 | 电子科技大学 | The junction termination structures of lateral high voltage power device |
CN106098755B (en) * | 2016-08-25 | 2019-04-12 | 电子科技大学 | The junction termination structures of lateral high voltage power device |
CN106298874B (en) * | 2016-08-25 | 2019-08-02 | 电子科技大学 | The junction termination structures of lateral high voltage power device |
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