CN103888012B - Power control circuit, SPM and frequency-conversion domestic electric appliances - Google Patents
Power control circuit, SPM and frequency-conversion domestic electric appliances Download PDFInfo
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Abstract
The invention provides a kind of power control circuit, a kind of SPM and a kind of frequency-conversion domestic electric appliances.Wherein, power control circuit, including: low power consumption switch element, the arbitrary IGBT being connected in parallel in SPM manages, to constitute switch module；Switching control module, it is connected to the control chip that SPM is corresponding, the dutycycle of the signal in adjacent two cycles of the control signal of detection control chip output, and calculate the duty cycle difference of the signal in adjacent two cycles, in the case of duty cycle difference is more than or equal to predetermined threshold, make arbitrary IGBT pipe and low power consumption switch element be simultaneously in duty, in the case of duty cycle difference is less than predetermined threshold, only make low power consumption switch element in running order.Pass through technical scheme, it is possible to when adjacent two the cycle duty cycle difference differences of input signal, use different switching device, contribute to reducing the power consumption of SPM, and do not have the risk that switching device is punctured by mistake stream.
Description
Technical field
The present invention relates to power consumption control techniques field, in particular to a kind of power control circuit,
A kind of SPM and a kind of frequency-conversion domestic electric appliances.
Background technology
SPM, i.e. IPM (Intelligent Power Module), is a kind of by electric power
The power drive series products that electronics and integrated circuit technique combine.SPM is power switch device
Part and high-voltage driving circuit integrate, and in keep overvoltage, overcurrent and the fault such as overheated inspection
Slowdown monitoring circuit.On the one hand SPM receives MCU (Micro Control Unit, miniature control
Chip) control signal, on the other hand drive subsequent conditioning circuit work, by the state detection signal of system
Send MCU back to.Compared with traditional discrete scheme, SPM is with its high integration, Gao Ke
Win increasing market by advantages such as property, be particularly suitable for driving the converter of motor and various inverse
Variable power source, is to be applied to frequency control, metallurgical machinery, electric propulsion, servo-drive, frequency-conversion domestic electric appliances
A kind of desired power level electronic device.
In the related, the circuit structure of SPM 100 is as shown in Figure 1:
The VCC end of HVIC pipe 1000 as SPM 100 low-pressure area power supply just
End VDD, VDD are generally 15V；Meanwhile, inside described HVIC pipe 1000, there is bootstrapping electricity
Road, boostrap circuit structure is as follows:
VCC end and UH drive circuit 101, VH drive circuit 102, WH drive circuit 103,
UL drive circuit 104, VL drive circuit 105, the low-pressure area of WL drive circuit 106 are powered electricity
Source anode is connected.
In the HIN1 end of the described HVIC pipe 1000 U phase as described SPM 100
Brachium pontis input UHIN, internal and described UH drive circuit 101 at described HVIC pipe 1000
Input is connected；The HIN2 end of described HVIC pipe 1000 is as described SPM 100
Brachium pontis input VHIN in V phase, the internal and described VH drive circuit at described HVIC pipe 1000
The input of 102 is connected；The HIN3 end of described HVIC pipe 1000 is as described SPM
Brachium pontis input WHIN in the W phase of 100, the internal and described WH at described HVIC pipe 1000
The input of drive circuit 103 is connected.
Under the LIN1 end of the described HVIC pipe 1000 U phase as described SPM 100
Brachium pontis input ULIN, internal and described UL drive circuit 104 at described HVIC pipe 1000
Input is connected；The LIN2 end of described HVIC pipe 1000 is as described SPM 100
The lower brachium pontis input VLIN of V phase, the internal and described VL drive circuit at described HVIC pipe 1000
The input of 105 is connected；The LIN3 end of described HVIC pipe 1000 is as described SPM
The lower brachium pontis input WLIN of the W phase of 100, the internal and described WL at described HVIC pipe 1000
The input of drive circuit 106 is connected；Here, U, V, W of described SPM 100
Six tunnel inputs of three-phase receive the input signal of 0V or 5V.
The GND end of described HVIC pipe 1000 supplies as the low-pressure area of described SPM 100
Electricity power supply negative terminal COM, and with described UH drive circuit 101, described VH drive circuit 102,
Described WH drive circuit 103, described UL drive circuit 104, described VL drive circuit 105,
The low-pressure area power supply negative terminal of described WL drive circuit 106 is connected.
The VB1 end of described HVIC pipe 1000 drives with described UH in described HVIC pipe 1000 inside
The higher-pressure region power supply anode on galvanic electricity road 101 is connected, in described HVIC pipe 1000 external connection
One end of electric capacity 133, and as described SPM 100 U phase higher-pressure region power supply just
End UVB；The HO1 end of described HVIC pipe 1000 is internal with described at described HVIC pipe 1000
The outfan of UH drive circuit 101 is connected, at described HVIC pipe 1000 outside and bridge in U phase
The grid of arm IGBT pipe 121 is connected；The VS1 end of described HVIC pipe 1000 is at described HVIC
Pipe 1000 is internal to be connected, in institute with the higher-pressure region power supply negative terminal of described UH drive circuit 101
State HVIC pipe 1000 outside and the emitter-base bandgap grading of described IGBT pipe 121, the anode of FRD pipe 111, U
Descend mutually the colelctor electrode of brachium pontis IGBT pipe 124, the negative electrode of FRD pipe 114, described electric capacity 133 another
One end is connected, and as the U phase higher-pressure region power supply negative terminal of described SPM 100
UVS。
The VB2 end of described HVIC pipe 1000 drives with described VH in described HVIC pipe 1000 inside
The higher-pressure region power supply anode on galvanic electricity road 102 is connected, in described HVIC pipe 1000 external connection
One end of electric capacity 132, as the U phase higher-pressure region power supply anode of described SPM 100
VVB；The HO2 end of described HVIC pipe 1000 is internal and described VH at described HVIC pipe 1000
The outfan of drive circuit 102 is connected, at described HVIC pipe 1000 outside and brachium pontis in V phase
The grid of IGBT pipe 123 is connected；The VS2 end of described HVIC pipe 1000 is managed at described HVIC
1000 inside are connected, described with the higher-pressure region power supply negative terminal of described VH drive circuit 102
The outside emitter-base bandgap grading with described IGBT pipe 122 of HVIC pipe 1000, the anode of FRD pipe 112, V phase
The colelctor electrode of lower brachium pontis IGBT pipe 125, the negative electrode of FRD pipe 115, described electric capacity 132 another
End is connected, and as the W phase higher-pressure region power supply negative terminal of described SPM 100
VVS。
The VB3 end of described HVIC pipe 1000 is internal and described WH at described HVIC pipe 1000
The higher-pressure region power supply anode of drive circuit 103 is connected, and connects outside described HVIC pipe 1000
Connect one end of electric capacity 131, as the W phase higher-pressure region power supply of described SPM 100
Anode WVB；The HO3 end of described HVIC pipe 1000 is internal and institute at described HVIC pipe 1000
The outfan stating WH drive circuit 101 is connected, described HVIC pipe 1000 outside with in W phase
The grid of brachium pontis IGBT pipe 123 is connected；The VS3 end of described HVIC pipe 1000 is at described HVIC
Pipe 1000 is internal to be connected, in institute with the higher-pressure region power supply negative terminal of described WH drive circuit 103
State HVIC pipe 1000 outside with the emitter-base bandgap grading of described IGBT pipe 123, the anode of FRD pipe 113,
The W phase lower colelctor electrode of brachium pontis IGBT pipe 126, the negative electrode of FRD pipe 116, described electric capacity 131
The other end is connected, and as the W phase higher-pressure region power supply negative terminal of described SPM 100
WVS。
The LO1 end of described HVIC pipe 1000 is connected with the grid of described IGBT pipe 124；Described
The LO2 end of HVIC pipe 1000 is connected with the grid of described IGBT pipe 125；Described HVIC manages
The LO3 end of 1000 is connected with the grid of described IGBT pipe 126.
The emitter-base bandgap grading of described IGBT pipe 124 is connected with the anode of described FRD pipe 114, and as institute
State the U phase low reference voltage end UN of SPM 100；The emitter-base bandgap grading of described IGBT pipe 125
It is connected with the anode of described FRD pipe 115, and the V phase as described SPM 100 is low
Voltage Reference end VN；The anode phase of the emitter-base bandgap grading of described IGBT pipe 126 and described FRD pipe 116
Connect, and as the W phase low reference voltage end WN of described SPM 100.
The colelctor electrode of described IGBT pipe 121, the negative electrode of described FRD pipe 111, described IGBT manage
The colelctor electrode of 122, the negative electrode of described FRD pipe 112, the colelctor electrode of described IGBT pipe 123, institute
The negative electrode stating FRD pipe 113 is connected, and the high voltage as described SPM 100 inputs
End P, P typically meet 300V.
The effect of described HVIC pipe 1000 is:
VDD is the power supply anode of described HVIC pipe 1000, and GND is described HVIC pipe
The power supply negative terminal (VDD-GND voltage is generally 15V) of 1000.VB1 and VS1 is respectively
For the positive pole of power supply and the negative pole of U phase higher-pressure region, HO1 is the outfan of U phase higher-pressure region；VB2
With positive pole and the negative pole of the power supply that VS2 is respectively V phase higher-pressure region, HO2 is the defeated of V phase higher-pressure region
Go out end；VB3 and VS3 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO3 is W phase
The outfan of higher-pressure region；LO1, LO2, LO3 be respectively U phase, V phase, W phase low-pressure area defeated
Go out end.
By patrolling of input HIN1, HIN2, HIN3 and LIN1, the 0 of LIN2, LIN3 or 5V
Collect input signal and pass to outfan HO1, HO2, HO3 and LO1, LO2, LO3 respectively, its
In, HO1 be the logic output signal of VS1 or VS1+15V, HO2 be VS2 or VS2+15V
Logic output signal, HO3 be the logic output signal of VS3 or VS3+15V, LO1,
LO2, LO3 are the logic output signals of 0 or 15V.
Meanwhile, the input signal of same phase can not be high level simultaneously, i.e. HIN1 and LIN1,
HIN2 and LIN2, HIN3 and LIN3 can not be high level simultaneously.
A kind of preferred circuit during described SPM 100 real work is as shown in Figure 2:
External capacitor 135 between UVB and UVS；External capacitor 136 between VVB and VVS；WVB
And external capacitor 137 between WVS.Make here, described electric capacity 133,132,131 acts primarily as filtering
With, described electric capacity 135,136,137 acts primarily as storing electricity effect.
UN, VN, WN are connected, and connect one end of resistance 138 and MCU pipe 200
Pin7；Another termination COM of described resistance 138.
The Pin1 of described MCU200 is connected with the UHIN end of described SPM 100；Institute
The VHIN end of the Pin2 and described SPM 100 that state MCU200 is connected；Described
The Pin3 of MCU200 is connected with the WHIN end of described SPM 100；Described
The Pin4 of MCU200 is connected with the ULIN end of described SPM 100；Described MCU200
Pin5 be connected with the VLIN end of described SPM 100；The Pin6 of described MCU200
It is connected with the WLIN end of described SPM 100.
The duty of explanation SPM 100 as a example by U phase:
1, when the pin Pin4 of described MCU200 sends high level signal, described MCU200
Pin Pin1 must send out low level signal, signal make LIN1 be high level, HIN1 be low electricity
Flat, at this moment, LO1 output high level and HO1 output low level, thus described IGBT pipe 124
Conducting and described IGBT pipe 121 ends, VS1 voltage is about 0V；VCC is to described electric capacity 133
And described electric capacity 135 charges, when time long enough or make described electric capacity 133 and described electric capacity 135 fill
When dump energy before electricity is abundant, VB1 obtains the voltage close to 15V to VS1.
2, when the pin Pin1 of described MCU200 sends high level signal, described MCU200
Pin Pin4 must send out low level signal, signal make LIN1 be low level, HIN1 be high electricity
Flat, at this moment, LO1 output low level and HO1 export high level, thus described IGBT pipe 124
Cut-off and described IGBT pipe 121 turns on, thus VS1 voltage is about 300V, VB1 voltage and is lifted
High to about 315V, by described electric capacity 133 and the electricity of described electric capacity 135, maintain U phase high
Nip works, if the persistent period that HIN1 is high level is the shortest or described electric capacity 133 and described
The electricity of electric capacity 135 storage is abundant, and VB1 is to VS1 electricity in the work process of U phase higher-pressure region
Pressure is positively retained at more than 14V.
In actual application, particularly in the application of convertible frequency air-conditioner, MCU200 can be according to environmental change
And use the break-make of different algorithm controls SPMs 100, make frequency-changeable compressor be operated in not
Under same frequency.
The MCU200 control to compressor frequency, is by the carrier frequency at fixing 6kHz
Under, the dutycycle in regulation carrier cycle realizes, when needing compressor operating in higher frequency
Time, differing greatly of the dutycycle of each carrier cycle, as shown in Figure 3A, control signal first week
The dutycycle of phase is 80%, and the dutycycle of second round is 20%, the dutycycle in adjacent two cycles
Difference is 60%；When needing compressor operating in relatively low frequency, the dutycycle of each carrier cycle
Difference less, as shown in Figure 3 B, the dutycycle of control signal period 1 is 60%, and second
The dutycycle in cycle is 40%, and the duty cycle difference in adjacent two cycles is 20%.
When the differing greatly of dutycycle of each carrier cycle, compressor operating in high frequency, this
Time, six pieces of IGBT pipes within SPM 100 are (as IGBT pipe 121 to IGBT manages
126) need to flow through bigger electric current；When the difference of the dutycycle of each carrier cycle is less, pressure
Contracting machine works at low frequency, and at this moment, six pieces of IGBT pipe flow within SPM 100 are crossed
Electric current is less.
For the state of compressor low frequency operation, wish often to obtain low-power consumption, and use IGBT
When pipe is as on-off element, due to the smearing of IGBT pipe, cause the switching loss of on-off element
Can not be the lowest, so that the loss of SPM 100 is also impossible to be made the lowest.
If using the metal-oxide-semiconductor without smearing to substitute IGBT pipe, when compressor low frequency operation
Really switching losses and system power dissipation can be reduced, but due to the restriction of metal-oxide-semiconductor current capacity,
When compressor enters high-frequency work state, the electric current that excessive electric current can be able to bear beyond metal-oxide-semiconductor
Scope and cause metal-oxide-semiconductor to cross stream and burn, also can cause fire time serious.
In the related, the smearing by improving IGBT pipe reduces SPM
Low frequency operation loss realizes, but the production cost that this special process makes IGBT pipe is the highest, no
It is suitable for promoting at civil areas such as convertible frequency air-conditioners.
Therefore, how to reduce the SPM loss when low frequency operation, and avoid high-frequency work
Time cross stream risk, and production cost is applicable to civil area, and the technology becoming the most urgently to be resolved hurrily is asked
Topic.
Summary of the invention
It is contemplated that at least solve one of technical problem present in prior art or correlation technique.
To this end, it is an object of the present invention to propose a kind of power control circuit.
Further object is that and propose a kind of SPM.
A further object of the present invention is to propose a kind of frequency-conversion domestic electric appliances.
For achieving the above object, embodiment according to the first aspect of the invention, it is proposed that a kind of power consumption
Control circuit, including: low power consumption switch element, the arbitrary IGBT being connected in parallel in SPM
Pipe, to constitute switch module；Switching control module, is connected to the control that described SPM is corresponding
Coremaking sheet, for detecting the signal in adjacent two cycles of the control signal of described control chip output
Dutycycle, and calculate the duty cycle difference of the signal in described adjacent two cycles, at described duty ratio
Value, more than or equal in the case of predetermined threshold, makes described arbitrary IGBT pipe and described low power consumption switch
Element is simultaneously in duty, in the case of described duty cycle difference is less than predetermined threshold, only makes
Described low power consumption switch element is in running order.
Power control circuit according to an embodiment of the invention, by make low power consumption switch element and
IGBT pipe parallel connection constitutes switch module, and at the control letter of control chip input to SPM
Number adjacent two cycles signal dutycycle difference less than predetermined threshold time, only make low-power consumption open
Pass element is in running order such that it is able to avoid in prior art because of the smearing of IGBT pipe
Cause unnecessary working loss, contribute to reducing the overall power of SPM.
Meanwhile, by adjacent two week in control chip input to the control signal of SPM
When the difference of the dutycycle of the signal of phase is more than or equal to predetermined threshold so that IGBT pipe and low-power consumption
Switch element is simultaneously in duty, thus avoids low power consumption switch element to be punctured by crossing stream, helps
In the safety guaranteeing intelligence power consumption module.
Wherein, the determination mode of predetermined threshold includes but not limited to: permissible according to low power consumption switch element
The scope of the current intensity born, determines the difference of the dutycycle in adjacent two cycles of control signal
Maxima and minima, may act as the scope of predetermined threshold.Low power consumption switch element is the most permissible
For metal-oxide-semiconductor, such as NMOS tube etc., thus SPM can either be born and flow through electric current relatively
Current intensity time big, effectively reduces again switching losses owing to not having smearing and system is damaged
Consumption.
It addition, power control circuit according to the above embodiment of the present invention, it is also possible to have following additional
Technical characteristic:
According to one embodiment of present invention, described switching control module is more than or equal in described difference
In the case of predetermined threshold, described arbitrary IGBT pipe and described low power consumption switch element is made to be simultaneously in
Duty, the most described switching control module includes: signal output apparatus, is connected to described control core
Sheet, exports the first signal, Yi Ji in the case of in described difference more than or equal to predetermined threshold
Described difference is less than exporting secondary signal in the case of predetermined threshold；State control circuit, is connected to institute
State signal output apparatus, for when described state control circuit receives the first signal, control described
Arbitrary IGBT pipe and described low power consumption switch element are simultaneously in duty, and in described state
When control circuit receives secondary signal, control described low power consumption switch element in running order.
Power control circuit according to an embodiment of the invention, by inputting to SPM
The difference of dutycycle of the signal in adjacent two cycles of control signal turns with the comparison of predetermined threshold
It is changed to the first signal or secondary signal, such as: can be by this difference turning more than or equal to predetermined threshold
Being changed to high level signal, what this difference was less than predetermined threshold is converted to low level signal such that it is able to
The switching of accuracy control circuitry duty.
According to one embodiment of present invention, described signal output apparatus includes: the first signal processing electricity
Road, is connected to described control chip, and the control signal exporting described control chip processes, with
Obtain the first switching signal；Secondary signal processes circuit, is connected to described control chip, to described control
The control signal of coremaking sheet output processes, to obtain the second switching signal；First output circuit,
Described first output circuit includes: the first electric capacity, and described first electric capacity is connected to signal source and ground
Between；First switching device and the first resistance, described first switching device and described first resistant series
After, it being parallel to the two ends of described first electric capacity, described first switching device is additionally coupled to described first letter
Number process circuit, for carrying out on or off according to described first switching signal；Second output electricity
Road, described second output circuit includes: the second electric capacity, and described second electric capacity is connected to signal source and ground
Between；Second switch device and the second resistance, described second switch device and described second resistant series
After, it being parallel to the two ends of described second electric capacity, described second switch device is additionally coupled to described second letter
Number process circuit, for carrying out on or off according to described second switching signal；First voltage ratio is relatively
Device, the first input end of described first voltage comparator is connected to described first electric capacity and described first electricity
The common port of resistance, the second input input preset voltage value, for by described first output circuit output
The first voltage and preset voltage value compare, and export the first enabling signal according to comparative result,
Wherein, when the first voltage of described first output circuit output is more than or equal to preset voltage value, defeated
Go out high level, when the first voltage of described first output circuit output is less than preset voltage value, output
Low level；Second voltage comparator, the first input end of described second voltage comparator is connected to described
Second electric capacity and the common port of described second resistance, the second input input described preset voltage value, use
In by described second output circuit output the second voltage and preset voltage value compare, and according to than
Relatively result exports the second enabling signal, wherein, big at the second voltage of described second output circuit output
In or equal to preset voltage value time, export high level, described second output circuit output second electricity
When pressure is less than preset voltage value, output low level；Trigger, the first end of described trigger is connected to
The outfan of described first voltage comparator, the second end of described trigger is connected to described second voltage
The outfan of comparator, for exporting institute according to the first enabling signal received and the second enabling signal
State the first signal or described secondary signal.
Power control circuit according to an embodiment of the invention, the switching exported by signal processing circuit
Signal controls the on or off of output circuit breaker in middle device, and the on or off of switching device will
To lasting the charging and discharging of the oscillating circuit being made up of resistance and electric capacity in output circuit, thus
The voltage of resistance and electric capacity common port in output circuit is become with the charging and discharging of oscillating circuit
Change, and then by the letter of control chip input to adjacent two cycles of the control signal of SPM
Number the difference of dutycycle be converted to the big of output circuit output voltage with the comparison of predetermined threshold
Little.
The first voltage first output circuit exported by voltage comparator or the output of the second output circuit
The second voltage compare with preset voltage value, generate the first enabling signal or according to comparative result
Two enabling signals, the first enabling signal and the second enabling signal are as the input of trigger, according to touching
Send out the characteristic of device, generate the first signal or secondary signal, and then by the size of output circuit output voltage
It is converted into the first signal or secondary signal such that it is able to the switching of accuracy control circuitry duty.
Specifically, the first voltage or the second voltage compare with preset voltage value, according to comparing knot
Fruit generates the first enabling signal or the second enabling signal, and wherein, the first voltage or the second voltage are more than pre-
If during magnitude of voltage, enabling signal is high level, and the first voltage or the second voltage are less than preset voltage value
Time, enabling signal is low level.Certainly, it will be apparent to a skilled person that and generate herein
The comparative approach of the first enabling signal or the second enabling signal is not used to specifically limit.
According to one embodiment of present invention, described first signal processing circuit includes: the first time delay electricity
Road, is connected between signal source and ground, and input is connected to the outfan of described control chip, by institute
The control signal stating control chip output postpones a cycle；First logic circuit, described first logic
The first input end of circuit is connected to the outfan of described first delay circuit, described first logic circuit
The second input be connected to the outfan of described control chip, for by described control signal and delay
The described control signal of one all after date compares；First phase inverter, described first phase inverter defeated
Entering end and be connected to the outfan of described first logic circuit, the outfan of described first phase inverter is connected to
The control end of described first switching device, for carrying out instead the signal of described first logic circuit output
Phase, and use anti-phase after signal control described first switching device；Described secondary signal processes circuit
Including: the second delay circuit, it is connected between signal source and ground, input is connected to described control core
The outfan of sheet, the control signal exported by described control chip postpones a cycle；Second logic electricity
Road, the first input end of described second logic circuit is connected to the outfan of described second delay circuit,
Second input of described second logic circuit is connected to the outfan of described control chip, for by institute
The described control signal stating control signal and one all after date of delay compares；Second phase inverter, institute
The input stating the second phase inverter is connected to the outfan of described second logic circuit, described second anti-phase
The outfan of device is connected to the control end of described second switch device, for described second logic circuit
Output signal carry out anti-phase, and use anti-phase after signal control described second switch device.
Power control circuit according to an embodiment of the invention, by carrying out time delay one to input signal
Cycle, and using the control signal after time delay with without the control signal of time delay as the first logic circuit
Or second input of logic circuit, carry out logical operations, i.e. control chip is inputted to intelligent power
The signal in adjacent two cycles of the control signal of module carries out logical operations, and with logic operation result
Inversion signal control the first switching device and the on or off of second switch device, to be exported
The output voltage of circuit, the i.e. first voltage and the second voltage.
Wherein, in order to obtain preferable control signal waveform, after being exported by control chip, can pass through
Phase inverter carries out whole ripple process, and after delay circuit, it is also possible to use two instead simultaneously
Phase device carries out whole ripple process.
According to one embodiment of present invention, described first logic circuit is the gate circuit of logical AND, institute
State the gate circuit that the second logic circuit is logic XOR.
Power control circuit according to an embodiment of the invention, inputs to intelligent power mould with control chip
The cycle that in adjacent two cycles of the control signal of block, dutycycle is bigger is period 1 signal, duty
As a example by the smaller cycle is signal second round, owing to control chip inputs to SPM
The signal in adjacent two cycles of control signal is respectively as the first logic circuit or the second logic circuit
Input, therefore, when the first logic circuit is logical AND circuit, logical AND circuit output signal
Dutycycle is the dutycycle of signal second round；And when the second logic circuit is logic XOR circuit,
The dutycycle of logic XOR circuit output signal is period 1 signal and the dutycycle of signal second round
Difference.
Dutycycle in control chip input to adjacent two cycles of the control signal of SPM
Difference less than predetermined threshold time, the second switching signal dutycycle of the i.e. second logic circuit output is less than pre-
Determine threshold value, then the second voltage of the second output circuit output will be less than preset voltage value, and trigger is the
Secondary signal will be exported when two inputs are for continuing low level, and only make low-consumption power element be in work
State；Owing to the dutycycle of signal second round is the least, period 1 signal and signal second round
The difference of dutycycle is the biggest, and adjacent two of the control signal in control chip input to SPM
When the difference of the dutycycle in individual cycle is more than or equal to predetermined threshold, the first of the i.e. first logic circuit output
The duty of switching signal is smaller, then the first voltage of the first output circuit output will be less than predeterminated voltage
Value, trigger will export the first signal when first input end is for continuing low level so that IGBT manages
It is simultaneously in duty with low-power consumption element.
According to one embodiment of present invention, described first delay circuit includes: the 3rd resistance and first
Switching tube, described 3rd resistance and described first switching tube be connected between described signal source and ground, institute
The end that controls stating the first switching tube is connected to the outfan of described control chip；3rd electric capacity, is connected in parallel on
Described 3rd resistance and the two ends of described first switching tube；3rd phase inverter, described 3rd phase inverter
Input is connected to described 3rd electric capacity and the common port of described 3rd resistance, described 3rd phase inverter
Outfan is connected to the input of described first logic circuit；Described second delay circuit includes: the 4th
Resistance and second switch pipe, described 4th resistance and described second switch pipe be connected on described signal source and
Between ground, the end that controls of described second switch pipe is connected to the outfan of described control chip；4th electricity
Hold, be connected in parallel on described 4th resistance and the two ends of described second switch pipe；4th phase inverter, described
The input of four phase inverters is connected to described 4th electric capacity and the common port of described 4th resistance, and described
The outfan of four phase inverters is connected to the input of described second logic circuit.
Power control circuit according to an embodiment of the invention, is believed by the control exporting control chip
Number one cycle of time delay, the signal in adjacent two cycles of the control signal of control chip output can be entered
Row logical operations.Wherein, the control signal of control chip output controls leading of delay circuit breaker in middle pipe
Lead to or cut-off, when i.e. controlling the charging and discharging being made up of oscillating circuit in delay circuit resistance and electric capacity
Between, by regulation resistance and the size of electric capacity, the delay cycle of scalable delay circuit.
According to one embodiment of present invention, described state control circuit includes: the 3rd logic circuit,
The first input end of described 3rd logic circuit is connected to the outfan of described trigger, the second input
Be connected to the outfan of described control chip, outfan is connected to the first drive circuit, for receiving
In the case of described first signal, the control signal from described control chip is exported to the most described the
One drive circuit, in the case of receiving described secondary signal, stops from described control chip
Control signal output is to described first drive circuit；4th logic circuit, described 4th logic circuit
First input end and the second input are connected to the signal output part of described control chip, in the future
Export to described second drive circuit from the control signal of described control chip；Wherein, described first drive
Galvanic electricity road for described arbitrary IGBT pipe is driven, described second drive circuit is for described
Low power consumption switch element is driven.
Power control circuit according to an embodiment of the invention, by the first signal or secondary signal and control
The control signal of coremaking sheet output carries out logical operations, controls the duty of the first drive circuit, also
I.e. control the duty of arbitrary IGBT pipe in SPM, so that receiving first
During signal so that IGBT pipe and low power consumption switch element are simultaneously in duty, thus avoid low
Power consumption switch element is punctured by crossing stream, contributes to guaranteeing the safety of intelligence power consumption module.Receiving
During secondary signal, only make low power consumption switch element in running order such that it is able to avoid prior art
The middle smearing because of IGBT pipe and cause unnecessary working loss, contribute to reduce intelligent power
The overall power of module.
According to one embodiment of present invention, described 3rd logic circuit and described 4th logic circuit are
The gate circuit of logical AND.
Power control circuit according to an embodiment of the invention, by the gate circuit of logical AND so that nothing
How opinion input changes to the control signal of intelligent power control module, low power consumption switch element all in
Duty, and owing to an input with the logical AND gate being connected of IGBT pipe is believed for control
Number, another input is the first signal or secondary signal, thus the duty of IGBT pipe can be subject to
To the first signal and the control of secondary signal, it is achieved the switching of duty.
Embodiment according to a second aspect of the present invention, it is proposed that a kind of SPM, including as above
State the power control circuit described in any one technical scheme.
Embodiment according to a third aspect of the present invention, it is proposed that a kind of frequency-conversion domestic electric appliances, including the most above-mentioned skill
SPM described in art scheme, such as convertible frequency air-conditioner, frequency conversion refrigerator, variable-frequency washing machine etc..
By above technical scheme, it is possible to different at adjacent two the cycle duty cycle differences of input signal
Time, use different switching device, thus contribute to reducing the power consumption of SPM, and will not
There is switching device and crossed the risk that stream punctures.
The additional aspect of the present invention and advantage will part be given in the following description, and part will be from following
Description in become obvious, or recognized by the practice of the present invention.
Accompanying drawing explanation
Embodiment is retouched by the above-mentioned and/or additional aspect of the present invention and advantage from combining accompanying drawings below
Will be apparent from easy to understand in stating, wherein:
Fig. 1 shows the structural representation of the SPM in correlation technique；
Fig. 2 shows the structural representation when SPM in correlation technique carries out sequencing contro
Figure；
Fig. 3 A to Fig. 3 B show in correlation technique when SPM is carried out sequencing contro
The waveform diagram of control signal；
Fig. 4 A shows the structural representation of power control circuit according to an embodiment of the invention；
Fig. 4 B shows the structural representation of switching control module according to an embodiment of the invention；
Fig. 4 C shows the structural representation of signal processing circuit according to an embodiment of the invention；
Fig. 5 shows the structural representation of SPM according to an embodiment of the invention；
Fig. 6 shows the circuit structure signal of switching control module according to an embodiment of the invention
Figure；
Fig. 7 controls letter when showing and carry out sequencing contro according to embodiments of the invention SPM
Number waveform diagram；
Fig. 8 shows the structural representation of delay circuit according to an embodiment of the invention.
Detailed description of the invention
In order to be more clearly understood that the above-mentioned purpose of the present invention, feature and advantage, below in conjunction with attached
The present invention is further described in detail by figure and detailed description of the invention.It should be noted that not
In the case of conflict, the feature in embodiments herein and embodiment can be mutually combined.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but,
The present invention can implement to use other to be different from other modes described here, therefore, and the present invention
Protection domain be not limited to the restriction of following public specific embodiment.
One, overall structure
In the related, SPM all use IGBT pipe as switching device, a but side
Face, the smearing of IGBT pipe causes the switching loss under its low frequency too high, on the other hand, if directly
Connect use low power consumption switch element, then easily damage low power consumption switch owing to the electric current under high frequency is excessive
The unsafe conditions such as element, even initiation fire.
Therefore, in order to solve switching loss and cross many problems such as stream risk, Fig. 4 A shows
The structural representation of power control circuit according to an embodiment of the invention.
As shown in Figure 4 A, power control circuit according to an embodiment of the invention, including: low
Power consumption switch element 42, is connected in parallel to SPM (than SPM as shown in Figure 1
100) the arbitrary IGBT pipe (than 121 as shown in Figure 4 A) in, to constitute switch module
(not specifically illustrated in figure)；Switching control module 44, is connected to described SPM corresponding
Control chip, for detecting the letter in adjacent two cycles of the control signal of described control chip output
Number dutycycle, and calculate the duty cycle difference of the signal in described adjacent two cycles, at described duty
Than difference more than or equal in the case of predetermined threshold, make described arbitrary IGBT pipe and described low-power consumption
Switch element 42 is simultaneously in duty, is less than the situation of predetermined threshold at described duty cycle difference
Under, only make described low power consumption switch element 42 in running order.
By making low power consumption switch element 42 and IGBT pipe parallel connection constitute switch module, and controlling
Chip inputs the difference of the dutycycle of the signal in adjacent two cycles of the control signal to SPM
When value is less than predetermined threshold, only make low power consumption switch element 42 in running order such that it is able to keep away
Exempt from prior art causes unnecessary working loss because of the smearing of IGBT pipe, contribute to fall
The overall power of low SPM.
Meanwhile, by adjacent two week in control chip input to the control signal of SPM
When the difference of the dutycycle of the signal of phase is more than or equal to predetermined threshold so that IGBT pipe and low-power consumption
Switch element 42 is simultaneously in duty, thus avoids low power consumption switch element to be punctured by crossing stream,
Contribute to guaranteeing the safety of intelligence power consumption module.
Wherein, the determination mode of predetermined threshold includes but not limited to: according to low power consumption switch element 42
The scope of the current intensity that can bear, determines the difference of the dutycycle in adjacent two cycles of control signal
The maxima and minima of value, may act as the scope of predetermined threshold.Low power consumption switch element 42
It is specifically as follows metal-oxide-semiconductor, such as NMOS tube etc., thus SPM stream can either be born
Current intensity when overcurrent is bigger, effectively reduce owing to not there is smearing again switching losses and
System loss.
It addition, power control circuit according to the above embodiment of the present invention, it is also possible to have following additional
Technical characteristic:
Two, switching control module
In order to describe switching control module according to an embodiment of the invention 44 in detail, Fig. 4 B shows
The structural representation of switching control module according to an embodiment of the invention.
As shown in Figure 4 B, switching control module 44 according to an embodiment of the invention, described in cut
Change control module 44 in described difference more than or equal in the case of predetermined threshold, make described arbitrary
IGBT pipe and described low power consumption switch element 42 are simultaneously in duty, the most described switching control mould
Block 44 includes: signal output apparatus (not specifically illustrated in figure), is connected to described control chip,
The first signal is exported in the case of in described difference more than or equal to predetermined threshold, and described
Difference is less than exporting secondary signal in the case of predetermined threshold；State control circuit 441, is connected to institute
State signal output apparatus, for when described state control circuit 441 receives the first signal, control
Described arbitrary IGBT pipe and described low power consumption switch element 42 are simultaneously in duty, Yi Ji
When described state control circuit 441 receives secondary signal, control described low power consumption switch element 42
In running order.
By the duty by the signal in adjacent two cycles of the control signal of input to SPM
The difference of ratio and the comparison of predetermined threshold are converted to the first signal or secondary signal, such as: permissible
What this difference was more than or equal to predetermined threshold is converted to high level signal, by this difference less than predetermined threshold
Value be converted to low level signal such that it is able to the switching of accuracy control circuitry duty.
According to one embodiment of present invention, described signal output apparatus includes: the first signal processing electricity
Road 442, is connected to described control chip, at the control signal export described control chip
Reason, to obtain the first switching signal；Secondary signal processes circuit 443, is connected to described control core
Sheet, the control signal exporting described control chip processes, to obtain the second switching signal；The
One output circuit 444, described first output circuit 444 includes: the first electric capacity, described first electric capacity
It is connected between signal source and ground；First switching device and the first resistance, described first switching device with
After described first resistant series, being parallel to the two ends of described first electric capacity, described first switching device is also
It is connected to described first signal processing circuit 442, for turning on according to described first switching signal
Or cut-off；Second output circuit 445, described second output circuit 445 includes: the second electric capacity, institute
State the second electric capacity to be connected between signal source and ground；Second switch device and the second resistance, described second
After switching device and described second resistant series, it is parallel to the two ends of described second electric capacity, described second
Switching device is additionally coupled to described secondary signal and processes circuit 443, for according to described second switching letter
Number carry out on or off；First voltage comparator 446, the of described first voltage comparator 446
One input is connected to described first electric capacity and the common port of described first resistance, the second input input
Preset voltage value, for the first voltage exported by described first output circuit 444 and preset voltage value
Compare, and export the first enabling signal according to comparative result, wherein, at described first output electricity
When first voltage of road 444 output is more than or equal to preset voltage value, export high level, described the
When first voltage of one output circuit 444 output is less than preset voltage value, output low level；Second electricity
Pressure comparator 447, the first input end of described second voltage comparator 447 is connected to described second electricity
Hold and the common port of described second resistance, the second input input described preset voltage value, for by institute
The second voltage and the preset voltage value of stating the second output circuit 445 output compare, and according to comparing
Result exports the second enabling signal, wherein, at the second voltage of described second output circuit 445 output
During more than or equal to preset voltage value, export high level, in described second output circuit 445 output
When second voltage is less than preset voltage value, output low level；Trigger 448, described trigger 448
The first end be connected to the outfan of described first voltage comparator 446, the of described trigger 448
Two ends are connected to the outfan of described second voltage comparator 447, for opening according to receive first
Dynamic signal and the second enabling signal export described first signal or described secondary signal.
The switching signal exported by signal processing circuit control output circuit breaker in middle device conducting or
Cut-off, the on or off of switching device will give the vibration being made up of in output circuit resistance and electric capacity
Lasting the charging and discharging of circuit, so that resistance and the electricity of electric capacity common port in output circuit
Pressure changes with the charging and discharging of oscillating circuit, and then inputs control chip to SPM
The comparison of difference and predetermined threshold of dutycycle of signal in adjacent two cycles of control signal
Be converted to the size of output circuit output voltage.
The first voltage first output circuit 444 exported by voltage comparator or the second output circuit
Second voltage of 445 outputs compares with preset voltage value, generates the first startup according to comparative result
Defeated as trigger 448 of signal or the second enabling signal, the first enabling signal and the second enabling signal
Enter end, according to the characteristic of trigger 448, generate the first signal or secondary signal, and then will output electricity
The size of road output voltage is converted into the first signal or secondary signal such that it is able to accuracy control circuitry work
Make the switching of state.
Specifically, the first voltage or the second voltage compare with preset voltage value, according to comparing knot
Fruit generates the first enabling signal or the second enabling signal, and wherein, the first voltage or the second voltage are more than pre-
If during magnitude of voltage, enabling signal is high level, and the first voltage or the second voltage are less than preset voltage value
Time, enabling signal is low level.Certainly, it will be apparent to a skilled person that and generate herein
The comparative approach of the first enabling signal or the second enabling signal is not used to specifically limit.
Signal processing circuit according to an embodiment of the invention is described in detail below in conjunction with Fig. 4 C,
Fig. 4 C shows the structural representation of signal processing circuit according to an embodiment of the invention.
As shown in Figure 4 C, signal processing circuit according to an embodiment of the invention, including the first signal
Processing circuit 442 and secondary signal processes 443 circuit, described first signal processing circuit 442 is wrapped
Including: the first delay circuit 442A, be connected between signal source and ground, input is connected to described control
The outfan of coremaking sheet, the control signal exported by described control chip postpones a cycle；First patrols
Collecting circuit 442B, the first input end of described first logic circuit 442B is connected to described first time delay
The outfan of circuit 442A, second input of described first logic circuit 442B is connected to described
The outfan of control chip, for the described control letter by described control signal and one all after date of delay
Number compare；First phase inverter 442C, the input of described first phase inverter 442C is connected to institute
Stating the outfan of the first logic circuit 442B, the outfan of described first phase inverter 442C is connected to
The control end of described first switching device, for the signal to described first logic circuit 442B output
Carry out anti-phase, and use anti-phase after signal control described first switching device；At described secondary signal
Reason circuit 443 includes: the second delay circuit 443A, is connected between signal source and ground, input
Being connected to the outfan of described control chip, the control signal exported by described control chip postpones one
Cycle；Second logic circuit 443B, the first input end of described second logic circuit 443B is connected to
The outfan of described second delay circuit 443A, second input of described second logic circuit 443B
End is connected to the outfan of described control chip, for by described control signal and one all after date of delay
Described control signal compare；Second phase inverter 443C, described second phase inverter 443C's is defeated
Enter end and be connected to the outfan of described second logic circuit 443B, described second phase inverter 443C's
Outfan is connected to the control end of described second switch device, for described second logic circuit
443B output signal carry out anti-phase, and use anti-phase after signal control described second switch device
Part.
By input signal being carried out one cycle of time delay, and by the control signal after time delay with without
The control signal of time delay is as the first logic circuit 442B or the input of the second logic circuit 443B
End, carries out logical operations, i.e. control chip is inputted the adjacent of the control signal to SPM
The signal in two cycles carries out logical operations, and opens with the inversion signal control first of logic operation result
Close device and the on or off of second switch device, to obtain the output voltage of output circuit, i.e. the
One voltage and the second voltage.
Wherein, in order to obtain preferable control signal waveform, after being exported by control chip, can pass through
Phase inverter carries out whole ripple process, and after delay circuit, it is also possible to use two instead simultaneously
Phase device carries out whole ripple process.
According to one embodiment of present invention, described first logic circuit 442B is the door electricity of logical AND
Road, described second logic circuit 443B is the gate circuit of logic XOR.
Input to dutycycle in adjacent two cycles of the control signal of SPM with control chip
The bigger cycle is period 1 signal, as a example by duty smaller cycle is signal second round, by
Signal in control chip input to adjacent two cycles of the control signal of SPM is made respectively
It is the first logic circuit 442B or the input of the second logic circuit 443B, therefore, patrols first
When volume circuit 442B is logical AND circuit, the dutycycle of logical AND circuit output signal is second round
The dutycycle of signal；And when the second logic circuit 443B is logic XOR circuit, logic XOR electricity
The dutycycle of road output signal is the difference of the dutycycle of period 1 signal and signal second round.
Dutycycle in control chip input to adjacent two cycles of the control signal of SPM
Difference less than predetermined threshold time, i.e. second logic circuit 443B output the second switching signal dutycycle
Less than predetermined threshold, then the second voltage of the second output circuit 445 output will less than preset voltage value,
Trigger 448 will export secondary signal when the second input is for continuing low level, only make low-power consumption merit
Rate element 42 is in running order；Owing to the dutycycle of signal second round is the least, the period 1 believes
Number the biggest with the difference of the dutycycle of signal second round, and input to SPM at control chip
Control signal adjacent two cycles dutycycle difference more than or equal to predetermined threshold time, i.e. first
The duty of the first switching signal of logic circuit 442B output is smaller, then the first output circuit 444
First voltage of output will be less than preset voltage value, and trigger 448 is the lowest electricity at first input end
The first signal will be exported at ordinary times so that IGBT pipe and low-power consumption element 42 are simultaneously in work shape
State.
According to one embodiment of present invention, described first delay circuit 442A includes: the 3rd resistance
With the first switching tube, described 3rd resistance and described first switching tube are connected on described signal source and ground
Between, the end that controls of described first switching tube is connected to the outfan of described control chip；3rd electric capacity,
It is connected in parallel on described 3rd resistance and the two ends of described first switching tube；3rd phase inverter, described 3rd anti-
The input of phase device is connected to described 3rd electric capacity and the common port of described 3rd resistance, described 3rd anti-
The outfan of phase device is connected to the input of described first logic circuit 442B；Described second time delay electricity
Road 443A includes: the 4th resistance and second switch pipe, described 4th resistance and described second switch pipe
Being connected between described signal source and ground, the control end of described second switch pipe is connected to described control core
The outfan of sheet；4th electric capacity, is connected in parallel on described 4th resistance and the two ends of described second switch pipe；
4th phase inverter, the input of described 4th phase inverter is connected to described 4th electric capacity and described 4th electricity
The common port of resistance, the outfan of described 4th phase inverter is connected to described second logic circuit 443B's
Input.
By one cycle of control signal time delay that control chip is exported, can be to control chip output
The signal in adjacent two cycles of control signal carries out logical operations.Wherein, the control of control chip output
Signal processed controls the on or off of delay circuit breaker in middle pipe, i.e. control in delay circuit by resistance and
The charging and discharging time of electric capacity composition oscillating circuit, by regulation resistance and the size of electric capacity, adjustable
The delay cycle of joint delay circuit.
According to one embodiment of present invention, described state control circuit 441 includes: the 3rd logic electricity
Road (not shown), the first input end of described 3rd logic circuit is connected to described trigger 448
Outfan, the second input is connected to the outfan of described control chip, outfan is connected to first
Drive circuit, in the case of receiving described first signal, by from described control chip
Control signal output is to described first drive circuit, in the case of receiving described secondary signal, and resistance
Only the control signal from described control chip exports to described first drive circuit；4th logic circuit
(not shown), first input end and second input of described 4th logic circuit are connected to institute
State the signal output part of control chip, for exporting the control signal from described control chip to institute
State the second drive circuit；Wherein, described first drive circuit is for carrying out described arbitrary IGBT pipe
Drive, described second drive circuit is used for being driven described low power consumption switch element.
Logical operations is carried out by the control signal of the first signal or secondary signal and control chip output,
Control the duty of the first drive circuit, namely control arbitrary IGBT pipe in SPM
Duty, so that when receiving the first signal so that IGBT pipe and low power consumption switch unit
Part 42 is simultaneously in duty, thus avoids low power consumption switch element to be punctured by crossing stream, contributes to
Guarantee the safety of intelligence power consumption module.When receiving secondary signal, only make low power consumption switch element
42 is in running order such that it is able to avoids causing because of the smearing of IGBT pipe in prior art
Unnecessary working loss, contributes to reducing the overall power of SPM.
According to one embodiment of present invention, described 3rd logic circuit and described 4th logic circuit are
The gate circuit of logical AND.
By the gate circuit of logical AND so that no matter input the control signal to intelligent power control module
How changing, low power consumption switch element 42 is all in duty, and due to the phase with IGBT pipe
One input of logical AND gate even is control signal, and another input is the first signal or second
Signal, thus the duty of IGBT pipe can be controlled by the first signal and secondary signal, it is achieved
The switching of duty.
Embodiment according to a second aspect of the present invention, it is proposed that a kind of SPM, including as above
State the power control circuit described in any one technical scheme.
Embodiment according to a third aspect of the present invention, it is proposed that a kind of frequency-conversion domestic electric appliances, including the most above-mentioned skill
SPM described in art scheme, such as convertible frequency air-conditioner, frequency conversion refrigerator, variable-frequency washing machine etc..
By above technical scheme, it is possible to different at adjacent two the cycle duty cycle differences of input signal
Time, use different switching device, thus contribute to reducing the power consumption of SPM, and will not
There is switching device and crossed the risk that stream punctures.
The circuit structure diagram of embodiments of the invention is described in detail below in conjunction with Fig. 5 to Fig. 8.
Fig. 5 shows the structural representation of SPM according to an embodiment of the invention.
As it is shown in figure 5, SPM 4100 according to an embodiment of the invention, Fig. 5 be by
Circuit diagram after output gating circuit 4400 simplification, output gating circuit 4400 is switching control mould
Block.
The power positive end VCC end of output gating circuit 4400 is as described SPM 4100
Low-pressure area power supply anode VDD, VDD is generally 15V；Described output gating circuit 4400
First input end HIN1 as brachium pontis input in the U phase of described SPM 4100
UHIN；Second input HIN2 of described output gating circuit 4400 is as described intelligent power mould
Brachium pontis input VHIN in the V phase of block 4100；3rd input of described output gating circuit 4400
End HIN3 is as brachium pontis input WHIN in the W phase of described SPM 4100；Described
The four-input terminal LIN1 of output gating circuit 4400 is as the U of described SPM 4100
Descend brachium pontis input ULIN mutually；5th input LIN2 conduct of described output gating circuit 4400
The lower brachium pontis input VLIN of the V phase of described SPM 4100；Described output gating circuit
The 6th input LIN3 of 4400 is as the W phase lower brachium pontis input of described SPM 4100
End WLIN；The power supply negative terminal GND of described output gating circuit 4400 is as described intelligence merit
The low-pressure area power supply negative terminal COM of rate module 4100.
The U phase higher-pressure region power supply anode VB1 of described output gating circuit 4400 and electric capacity
One end of 4133 is connected, and as the U phase higher-pressure region power supply of described SPM 4100
Anode UVB；The U phase higher-pressure region power supply negative terminal VS1 of described output gating circuit 4400 with
The other end of described electric capacity 4133 is connected, and as the U phase high pressure of described SPM 4100
District power supply negative terminal UVS.
The V phase higher-pressure region power supply anode VB2 of described output gating circuit 4400 and electric capacity
One end of 4132 is connected, and as the V phase higher-pressure region power supply of described SPM 4100
Anode VVB；The V phase higher-pressure region power supply negative terminal VS2 of described output gating circuit 4400 with
The other end of described electric capacity 4132 is connected, and as the V phase high pressure of described SPM 4100
District power supply negative terminal VVS.
The W phase higher-pressure region power supply anode VB3 of described output gating circuit 4400 and electric capacity
One end of 4131 is connected, and as the W phase higher-pressure region power supply of described SPM 4100
Anode WVB；The W phase higher-pressure region power supply negative terminal VS3 of described output gating circuit 4400 with
The other end of described electric capacity 4131 is connected, and the W phase as described SPM 4100 is high
Nip power supply negative terminal WVS.
The UHO end of described output gating circuit 4400 is connected with the grid of IGBT pipe 4121, institute
The colelctor electrode stating IGBT pipe 4121 is connected with the negative electrode of FRD pipe 4111 and connects described intelligent power
The ceiling voltage point P end of module 4100, the emitter-base bandgap grading of described IGBT pipe 4121 is managed with described FRD
The anode of 4111 is connected and connects the UVS end of described SPM 4100.
The VHO end of described output gating circuit 4400 is connected with the grid of IGBT pipe 4122, institute
The colelctor electrode stating IGBT pipe 4122 is connected with the negative electrode of FRD pipe 4112 and connects described intelligent power
The ceiling voltage point P end of module 4100, the emitter-base bandgap grading of described IGBT pipe 4122 is managed with described FRD
The anode of 4112 is connected and connects the VVS end of described SPM 4100.
The VHO end of described output gating circuit 4400 is connected with the grid of IGBT pipe 4123, institute
The colelctor electrode stating IGBT pipe 4123 is connected with the negative electrode of FRD pipe 4113 and connects described intelligent power
The ceiling voltage point P end of module 4100, the emitter-base bandgap grading of described IGBT pipe 4123 is managed with described FRD
The anode of 4113 is connected and connects the WVS end of described SPM 4100.
The ULO1 end of described SPM 4100 is connected with the grid of IGBT pipe 4124, institute
The grid of the ULO2 end and NMOS tube 4114 of stating SPM 4100 is connected；Described
The colelctor electrode of IGBT pipe 4124 is connected with the drain electrode of described high pressure NMOS pipe 4114 and connects described intelligence
The UVS end of energy power model 4100, the emitter-base bandgap grading of described IGBT pipe 4124 and described high pressure
The substrate of NMOS tube 4114 is connected with source electrode and connects the UN end of described SPM 4100.
The VLO1 end of described SPM 4100 is connected with the grid of IGBT pipe 4125, institute
The grid of the VLO2 end and NMOS tube 4115 of stating SPM 4100 is connected；Described
The colelctor electrode of IGBT pipe 4125 is connected with the drain electrode of described high pressure NMOS pipe 4115 and connects described intelligence
The VVS end of energy power model 4100, the emitter-base bandgap grading of described IGBT pipe 4124 and described high pressure
The substrate of NMOS tube 4115 is connected with source electrode and connects the VN end of SPM 4100.
The WLO1 end of described SPM 4100 is connected with the grid of IGBT pipe 4125, institute
The grid of the WLO2 end and NMOS tube 4115 of stating SPM 4100 is connected；Described
The colelctor electrode of IGBT pipe 4125 is connected with the drain electrode of described high pressure NMOS pipe 4115 and meets described institute
State the WVS end of SPM 4100, the emitter-base bandgap grading of described IGBT pipe 4125 and described high pressure
The substrate of NMOS tube 4115 is connected with source electrode and meets the WN of described SPM 4100
End.
The effect of described output gating circuit 4400 is:
Adjacent two cycles when the control signal entering described output gating circuit 4400 input
When dutycycle gap is bigger, the signal of LIN1 can control the output of ULO1 and ULO2 simultaneously,
The signal of LIN2 can control the output of VLO1 and VLO2 simultaneously, and the signal of LIN3 can control simultaneously
The output of WLO1 and WLO2；When the control letter entering described output gating circuit 4400 input
Number the dutycycle gap in adjacent two cycles less time, the signal of LIN1 controls the defeated of ULO2
Going out, the signal of LIN2 controls the output of VLO2, and the signal of LIN3 controls the output of WLO2.
The signal of HIN1 controls the output of UHO, and the signal of HIN2 controls VHO's
Output, the signal of HIN3 controls the output of WHO.
Because accounting for of adjacent two cycles of the control signal of described output gating circuit 4400 input
Empty ratio, when bigger, represent and needs described SPM 4100 to produce break-make speed faster
Degree, i.e. need described SPM 4100 produce strengthen current capacity, at this moment LIN1,
The signal of LIN3, LIN3 control the most simultaneously ULO1 and ULO2, VLO1 and VLO2,
WLO1 and WLO2, under Synchronization Control, the IGBT of brachium pontis manages and the break-make of high pressure NMOS pipe, makes
Described SPM 4100 is provided that enough current capacities；Described output gating circuit 4400
When the dutycycle gap in adjacent two cycles of the control signal of input is less, represents and need described intelligence
The break-make speed of energy power model 4100 is the highest, and i.e. having only to described SPM 4100 provides
Less current capacity, at this moment the signal of LIN1, LIN3, LIN3 the most only control ULO2,
VLO2, WLO2, only control the break-make of the high pressure NMOS pipe of lower brachium pontis, described intelligence at this moment
Although the lower brachium pontis current capacity of power model 4100 is relatively low, switching speed faster can be produced,
Although upper brachium pontis still uses IGBT pipe as on-off element, there is smearing, but because of lower bridge
Arm reliable turn-off, even if upper brachium pontis not yet turns off can not produce current loop again, the most permissible
Reduce the purpose of system power dissipation.
Fig. 6 shows the electrical block diagram of switching control module according to an embodiment of the invention.
As shown in Figure 6, the circuit of switching control module according to an embodiment of the invention, Fig. 6 be by
Circuit diagram after output gating circuit 4400 (switching control module) materialization.
The present embodiment is that the input signal to WLIN detects, by the duty to WLIN signal
The judgement of ratio, switches over outfan, because ULIN, VLIN, WLIN signal is the most right
Claim, so, carry out the method that the detects side with WLIN by the input signal of ULIN, VLIN
Method.
The low-pressure area power supply anode VCC of described output gating circuit 4400 and current source 5206
Negative terminal, the negative terminal of current source 5211, the negative terminal of current source 5306, current source 5311 negative
End, the low-pressure area power supply anode of UH drive circuit 5001, VH drive circuit 5001 low
Nip power supply anode, the low-pressure area power supply anode of WH drive circuit 5003, UL drive
The low-pressure area power supply anode of circuit 5004, the low-pressure area power supply of VL drive circuit 5005
Anode, the low-pressure area power supply anode of WL drive circuit 5006 are connected.
WLIN connects the input of not gate 5201, the input of not gate 5202；Described not gate 5201
Output termination not gate 5209 input；The output termination delay circuit of described not gate 5202
The input of 5217, the input of the output termination not gate 5207 of described delay circuit 5217；Institute
State the power supply that delay circuit 5217 is made up of VCC and GND to power；The output of described not gate 5207
The input of termination not gate 5208；The input of the output termination not gate 5209 of described not gate 5201
End；The output termination of described not gate 5208 and one of them input of door 5210, described not gate
Described another input with door 5210 of output termination of 5209；The described output with door 5210
The input of termination not gate 5217；The grid of the output termination NMOS tube 5213 of described not gate 5217
Pole；The substrate of described NMOS tube 5213 is connected with source electrode and meets GND；Described NMOS tube
The drain electrode of 5213 connects one end of resistance 5212；Another of described resistance 5212 terminates described electric current
The anode in source 5211, one end of electric capacity 5214 and the positive input terminal of voltage comparator 5216；Described
The other end of electric capacity 5214 is connected with GND；The anode of voltage source 5215 and described voltage comparator
The negative input end of 5216 is connected, and the negative terminal of described voltage source 5215 is connected with GND；Described voltage
The outfan of comparator 5216 is connected with the R end of rest-set flip-flop 5401.
WLIN connects the input of not gate 5301, the input of not gate 5302；Described not gate 5301
Output termination not gate 5309 input；The output termination delay circuit of described not gate 5202
The input of 5217, the input of the output termination not gate 5207 of described delay circuit 5217；Institute
State the power supply that delay circuit 5217 is made up of VCC and GND to power；The output of described not gate 5307
The input of termination not gate 5308；The input of the output termination not gate 5309 of described not gate 5301
End；One of them input of the output termination XOR gate 5310 of described not gate 5308, described not gate
Described another input with door 5310 of output termination of 5309；The described output with door 5310
The input of termination not gate 5317；The grid of the output termination NMOS tube 5313 of described not gate 5317
Pole；The substrate of described NMOS tube 5313 is connected with source electrode and meets GND；Described NMOS tube
The drain electrode of 5313 connects one end of resistance 5312；Another of described resistance 5312 terminates described electric current
The anode in source 5311, one end of electric capacity 5314 and the positive input terminal of voltage comparator 5316；Described
The other end of electric capacity 5314 is connected with GND；The anode of voltage source 5315 and described voltage comparator
The negative input end of 5316 is connected, and the negative terminal of described voltage source 5315 is connected with GND；Described voltage
The outfan of comparator 5316 is connected with the S end of rest-set flip-flop 5401.
The Q end of described rest-set flip-flop 5401 with door 5115 and door 5114 and door 5125 and
Door 5124, one end with door 5135, with door 5124 are connected.
UHIN is connected with the input of described UH drive circuit；VHIN and described VH drives electricity
The input on road is connected；WHIN is connected with the input of described WH drive circuit；ULIN and institute
State and be connected with the other end of door 5115 and described and door 5114 the other end；VLIN and described and door
The other end of 5125 is connected with described and door 5124 the other end；WLIN is with described and door 5135
The other end is connected with described and door 5134 the other end；Described with the outfan of door 5115 with described
The input of UL drive circuit 15014 is connected；Described drive with described UL with the outfan of door 5114
The input on galvanic electricity road 25024 is connected；The described outfan with door 5125 drives electricity with described VL
The input on road 15015 is connected；The described outfan with door 5124 and described VL drive circuit 2
The input of 5025 is connected；
Described and the outfan of door 5135 with described WL drive circuit 15016 input is connected；
Described and the outfan of door 5134 with described WL drive circuit 25026 input is connected；
The low-pressure area power supply negative terminal of described UH drive circuit 5001, described VH drive circuit
The low-pressure area power supply negative terminal of 5001, the low-pressure area power supply of described WH drive circuit 5003
Negative terminal, the low-pressure area power supply negative terminal of described UL drive circuit 5004, described VL drive circuit
The low-pressure area power supply negative terminal of 5005, the low-pressure area power supply of described WL drive circuit 5006
Negative terminal is connected, and connects GND.
The VB1 end of described output gating circuit 4400 and the high pressure of described UH drive circuit 5001
District's power supply anode is connected；The VS1 end of described output gating circuit 4400 drives with described UH
The higher-pressure region power supply negative terminal of circuit 5001 is connected.
The VB2 end of described output gating circuit 4400 and the high pressure of described VH drive circuit 5002
District's power supply anode is connected；The VS2 end of described output gating circuit 4400 drives with described VH
The higher-pressure region power supply negative terminal of circuit 5002 is connected.
The VB3 end of described output gating circuit 4400 and the high pressure of described WH drive circuit 5003
District's power supply anode is connected；The VS3 end of described output gating circuit 4400 drives with described WH
The higher-pressure region power supply negative terminal of circuit 5003 is connected.
Wherein, the function of described UH drive circuit 5001 drives electricity with the described UH of prior art
Road 101 is identical, the function of described VH drive circuit 5002 and the described VH of prior art
Drive circuit 102 is identical, the function of described WH drive circuit 5003 and the institute of prior art
State WH drive circuit 103 identical, the function of described UL drive circuit 15014 and existing skill
The described UL drive circuit 104 of art is identical, the function of described VL drive circuit 15015 with
The described VL drive circuit 105 of prior art is identical, described WL drive circuit 15016
Function is identical with the described WL drive circuit 106 of prior art.
Concrete oscillogram below in conjunction with Fig. 7 illustrates the operation principle of the present embodiment.
From Fig. 3 A and Fig. 3 B it can be seen that when compressor operating is at high frequency, adjacent two cycles
Between the difference of dutycycle be 60%, when compressor operating is at low frequency, accounting for during adjacent two week
The difference of empty ratio is 20%, and this specific embodiment carries out parameter designing according to conditions above, according to difference
Driven compressor algorithm, it is possible to just can embody compressor operating after being spaced several cycle in difference
Difference between frequency lower cycle dutycycle, at this moment, adjusts accordingly according to the design principle of the present embodiment
Whole.
Fig. 7 controls letter when showing and carry out sequencing contro according to embodiments of the invention SPM
Number waveform diagram.
As it is shown in fig. 7, the input signal of WLIN is through described delay circuit 5217, make signal delay
One cycle arrives A203, arrives A211 through described not gate 5208, thus at A211 point
To the signal postponing a cycle than WLIN；And the input signal of WLIN is through described not gate
5201 and described not gate 5209 after, obtain signal on all four with WLIN, through described and door
After 5210, when compressor operating is at high frequency, at the signal that A206 obtains 20% dutycycle, work as pressure
When contracting machine is operated in low frequency, obtain the signal of 40% dutycycle at A206.
The input signal of WLIN, through described delay circuit 5317, makes one cycle of signal delay arrive
A303, arrives A311 through described not gate 5308, thus is obtaining prolonging than WLIN at A311 point
The signal in a slow cycle；And the input signal of WLIN is through described not gate 5301 and described not gate
After 5309, obtain signal on all four with WLIN, after described XOR gate 5310, work as pressure
When contracting machine is operated in high frequency, obtain the signal of 60% dutycycle at A306, when compressor operating is low
Frequently, time, the signal of 20% dutycycle is obtained at A306.
The signal of A206, after described not gate 5217 is anti-phase, arrives by described current source 5211, institute
State resistance 5212, described NMOS tube 5213, the charging circuit of described electric capacity 5214 composition, when
Compressor operating is when high frequency, and the time having 20% cycle is that electric capacity 5214 charges, when compressor work
Making when low frequency, the time having 40% cycle is that electric capacity 5214 charges.
Design suitable magnitude of voltage VA209 for described voltage source 5215, make described electric capacity 5214 need
The charging interval in 30% cycle just can make the voltage of described electric capacity 5214 reach this value；Then work as compressor
When being operated in low frequency, the outfan of described voltage comparator 5216 there will be high level, the most always
Keep low level.
The signal of A306, after described not gate 5317 is anti-phase, arrives by described current source 5311, institute
State resistance 5312, described NMOS tube 5313, the charging circuit of described electric capacity 5314 composition, when
Compressor operating is when high frequency, and the time having 60% cycle is that electric capacity 5214 charges, when compressor work
Making when low frequency, the time having 20% cycle is that electric capacity 5214 charges.
Design suitable magnitude of voltage VA309 for described voltage source 5315, make described electric capacity 5314 need
The charging interval in 30% cycle just can make the voltage of described electric capacity 5314 reach this value；Then work as compressor
When being operated in high frequency, the outfan of described voltage comparator 5316 there will be high level, the most always
Keep low level.
I.e. when compressor from be operated in low frequency become being operated in high frequency time, the Q of described rest-set flip-flop is defeated
Go out end become high level and keep；When compressor from be operated in high frequency become being operated in low frequency time, described
The Q output of rest-set flip-flop becomes low level and keeps.
When the Q output of described rest-set flip-flop is high level, described and door 5115, described and door
5125, the described output with door 5135 respectively with the input signal one of ULIN, VLIN, WLIN
Cause, i.e. the signal of ULO1, VLO1, WLO1 respectively with the letter of ULO2, VLO2, WLO2
As number, controlled by ULIN, VLIN, WLIN；And when the Q output of described rest-set flip-flop
During for low level, described and door 5115, described and door 5125, the described output holding with door 5135
Signal in low level, i.e. ULO1, VLO1, WLO1 is maintained at low level, only ULO2,
The signal of VLO2, WLO2 is controlled by ULIN, VLIN, WLIN；Thus reached when compression
Machine is operated in IGBT and the low power consumption control element break-make simultaneously of high frequency brachium pontis at present, when compressor work
Make the purpose only having low power consumption control element break-make at low frequency brachium pontis at present.
Further illustrate the parameter designing of each Primary Component of the present invention below in conjunction with Fig. 8, Fig. 8 shows
The structural representation of delay circuit according to an embodiment of the invention.
Described delay circuit 5217 may be designed to identical with described delay circuit 5317, to postpone
Illustrating as a example by circuit 5217, described delay circuit 5217 is by 20 unit series connection as shown in Figure 8
Form.
A2011 connects the grid of NMOS tube 5203；The substrate of described NMOS tube 5203 and source electrode
It is connected and meets GND；One end of the drain electrode connecting resistance 5204 of described NMOS tube 5203, described electricity
Another termination anode of described current source 5206, one end of electric capacity 5205, not gate of resistance 5204
The input of 5207；The output termination A2031 of described not gate 5207.
Described current source 5206, described resistance 5204, described NMOS tube 5203, described electric capacity
5205, the value of described not gate 5207.
Threshold value Vth of described not gate 5207 is designed as 5V, and capacitance Cd of described electric capacity 5205 sets
It is calculated as 100pF, the electric current Id of the most described current source 5206, time for the charging of described electric capacity 5205
There is following relation in td, the voltage Vd of described electric capacity 5205:
As td=0.05 × 1/6kHz, Vd reaches Vth=5V, substitutes into above formula and obtains Id=60uA.
The breadth length ratio of described NMOS tube 5203 is designed to the least, such as 2 μm/1 μm, then described
When NMOS tube 5203 turns on and flows through the electric current of uA level, its conducting resistance almost can be ignored,
If described NMOS tube 5203 when turning on described electric capacity 5205 by the electric discharge of described resistance 5204 time
Between be tf, there is following relation with resistance Rd of described resistance:
As tf=0.05 × 1/6kHz, Vd drops to Vth=5V, VCC and is generally 15V, substitutes into above formula
Obtain Rd=15k Ω.
Because unit time delay 0.05 cycle, therefore more than 20 unit can be with 1 week of time delay
Phase.
Described current source 5211, described resistance 5212, described NMOS tube 5213, described electric capacity
5214, the value of described voltage source 5215 may be designed to respectively with described current source 5311, described electricity
Resistance 5312, described NMOS tube 5313, described electric capacity 5314, the value of described voltage source 5315
Identical, current source 5211, described resistance 5212, described NMOS tube described in following description
5213, described electric capacity 5214, the value of described voltage source 5215:
Value Vthm of described current source 5215 is designed to 5V, capacitance Cm of described electric capacity 5214
Be designed as 100pF, the electric current Im of the most described current source 5211, for the charging of described electric capacity 5214 time
Between tm, the voltage Vm of described electric capacity 5214 there is following relation:
As td=0.3 × 1/6kHz, Vm reaches Vthm=5V, substitutes into above formula and obtains Id=10uA；
The breadth length ratio of described NMOS tube 5213 is designed to the least, such as 1 μm/0.5 μm, then described
When NMOS tube 5213 turns on and flows through the electric current of uA level, its conducting resistance almost can be ignored,
Resistance Rm of described resistance may be designed to 100 Ω, then set described NMOS tube 5213 and turn on time institute
State electric capacity 5205 the shortest by the time of described resistance 5212 electric discharge, the most several millesimal weeks
Phase, it is ensured that such as the rapid discharge waveform of Fig. 7.
Technical scheme being described in detail above in association with accompanying drawing, the present invention proposes a kind of power consumption
Control circuit, a kind of SPM and a kind of frequency-conversion domestic electric appliances, it is possible to achieve techniques below effect:
When SPM needs to produce bigger driving electric current, SPM can provide
There is the on-off element of enough current capacities, during because system needs big driving electric current, always wish
Hope and quickly obtain enough energy and power consumption is paid close attention to less, even if so switching loss now relatively
Height, also has no effect on overall system performance evaluation.
When SPM needs less driving electric current, SPM can provide switch
Less on-off element is lost, during because system needs little driving electric current, it is always desirable to obtain less
Energy consumption, so, in the case of current capacity meets system requirements, less switching loss can
Improve overall system performance evaluation.
When small area analysis, the SPM of the present invention only can switch to that switching loss is more in time
The pattern of little low-power consumption element manipulation, can effectively reduce the energy consumption of SPM；And at big electricity
During stream, the SPM of the present invention can switch to again the break-make with larger current ability in time
Element (IGBT pipe) and there is on-off element (low-power consumption element) work simultaneously of smaller current ability
The pattern made, it is to avoid the element damage caused because electric current is excessive, is effectively improved the strong of SPM
Strong property, it is to avoid because pursuing low energy consumption, SPM caused that stream punctured waits and negatively affect, thus
The combination property making SPM is improved.
Use high pressure NMOS pipe as on-off element during small area analysis, high pressure can be directly utilized
The parasitic diode of NMOS tube self, as anti-paralleled diode, makes lower brachium pontis without re-using
FRD manages, and in terms of on-off element, compared with prior art, cost increases very limited the present invention；
Additionally, switch different on-off elements according to different current capacity demands, no longer to big current switching
Element proposes harsh switching characteristic requirement, it is possible to be realized with a low cost under the small area analysis of SPM
Little energy consumption.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for
For those skilled in the art, the present invention can have various modifications and variations.All essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement etc. made, should be included in the present invention
Protection domain within.
Claims (10)
1. a power control circuit, it is characterised in that including:
Low power consumption switch element, the arbitrary IGBT being connected in parallel in SPM manages, and opens to constitute
Close assembly；
Switching control module, is connected to the control chip that described SPM is corresponding, is used for detecting
The dutycycle of the signal in adjacent two cycles of the control signal of described control chip output, and calculate institute
State the duty cycle difference of the signal in adjacent two cycles, at described duty cycle difference more than or equal to predetermined
In the case of threshold value, described arbitrary IGBT pipe and described low power consumption switch element is made to be simultaneously in work
State, in the case of described duty cycle difference is less than predetermined threshold, only makes described low power consumption switch unit
Part is in running order.
Power control circuit the most according to claim 1, it is characterised in that described switching control
Molding block in described difference more than or equal in the case of predetermined threshold, make described arbitrary IGBT pipe and
Described low power consumption switch element is simultaneously in duty, and the most described switching control module includes:
Signal output apparatus, is connected to described control chip, pre-for being more than or equal in described difference
The first signal is exported in the case of determining threshold value, and defeated in the case of described difference is less than predetermined threshold
Go out secondary signal；
State control circuit, is connected to described signal output apparatus, at described state control circuit
When receiving the first signal, control described arbitrary IGBT pipe and described low power consumption switch element is located simultaneously
In duty, and when described state control circuit receives secondary signal, control described low merit
Consumption switch element is in running order.
Power control circuit the most according to claim 2, it is characterised in that described signal is defeated
Go out circuit to include:
First signal processing circuit, is connected to described control chip, the control exporting described control chip
Signal processed processes, to obtain the first switching signal；
Secondary signal processes circuit, is connected to described control chip, the control exporting described control chip
Signal processed processes, to obtain the second switching signal；
First output circuit, described first output circuit includes:
First electric capacity, described first electric capacity is connected between signal source and ground；
First switching device and the first resistance, described first switching device and described first resistant series
After, it being parallel to the two ends of described first electric capacity, described first switching device is additionally coupled to described first letter
Number process circuit, for carrying out on or off according to described first switching signal；
Second output circuit, described second output circuit includes:
Second electric capacity, described second electric capacity is connected between signal source and ground；
Second switch device and the second resistance, described second switch device and described second resistant series
After, it being parallel to the two ends of described second electric capacity, described second switch device is additionally coupled to described second letter
Number process circuit, for carrying out on or off according to described second switching signal；
First voltage comparator, the first input end of described first voltage comparator is connected to described first
Electric capacity and the common port of described first resistance, the second input input preset voltage value, for by described
First voltage and the preset voltage value of the first output circuit output compare, and defeated according to comparative result
Going out the first enabling signal, wherein, the first voltage in described first output circuit output is more than or equal to
During preset voltage value, exporting high level, the first voltage in described first output circuit output is less than pre-
If during magnitude of voltage, output low level；
Second voltage comparator, the first input end of described second voltage comparator is connected to described second
Electric capacity and the common port of described second resistance, the second input input described preset voltage value, and being used for will
Second voltage and the preset voltage value of described second output circuit output compare, and according to comparing knot
Fruit output the second enabling signal, wherein, described second output circuit output the second voltage more than or
During equal to preset voltage value, export high level, little at the second voltage of described second output circuit output
When preset voltage value, output low level；
Trigger, the first end of described trigger is connected to the outfan of described first voltage comparator,
Second end of described trigger is connected to the outfan of described second voltage comparator, for according to reception
The first enabling signal arrived and the second enabling signal export described first signal or described secondary signal.
Power control circuit the most according to claim 3, it is characterised in that described first letter
Number process circuit include:
First delay circuit, is connected between signal source and ground, and input is connected to described control chip
Outfan, the control signal that described control chip is exported postpone a cycle；
First logic circuit, the first input end of described first logic circuit is connected to described first time delay
The outfan of circuit, the second input of described first logic circuit is connected to the defeated of described control chip
Go out end, for the described control signal of described control signal and one all after date of delay being compared；
First phase inverter, the input of described first phase inverter is connected to the defeated of described first logic circuit
Going out end, the outfan of described first phase inverter is connected to the control end of described first switching device, is used for
The signal of described first logic circuit output is carried out anti-phase, and use anti-phase after signal control described
First switching device；
Described secondary signal processes circuit and includes:
Second delay circuit, is connected between signal source and ground, and input is connected to described control chip
Outfan, the control signal that described control chip is exported postpone a cycle；
Second logic circuit, the first input end of described second logic circuit is connected to described second time delay
The outfan of circuit, the second input of described second logic circuit is connected to the defeated of described control chip
Go out end, for the described control signal of described control signal and one all after date of delay being compared；
Second phase inverter, the input of described second phase inverter is connected to the defeated of described second logic circuit
Going out end, the outfan of described second phase inverter is connected to the control end of described second switch device, is used for
The signal of described second logic circuit output is carried out anti-phase, and use anti-phase after signal control described
Second switch device.
Power control circuit the most according to claim 4, it is characterised in that described first patrols
Collecting circuit is the gate circuit of logical AND, and described second logic circuit is the gate circuit of logic XOR.
Power control circuit the most according to claim 4, it is characterised in that
Described first delay circuit includes:
3rd resistance and the first switching tube, described 3rd resistance and described first switching tube are connected on described
Between signal source and ground, the end that controls of described first switching tube is connected to the output of described control chip
End；
3rd electric capacity, is connected in parallel on described 3rd resistance and the two ends of described first switching tube；
3rd phase inverter, the input of described 3rd phase inverter is connected to described 3rd electric capacity and described
The common port of three resistance, the outfan of described 3rd phase inverter is connected to the defeated of described first logic circuit
Enter end；
Described second delay circuit includes:
4th resistance and second switch pipe, described 4th resistance and described second switch pipe are connected on described
Between signal source and ground, the end that controls of described second switch pipe is connected to the output of described control chip
End；
4th electric capacity, is connected in parallel on described 4th resistance and the two ends of described second switch pipe；
4th phase inverter, the input of described 4th phase inverter is connected to described 4th electric capacity and described
The common port of four resistance, the outfan of described 4th phase inverter is connected to the defeated of described second logic circuit
Enter end.
Power control circuit the most according to claim 3, it is characterised in that described state control
Circuit processed includes:
3rd logic circuit, the first input end of described 3rd logic circuit is connected to described trigger
Outfan, the second input are connected to the outfan of described control chip, outfan is connected to first and drives
Galvanic electricity road, in the case of receiving described first signal, by the control from described control chip
Signal processed output is to described first drive circuit, in the case of receiving described secondary signal, stops
Control signal from described control chip exports to described first drive circuit；
4th logic circuit, first input end and second input of described 4th logic circuit are all connected with
To the signal output part of described control chip, for the control signal from described control chip is exported
To the second drive circuit；
Wherein, described first drive circuit for described arbitrary IGBT pipe is driven, described the
Two drive circuits are for being driven described low power consumption switch element.
Power control circuit the most according to claim 7, it is characterised in that the described 3rd patrols
Collect circuit and described 4th logic circuit is the gate circuit of logical AND.
9. a SPM, it is characterised in that include at least one as claim 1 to
Power control circuit according to any one of 8.
10. a frequency-conversion domestic electric appliances, it is characterised in that include intelligent power as claimed in claim 9
Module.
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| US9397657B1 (en) * | 2014-07-24 | 2016-07-19 | Eaton Corporation | Methods and systems for operating hybrid power devices using multiple current-dependent switching patterns |
| CN104158428B (en) * | 2014-08-05 | 2016-08-17 | 广东美的集团芜湖制冷设备有限公司 | SPM and switch thereof adjust circuit, frequency-conversion domestic electric appliances |
| KR102588932B1 (en) * | 2018-04-18 | 2023-10-16 | 현대자동차주식회사 | Inverter system for vehicle |
| CN112432310B (en) * | 2020-10-23 | 2022-08-26 | 珠海格力电器股份有限公司 | Power factor calibration system, method, processor, compressor, air conditioner and medium |
| CN116582018A (en) * | 2023-06-07 | 2023-08-11 | 上海功成半导体科技有限公司 | Variable frequency control circuit and semiconductor device |
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| CN103166615A (en) * | 2011-12-14 | 2013-06-19 | 三菱电机株式会社 | Power semiconductor device |
| CN203813690U (en) * | 2014-03-13 | 2014-09-03 | 广东美的制冷设备有限公司 | Power consumption control circuit, intelligent power module and variable frequency household electrical appliance |
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| CN103166615A (en) * | 2011-12-14 | 2013-06-19 | 三菱电机株式会社 | Power semiconductor device |
| CN203813690U (en) * | 2014-03-13 | 2014-09-03 | 广东美的制冷设备有限公司 | Power consumption control circuit, intelligent power module and variable frequency household electrical appliance |
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