CN103888012A

CN103888012A - Power dissipation control circuit, intelligent power module and variable frequency household appliance

Info

Publication number: CN103888012A
Application number: CN201410093751.2A
Authority: CN
Inventors: 冯宇翔
Original assignee: Guangdong Midea Refrigeration Equipment Co Ltd
Current assignee: GD Midea Air Conditioning Equipment Co Ltd
Priority date: 2014-03-13
Filing date: 2014-03-13
Publication date: 2014-06-25
Anticipated expiration: 2034-03-13
Also published as: CN103888012B

Abstract

The invention provides a power dissipation control circuit, an intelligent power module and a variable frequency household appliance. The power dissipation control circuit comprises a low power dissipation switch element and a switching control module, wherein the low power dissipation switch element is connected to any IGBT in the intelligent power module in parallel to form a switch assembly, the switching control module is connected to a control chip corresponding to the intelligent power module to detect the duty ratios of control signals output by the control chip within two adjacent periods and calculate the difference value of the duty ratios of the control signals within the two adjacent periods, under the condition that the difference value of the duty ratios is larger than or equal to a preset threshold value, the IGBT and the low power dissipation switch element are in the working states at the same time, and under the condition that the difference value of the duty ratios is smaller than the preset threshold value, only the low power dissipation switch element is in the working state. By means of the technical scheme, different on-off devices can be adopted when the difference value of the duty ratios of input signals within two adjacent periods is changed, power dissipation of the intelligent power module is easily reduced, and the risk that the on-off devices are broken down by the overcurrent is avoided.

Description

Power control circuit, Intelligent Power Module and frequency-conversion domestic electric appliances

Technical field

The present invention relates to power consumption control technical field, in particular to a kind of power control circuit, a kind of Intelligent Power Module and a kind of frequency-conversion domestic electric appliances.

Background technology

Intelligent Power Module, i.e. IPM(Intelligent Power Module), be a kind of by the power drive series products of power electronics and integrated circuit technique combination.Intelligent Power Module integrates device for power switching and high-voltage driving circuit, and in keep overvoltage, overcurrent and the failure detector circuit such as overheated.Intelligent Power Module receives on the one hand MCU(Micro Control Unit, miniature control chip) control signal, drive subsequent conditioning circuit work, send the state detection signal of system back to MCU on the other hand.Compared with traditional discrete scheme, Intelligent Power Module wins increasing market with advantages such as its high integration, high reliability, being particularly suitable for frequency converter and the various inverter of drive motors, is the desirable power electronic device of one that is applied to frequency control, metallurgical machinery, electric traction, servo-drive, frequency-conversion domestic electric appliances.

In correlation technique, the circuit structure of Intelligent Power Module 100 as shown in Figure 1:

The VCC end of HVIC pipe 1000 is as the low-pressure area power supply anode VDD of Intelligent Power Module 100, and VDD is generally 15V; Meanwhile, managing 1000 inside at described HVIC has boostrap circuit, and boostrap circuit structure is as follows:

VCC end is connected with the low-pressure area power supply anode of UH drive circuit 101, VH drive circuit 102, WH drive circuit 103, UL drive circuit 104, VL drive circuit 105, WL drive circuit 106.

The HIN1 end of described HVIC pipe 1000 is gone up brachium pontis input UHIN mutually as the U of described Intelligent Power Module 100, manages 1000 inside be connected with the input of described UH drive circuit 101 at described HVIC; The HIN2 end of described HVIC pipe 1000 is gone up brachium pontis input VHIN mutually as the V of described Intelligent Power Module 100, manages 1000 inside be connected with the input of described VH drive circuit 102 at described HVIC; The HIN3 end of described HVIC pipe 1000 is gone up brachium pontis input WHIN mutually as the W of described Intelligent Power Module 100, manages 1000 inside be connected with the input of described WH drive circuit 103 at described HVIC.

The LIN1 end of described HVIC pipe 1000 descends brachium pontis input ULIN mutually as the U of described Intelligent Power Module 100, manages 1000 inside be connected with the input of described UL drive circuit 104 at described HVIC; The LIN2 end of described HVIC pipe 1000 descends brachium pontis input VLIN mutually as the V of described Intelligent Power Module 100, manages 1000 inside be connected with the input of described VL drive circuit 105 at described HVIC; The LIN3 end of described HVIC pipe 1000 descends brachium pontis input WLIN mutually as the W of described Intelligent Power Module 100, manages 1000 inside be connected with the input of described WL drive circuit 106 at described HVIC; At this, the U of described Intelligent Power Module 100, V, the input of W three-phase Liu road receive the input signal of 0V or 5V.

The GND of described HVIC pipe 1000 holds the low-pressure area power supply negative terminal COM as described Intelligent Power Module 100, and is connected with the low-pressure area power supply negative terminal of described UH drive circuit 101, described VH drive circuit 102, described WH drive circuit 103, described UL drive circuit 104, described VL drive circuit 105, described WL drive circuit 106.

The VB1 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the higher-pressure region power supply anode of described UH drive circuit 101, in the outside one end that connect electric capacity 133 of described HVIC pipe 1000, and as the U phase higher-pressure region power supply anode UVB of described Intelligent Power Module 100; The HO1 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the output of described UH drive circuit 101, manages 1000 outsides be connected with the grid that U goes up brachium pontis IGBT pipe 121 mutually at described HVIC; The VS1 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the higher-pressure region power supply negative terminal of described UH drive circuit 101, anode, the U that manages emitter-base bandgap grading, the FRD pipe 111 of 1000 outsides and described IGBT pipe 121 at described HVIC descend that the collector electrode of brachium pontis IGBT pipe 124, FRD manage 114 negative electrode, the other end of described electric capacity 133 is connected mutually, and as the U phase higher-pressure region power supply negative terminal UVS of described Intelligent Power Module 100.

The VB2 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the higher-pressure region power supply anode of described VH drive circuit 102, in the outside one end that connects electric capacity 132 of described HVIC pipe 1000, as the U phase higher-pressure region power supply anode VVB of described Intelligent Power Module 100; The HO2 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the output of described VH drive circuit 102, manages 1000 outsides be connected with the grid that V goes up brachium pontis IGBT pipe 123 mutually at described HVIC; The VS2 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the higher-pressure region power supply negative terminal of described VH drive circuit 102, anode, the V that manages emitter-base bandgap grading, the FRD pipe 112 of 1000 outsides and described IGBT pipe 122 at described HVIC descend that the collector electrode of brachium pontis IGBT pipe 125, FRD manage 115 negative electrode, the other end of described electric capacity 132 is connected mutually, and as the W phase higher-pressure region power supply negative terminal VVS of described Intelligent Power Module 100.

The VB3 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the higher-pressure region power supply anode of described WH drive circuit 103, in the outside one end that connects electric capacity 131 of described HVIC pipe 1000, as the W phase higher-pressure region power supply anode WVB of described Intelligent Power Module 100; The HO3 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the output of described WH drive circuit 101, manages 1000 outsides be connected with the grid that W goes up brachium pontis IGBT pipe 123 mutually at described HVIC; The VS3 end of described HVIC pipe 1000 is managed 1000 inside at described HVIC and is connected with the higher-pressure region power supply negative terminal of described WH drive circuit 103, anode, the W that manages emitter-base bandgap grading, the FRD pipe 113 of 1000 outsides and described IGBT pipe 123 at described HVIC descend that the collector electrode of brachium pontis IGBT pipe 126, FRD manage 116 negative electrode, the other end of described electric capacity 131 is connected mutually, and as the W phase higher-pressure region power supply negative terminal WVS of described Intelligent Power Module 100.

The LO1 end of described HVIC pipe 1000 is connected with the grid of described IGBT pipe 124; The LO2 end of described HVIC pipe 1000 is connected with the grid of described IGBT pipe 125; The LO3 end of described HVIC pipe 1000 is connected with the grid of described IGBT pipe 126.

The emitter-base bandgap grading of described IGBT pipe 124 is connected with the anode of described FRD pipe 114, and as the U phase low reference voltage end UN of described Intelligent Power Module 100; The emitter-base bandgap grading of described IGBT pipe 125 is connected with the anode of described FRD pipe 115, and as the V phase low reference voltage end VN of described Intelligent Power Module 100; The emitter-base bandgap grading of described IGBT pipe 126 is connected with the anode of described FRD pipe 116, and as the W phase low reference voltage end WN of described Intelligent Power Module 100.

The negative electrode of the collector electrode of the negative electrode of the collector electrode of the negative electrode of the collector electrode of described IGBT pipe 121, described FRD pipe 111, described IGBT pipe 122, described FRD pipe 112, described IGBT pipe 123, described FRD pipe 113 is connected, and as the high voltage input P of described Intelligent Power Module 100, P generally meets 300V.

The effect of described HVIC pipe 1000 is:

VDD is the power supply anode of described HVIC pipe 1000, and GND is the power supply negative terminal (VDD-GND voltage is generally 15V) of described HVIC pipe 1000.VB1 and VS1 are respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO1 is the output of U phase higher-pressure region; VB2 and VS2 are respectively positive pole and the negative pole of the power supply of V phase higher-pressure region, and HO2 is the output of V phase higher-pressure region; VB3 and VS3 are respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO3 is the output of W phase higher-pressure region; LO1, LO2, LO3 are respectively the output of U phase, V phase, W phase low-pressure area.

The logic input signal of 0 or the 5V of input HIN1, HIN2, HIN3 and LIN1, LIN2, LIN3 is passed to respectively to output HO1, HO2, HO3 and LO1, LO2, LO3, wherein, HO1 is that logic output signal, the HO2 of VS1 or VS1+15V is that logic output signal, the HO3 of VS2 or VS2+15V is the logic output signal of VS3 or VS3+15V, and LO1, LO2, LO3 are 0 or the logic output signal of 15V.

Meanwhile, the input signal of same phase can not be high level simultaneously, and HIN1 and LIN1, HIN2 and LIN2, HIN3 and LIN3 can not be high level simultaneously.

A kind of preferred circuit when described Intelligent Power Module 100 real work is as shown in Figure 2:

External capacitor 135 between UVB and UVS; External capacitor 136 between VVB and VVS; External capacitor 137 between WVB and WVS.At this, described electric capacity 133,132,131 mainly strobes, and described electric capacity 135,136,137 mainly plays storing electricity effect.

UN, VN, WN are connected, and the Pin7 of one end of contact resistance 138 and MCU pipe 200; Another termination COM of described resistance 138.

The Pin1 of described MCU200 is connected with the UHIN end of described Intelligent Power Module 100; The Pin2 of described MCU200 is connected with the VHIN end of described Intelligent Power Module 100; The Pin3 of described MCU200 is connected with the WHIN end of described Intelligent Power Module 100; The Pin4 of described MCU200 is connected with the ULIN end of described Intelligent Power Module 100; The Pin5 of described MCU200 is connected with the VLIN end of described Intelligent Power Module 100; The Pin6 of described MCU200 is connected with the WLIN end of described Intelligent Power Module 100.

The operating state of Intelligent Power Module 100 is described as example mutually taking U:

1, in the time that the pin Pin4 of described MCU200 sends high level signal, the pin Pin1 of described MCU200 must send low level signal, it is that high level, HIN1 are low level that signal makes LIN1, at this moment, LO1 exports high level and HO1 output low level, described IGBT pipe 121 cut-offs thereby described IGBT manages 124 conductings, VS1 voltage is about 0V; VCC charges to described electric capacity 133 and described electric capacity 135, when time long enough or make described electric capacity 133 and described electric capacity 135 charging before dump energy when abundant, VB1 obtains the voltage that approaches 15V to VS1.

2, in the time that the pin Pin1 of described MCU200 sends high level signal, the pin Pin4 of described MCU200 must send low level signal, it is low level that signal makes LIN1, HIN1 is high level, at this moment, LO1 output low level and HO1 output high level, thereby described IGBT pipe 124 cut-offs and described IGBT manages 121 conductings, thereby VS1 voltage is about 300V, VB1 voltage is lifted to 315V left and right, by the electric weight of described electric capacity 133 and described electric capacity 135, maintain the work of U phase higher-pressure region, if the electric weight that the duration that HIN1 is high level, enough short or described electric capacity 133 and described electric capacity 135 were stored is abundant, VB1 is more than to VS1, the voltage in the course of work of U phase higher-pressure region can remain on 14V.

In practical application, particularly, in the application of convertible frequency air-conditioner, MCU200 can adopt according to environmental change the break-make of different algorithm control Intelligent Power Module 100, and frequency-changeable compressor is operated under different frequencies.

The control of MCU200 to compressor frequency, under the carrier frequency by the 6kHz fixing, duty in adjusting carrier cycle is recently realized, in the time needing compressor operating in higher frequency, differing greatly of the duty ratio of each carrier cycle, as shown in Figure 3A, the duty ratio of control signal period 1 is 80%, and the duty ratio of second round is 20%, the duty cycle difference in adjacent two cycles is 60%; In the time needing compressor operating in lower frequency, the difference of the duty ratio of each carrier cycle is less, and as shown in Figure 3 B, the duty ratio of control signal period 1 is 60%, and the duty ratio of second round is 40%, and the duty cycle difference in adjacent two cycles is 20%.

In the time of the differing greatly of the duty ratio of each carrier cycle, compressor operating is under high frequency, and at this moment, six pieces of IGBT pipes of Intelligent Power Module 100 inside (as IGBT pipe 121 to IGBT pipes 126) need to flow through larger electric current; When the difference of the duty ratio of each carrier cycle hour, compressor operating is under low frequency, at this moment, the electric current that six pieces of IGBT pipes of Intelligent Power Module 100 inside flow through is less.

For the state of compressor low frequency operation, wish often to obtain low-power consumption, and while using IGBT pipe as on-off element, due to the smearing of IGBT pipe, cause the switching loss of on-off element can not be very low, thereby make the loss of Intelligent Power Module 100 also can not do very lowly.

If use without the metal-oxide-semiconductor of smearing and substitute IGBT pipe, in the time of compressor low frequency operation, really can reduce break-make loss and system power dissipation, but due to the restriction of metal-oxide-semiconductor current capacity, in the time that compressor enters high-frequency work state, excessive electric current can exceed the current range that metal-oxide-semiconductor can bear and cause metal-oxide-semiconductor overcurrent to burn, and also can cause fire when serious.

In correlation technique, the low frequency operation loss that reduces Intelligent Power Module by improving the smearing of IGBT pipe realizes, but this special process makes the production cost of IGBT pipe very high, is not suitable for promoting at civil areas such as convertible frequency air-conditioners.

Therefore, how to reduce the loss of Intelligent Power Module in the time of low frequency operation, and overcurrent risk while avoiding high-frequency work, and production cost is applicable to civil area, becomes technical problem urgently to be resolved hurrily at present.

Summary of the invention

The present invention is intended at least solve one of technical problem existing in prior art or correlation technique.

For this reason, one object of the present invention is to have proposed a kind of power control circuit.

Another object of the present invention is to have proposed a kind of Intelligent Power Module.

Another object of the present invention is to have proposed a kind of frequency-conversion domestic electric appliances.

For achieving the above object, embodiment according to a first aspect of the invention, has proposed a kind of power control circuit, comprising: low-power consumption switch element, is connected in parallel to the arbitrary IGBT pipe in Intelligent Power Module, to form switch module; Switching controls module, be connected to control chip corresponding to described Intelligent Power Module, the duty ratio of the signal in adjacent two cycles of the control signal of exporting for detection of described control chip, and calculate the duty cycle difference of the signal in described adjacent two cycles, in the situation that described duty cycle difference is more than or equal to predetermined threshold, make described arbitrary IGBT pipe and described low-power consumption switch element simultaneously in running order, in the situation that described duty cycle difference is less than predetermined threshold, only make described low-power consumption switch element in running order.

Power control circuit according to an embodiment of the invention, by making low-power consumption switch element and IGBT pipe formation in parallel switch module, and in the time that the difference that control chip inputs to the duty ratio of the signal in adjacent two cycles of the control signal of Intelligent Power Module is less than predetermined threshold, only make low-power consumption switch element in running order, thereby can avoid in prior art, because the smearing of IGBT pipe causes unnecessary working loss, contributing to reduce the overall power of Intelligent Power Module.

Simultaneously, while being more than or equal to predetermined threshold by input to the difference of duty ratio of signal in adjacent two cycles of control signal of Intelligent Power Module at control chip, make IGBT pipe and low-power consumption switch element simultaneously in running order, thereby avoid low-power consumption switch element to be punctured by overcurrent, contribute to guarantee the fail safe of intelligent power consumption module.

Wherein, definite mode of predetermined threshold includes but not limited to: the scope of the current strength that can bear according to low-power consumption switch element, determine maximum and the minimum value of the difference of the duty ratio in adjacent two cycles of control signal, can be used as the scope of predetermined threshold.Low-power consumption switch element is specifically as follows metal-oxide-semiconductor, such as NMOS pipe etc., thereby can either bear the current strength of Intelligent Power Module current flowing when larger, effectively reduces break-make loss and system loss again owing to not having smearing.

In addition, power control circuit according to the above embodiment of the present invention, can also have following additional technical characterictic:

According to one embodiment of present invention, described switching controls module is in the situation that described difference is more than or equal to predetermined threshold, make described arbitrary IGBT pipe and described low-power consumption switch element simultaneously in running order, described switching controls module comprises: signal output apparatus, be connected to described control chip, for export first signal in the situation that described difference is more than or equal to predetermined threshold, and in the situation that being less than predetermined threshold, described difference exports secondary signal; State control circuit, be connected to described signal output apparatus, for in the time that described state control circuit receives first signal, control described arbitrary IGBT pipe and described low-power consumption switch element simultaneously in running order, and in the time that described state control circuit receives secondary signal, control described low-power consumption switch element in running order.

Power control circuit according to an embodiment of the invention, by the difference of duty ratio and the comparison of predetermined threshold of signal in adjacent two cycles of the control signal that inputs to Intelligent Power Module is converted to first signal or secondary signal, for example: the high level signal that is converted to that this difference can be more than or equal to predetermined threshold, this difference is less than to the low level signal that is converted to of predetermined threshold, thus the accurately switching of control circuit operating state.

According to one embodiment of present invention, described signal output apparatus comprises: first signal treatment circuit, be connected to described control chip, and the control signal of described control chip output is processed, to obtain the first switching signal; Secondary signal treatment circuit, is connected to described control chip, the control signal of described control chip output is processed, to obtain the second switching signal; The first output circuit, described the first output circuit comprises: the first electric capacity, described the first electric capacity is connected between signal source and ground; The first switching device and the first resistance, after described the first switching device is connected with described the first resistance, be parallel to the two ends of described the first electric capacity, described the first switching device is also connected to described first signal treatment circuit, for carrying out conducting or cut-off according to described the first switching signal; The second output circuit, described the second output circuit comprises: the second electric capacity, described the second electric capacity is connected between signal source and ground; Second switch device and the second resistance, after described second switch device is connected with described the second resistance, be parallel to the two ends of described the second electric capacity, described second switch device is also connected to described secondary signal treatment circuit, for carrying out conducting or cut-off according to described the second switching signal; The first voltage comparator, the first input end of described the first voltage comparator is connected to common port, the second input input predeterminated voltage value of described the first electric capacity and described the first resistance, for the first voltage and the predeterminated voltage value of described the first output circuit output are compared, and export the first enabling signal according to comparative result, wherein, in the time that the first voltage of described the first output circuit output is more than or equal to predeterminated voltage value, output high level, in the time that the first voltage of described the first output circuit output is less than predeterminated voltage value, output low level; Second voltage comparator, the first input end of described second voltage comparator is connected to common port, second input of described the second electric capacity and described the second resistance and inputs described predeterminated voltage value, for second voltage and the predeterminated voltage value of described the second output circuit output are compared, and export the second enabling signal according to comparative result, wherein, in the time that the second voltage of described the second output circuit output is more than or equal to predeterminated voltage value, output high level, in the time that the second voltage of described the second output circuit output is less than predeterminated voltage value, output low level; Trigger, the first end of described trigger is connected to the output of described the first voltage comparator, the second end of described trigger is connected to the output of described second voltage comparator, for exporting described first signal or described secondary signal according to the first enabling signal and the second enabling signal that receive.

Power control circuit according to an embodiment of the invention, conducting or the cut-off of switching device in the switching signal control output circuit of exporting by signal processing circuit, what the conducting of switching device or cut-off will continue to the oscillating circuit being made up of resistance and electric capacity in output circuit carries out charging and discharging, thereby the voltage of resistance and electric capacity common port in output circuit is changed with the charging and discharging of oscillating circuit, and then control chip is inputed to the difference of duty ratio of signal in adjacent two cycles of the control signal of Intelligent Power Module and the comparison of predetermined threshold and is converted to the size of output circuit output voltage.

By voltage comparator, second voltage and the predeterminated voltage value of the first voltage of the first output circuit output or the output of the second output circuit are compared, generate the first enabling signal or the second enabling signal according to comparative result, the first enabling signal and the second enabling signal are as the input of trigger, according to the characteristic of trigger, generate first signal or secondary signal, and then the size of output circuit output voltage is converted into first signal or secondary signal, thereby the accurately switching of control circuit operating state.

Specifically, the first voltage or second voltage and predeterminated voltage value compare, generate the first enabling signal or the second enabling signal according to comparative result, wherein, when the first voltage or second voltage are greater than predeterminated voltage value, enabling signal is high level, and when the first voltage or second voltage are less than predeterminated voltage value, enabling signal is low level.Certainly, one skilled in the art will appreciate that and generate the comparative approach of the first enabling signal or the second enabling signal herein and be not used in concrete restriction.

According to one embodiment of present invention, described first signal treatment circuit comprises: the first delay circuit, be connected between signal source and ground, and input is connected to the output of described control chip, and the control signal of described control chip output is postponed to one-period; The first logical circuit, the first input end of described the first logical circuit is connected to the output of described the first delay circuit, the second input of described the first logical circuit is connected to the output of described control chip, for the described control signal after described control signal and delay one-period is compared; The first inverter, the input of described the first inverter is connected to the output of described the first logical circuit, the output of described the first inverter is connected to the control end of described the first switching device, anti-phase for the signal of described the first logical circuit output is carried out, and use the first switching device described in the signal controlling after anti-phase; Described secondary signal treatment circuit comprises: the second delay circuit, be connected between signal source and ground, and input is connected to the output of described control chip, and the control signal of described control chip output is postponed to one-period; The second logical circuit, the first input end of described the second logical circuit is connected to the output of described the second delay circuit, the second input of described the second logical circuit is connected to the output of described control chip, for the described control signal after described control signal and delay one-period is compared; The second inverter, the input of described the second inverter is connected to the output of described the second logical circuit, the output of described the second inverter is connected to the control end of described second switch device, anti-phase for the signal of described the second logical circuit output is carried out, and use second switch device described in the signal controlling after anti-phase.

Power control circuit according to an embodiment of the invention, by input signal is carried out to time delay one-period, and using the control signal after time delay with do not pass through the control signal of time delay as the input of the first logical circuit or the second logical circuit, carry out logical operation, control chip is inputed to the signal in adjacent two cycles of the control signal of Intelligent Power Module and carry out logical operation, and with inversion signal control first switching device of logic operation result and conducting or the cut-off of second switch device, to obtain the output voltage of output circuit, i.e. the first voltage and second voltage.

Wherein, in order to obtain desirable control signal waveform, after being exported by control chip, can carry out whole ripple processing by inverter, and through after delay circuit, also can use two inverters to carry out whole ripple processing simultaneously.

According to one embodiment of present invention, the gate circuit that described the first logical circuit is logical AND, described the second logical circuit is the gate circuit of logic XOR.

Power control circuit according to an embodiment of the invention, inputing to the larger cycle of duty ratio in adjacent two cycles of control signal of Intelligent Power Module taking control chip is period 1 signal, the smaller cycle of duty be second round signal be example, the signal in adjacent two cycles that inputs to the control signal of Intelligent Power Module due to control chip is respectively as the input of the first logical circuit or the second logical circuit, therefore, in the time that the first logical circuit is logical AND circuit, the duty ratio of logical AND circuit output signal is the duty ratio of signal second round; And in the time that the second logical circuit is logic XOR circuit, the duty ratio of logic XOR circuit output signal be period 1 signal and second round signal duty ratio poor.

When the difference that inputs to the duty ratio in adjacent two cycles of the control signal of Intelligent Power Module at control chip is less than predetermined threshold, the second switching signal duty ratio of the second logical circuit output is less than predetermined threshold, the second voltage of the second output circuit output will be less than predeterminated voltage value, trigger is will export secondary signal while continuing low level at the second input, only makes low-consumption power element in running order; Due to second round, the duty ratio of signal is less, period 1 signal and second round signal the difference of duty ratio larger, and in the time that the difference that control chip inputs to the duty ratio in adjacent two cycles of the control signal of Intelligent Power Module is more than or equal to predetermined threshold, the duty of the first switching signal of the first logical circuit output is smaller, the first voltage of the first output circuit output will be less than predeterminated voltage value, trigger is will export first signal while continuing low level at first input end, makes IGBT pipe and low-power consumption element simultaneously in running order.

According to one embodiment of present invention, described the first delay circuit comprises: the 3rd resistance and the first switching tube, described the 3rd resistance and described the first switching tube are connected between described signal source and ground, and the control end of described the first switching tube is connected to the output of described control chip; The 3rd electric capacity, is connected in parallel on the two ends of described the 3rd resistance and described the first switching tube; The 3rd inverter, the common port of the 3rd electric capacity and described the 3rd resistance described in the input of described the 3rd inverter, the output of described the 3rd inverter is connected to the input of described the first logical circuit; Described the second delay circuit comprises: the 4th resistance and second switch pipe, and described the 4th resistance and described second switch pipe string are associated between described signal source and ground, and the control end of described second switch pipe is connected to the output of described control chip; The 4th electric capacity, is connected in parallel on the two ends of described the 4th resistance and described second switch pipe; The 4th inverter, the common port of the 4th electric capacity and described the 4th resistance described in the input of described the 4th inverter, the output of described the 4th inverter is connected to the input of described the second logical circuit.

Power control circuit according to an embodiment of the invention, by the control signal time delay one-period to control chip output, can carry out logical operation to the signal in adjacent two cycles of the control signal of control chip output.Wherein, conducting or the cut-off of switching tube in the control signal control delay circuit of control chip output, control the charging and discharging time that is formed oscillating circuit in delay circuit by resistance and electric capacity, by the size of regulating resistance and electric capacity, the delay cycle of adjustable delay circuit.

According to one embodiment of present invention, described state control circuit comprises: the 3rd logical circuit, the first input end of described the 3rd logical circuit is connected to the output of described trigger, output, the output that the second input is connected to described control chip is connected to the first drive circuit, for in the situation that receiving described first signal, described the first drive circuit will be exported to from the control signal of described control chip, in the situation that receiving described secondary signal, stop and export described the first drive circuit to from the control signal of described control chip; The 4th logical circuit, the first input end of described the 4th logical circuit and the second input are all connected to the signal output part of described control chip, for exporting described the second drive circuit to from the control signal of described control chip; Wherein, described the first drive circuit for described arbitrary IGBT pipe is driven, described the second drive circuit is for driving described low-power consumption switch element.

Power control circuit according to an embodiment of the invention, control signal by first signal or secondary signal and control chip output is carried out logical operation, control the operating state of the first drive circuit, also control the operating state of arbitrary IGBT pipe in Intelligent Power Module, thereby make in the time receiving first signal, make IGBT pipe and low-power consumption switch element simultaneously in running order, thereby avoid low-power consumption switch element to be punctured by overcurrent, contribute to guarantee the fail safe of intelligent power consumption module.In the time receiving secondary signal, only make low-power consumption switch element in running order, thereby can avoid in prior art, because the smearing of IGBT pipe causes unnecessary working loss, contributing to reduce the overall power of Intelligent Power Module.

According to one embodiment of present invention, the gate circuit that described the 3rd logical circuit and described the 4th logical circuit are logical AND.

Power control circuit according to an embodiment of the invention, by the gate circuit of logical AND, how the control signal that no matter inputs to intelligent power control module is changed, low-power consumption switch element is all in running order, and owing to being control signal with an input of the logical AND gate being connected of IGBT pipe, another input is first signal or secondary signal, thereby the operating state of IGBT pipe can be subject to the control of first signal and secondary signal, realizes the switching of operating state.

According to the embodiment of second aspect present invention, a kind of Intelligent Power Module has been proposed, comprise the power control circuit described in above-mentioned any one technical scheme.

According to the embodiment of third aspect present invention, a kind of frequency-conversion domestic electric appliances has been proposed, comprise the Intelligent Power Module as described in technique scheme, such as convertible frequency air-conditioner, frequency conversion refrigerator, variable-frequency washing machine etc.

By above technical scheme, can, in the time that adjacent two the cycle duty cycle differences of input signal are different, adopt different break-make devices, thereby contribute to reduce the power consumption of Intelligent Power Module, and the risk that can not exist break-make device to be punctured by overcurrent.

Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.

Brief description of the drawings

Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:

Fig. 1 shows the structural representation of the Intelligent Power Module in correlation technique;

The structural representation that Fig. 2 shows Intelligent Power Module in correlation technique while carrying out sequencing control;

Fig. 3 A to Fig. 3 B show in correlation technique Intelligent Power Module is carried out to sequencing control time control signal waveform schematic diagram;

Fig. 4 A shows the structural representation of power control circuit according to an embodiment of the invention;

Fig. 4 B shows the structural representation of switching controls module according to an embodiment of the invention;

Fig. 4 C shows the structural representation of signal processing circuit according to an embodiment of the invention;

Fig. 5 shows the structural representation of Intelligent Power Module according to an embodiment of the invention;

Fig. 6 shows the electrical block diagram of switching controls module according to an embodiment of the invention;

Fig. 7 shows the waveform schematic diagram of control signal while carrying out sequencing control according to embodiments of the invention Intelligent Power Module;

Fig. 8 shows the structural representation of delay circuit according to an embodiment of the invention.

Embodiment

In order more clearly to understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments, the present invention is further described in detail.It should be noted that, in the situation that not conflicting, the feature in the application's embodiment and embodiment can combine mutually.

A lot of details are set forth in the following description so that fully understand the present invention; but; the present invention can also adopt other to be different from other modes described here and implement, and therefore, protection scope of the present invention is not limited to the restriction of following public specific embodiment.

One, overall structure

In correlation technique, Intelligent Power Module all adopts IGBT pipe as break-make device, but on the one hand, the smearing of IGBT pipe causes the switching loss under its low frequency too high, on the other hand, if directly use low-power consumption switch element, easily damage low-power consumption switch element because the electric current under high frequency is excessive, even the unsafe condition such as initiation fire.

Therefore,, in order to solve many-sided problem such as switching loss and overcurrent risk, Fig. 4 A shows the structural representation of power control circuit according to an embodiment of the invention.

As shown in Figure 4 A, power control circuit according to an embodiment of the invention, comprise: low-power consumption switch element 42, be connected in parallel to arbitrary IGBT pipe in Intelligent Power Module (than Intelligent Power Module 100 as shown in Figure 1) (than as shown in Figure 4 A 121), to form switch module (not specifically illustrating in figure); Switching controls module 44, be connected to control chip corresponding to described Intelligent Power Module, the duty ratio of the signal in adjacent two cycles of the control signal of exporting for detection of described control chip, and calculate the duty cycle difference of the signal in described adjacent two cycles, in the situation that described duty cycle difference is more than or equal to predetermined threshold, make described arbitrary IGBT pipe and described low-power consumption switch element 42 simultaneously in running order, in the situation that described duty cycle difference is less than predetermined threshold, only make described low-power consumption switch element 42 in running order.

By making low-power consumption switch element 42 and IGBT pipe formation in parallel switch module, and in the time that the difference that control chip inputs to the duty ratio of the signal in adjacent two cycles of the control signal of Intelligent Power Module is less than predetermined threshold, only make low-power consumption switch element 42 in running order, thereby can avoid in prior art, because the smearing of IGBT pipe causes unnecessary working loss, contributing to reduce the overall power of Intelligent Power Module.

Simultaneously, while being more than or equal to predetermined threshold by input to the difference of duty ratio of signal in adjacent two cycles of control signal of Intelligent Power Module at control chip, make IGBT pipe and low-power consumption switch element 42 simultaneously in running order, thereby avoid low-power consumption switch element to be punctured by overcurrent, contribute to guarantee the fail safe of intelligent power consumption module.

Wherein, definite mode of predetermined threshold includes but not limited to: the scope of the current strength that can bear according to low-power consumption switch element 42, determine maximum and the minimum value of the difference of the duty ratio in adjacent two cycles of control signal, can be used as the scope of predetermined threshold.Low-power consumption switch element 42 is specifically as follows metal-oxide-semiconductor, such as NMOS pipe etc., thereby can either bear the current strength of Intelligent Power Module current flowing when larger, effectively reduces break-make loss and system loss again owing to not having smearing.

Two, switching controls module

In order to describe switching controls module 44 according to an embodiment of the invention in detail, Fig. 4 B shows the structural representation of switching controls module according to an embodiment of the invention.

As shown in Figure 4 B, switching controls module 44 according to an embodiment of the invention, described switching controls module 44 is in the situation that described difference is more than or equal to predetermined threshold, make described arbitrary IGBT pipe and described low-power consumption switch element 42 simultaneously in running order, described switching controls module 44 comprises: signal output apparatus (not specifically illustrating in figure), be connected to described control chip, for export first signal in the situation that described difference is more than or equal to predetermined threshold, and in the situation that being less than predetermined threshold, described difference exports secondary signal; State control circuit 441, be connected to described signal output apparatus, for in the time that described state control circuit 441 receives first signal, control described arbitrary IGBT pipe and 42 whiles of described low-power consumption switch element in running order, and in the time that described state control circuit 441 receives secondary signal, control described low-power consumption switch element 42 in running order.

By the difference of duty ratio and the comparison of predetermined threshold of signal in adjacent two cycles of the control signal that inputs to Intelligent Power Module is converted to first signal or secondary signal, for example: the high level signal that is converted to that this difference can be more than or equal to predetermined threshold, this difference is less than to the low level signal that is converted to of predetermined threshold, thus the accurately switching of control circuit operating state.

According to one embodiment of present invention, described signal output apparatus comprises: first signal treatment circuit 442, be connected to described control chip, and the control signal of described control chip output is processed, to obtain the first switching signal, secondary signal treatment circuit 443, is connected to described control chip, the control signal of described control chip output is processed, to obtain the second switching signal, the first output circuit 444, described the first output circuit 444 comprises: the first electric capacity, described the first electric capacity is connected between signal source and ground, the first switching device and the first resistance, after described the first switching device is connected with described the first resistance, be parallel to the two ends of described the first electric capacity, described the first switching device is also connected to described first signal treatment circuit 442, for carrying out conducting or cut-off according to described the first switching signal, the second output circuit 445, described the second output circuit 445 comprises: the second electric capacity, described the second electric capacity is connected between signal source and ground, second switch device and the second resistance, after described second switch device is connected with described the second resistance, be parallel to the two ends of described the second electric capacity, described second switch device is also connected to described secondary signal treatment circuit 443, for carrying out conducting or cut-off according to described the second switching signal, the first voltage comparator 446, the first input end of described the first voltage comparator 446 is connected to the common port of described the first electric capacity and described the first resistance, the second input input predeterminated voltage value, compare for the first voltage and predeterminated voltage value that described the first output circuit 444 is exported, and export the first enabling signal according to comparative result, wherein, when the first voltage of exporting at described the first output circuit 444 is more than or equal to predeterminated voltage value, output high level, when the first voltage of exporting at described the first output circuit 444 is less than predeterminated voltage value, output low level, second voltage comparator 447, the first input end of described second voltage comparator 447 is connected to the common port of described the second electric capacity and described the second resistance, the second input is inputted described predeterminated voltage value, compare for second voltage and predeterminated voltage value that described the second output circuit 445 is exported, and export the second enabling signal according to comparative result, wherein, when the second voltage of exporting at described the second output circuit 445 is more than or equal to predeterminated voltage value, output high level, when the second voltage of exporting at described the second output circuit 445 is less than predeterminated voltage value, output low level, trigger 448, the first end of described trigger 448 is connected to the output of described the first voltage comparator 446, the second end of described trigger 448 is connected to the output of described second voltage comparator 447, for exporting described first signal or described secondary signal according to the first enabling signal and the second enabling signal that receive.

Conducting or the cut-off of switching device in the switching signal control output circuit of exporting by signal processing circuit, what the conducting of switching device or cut-off will continue to the oscillating circuit being made up of resistance and electric capacity in output circuit carries out charging and discharging, thereby the voltage of resistance and electric capacity common port in output circuit is changed with the charging and discharging of oscillating circuit, and then control chip is inputed to the difference of duty ratio of signal in adjacent two cycles of the control signal of Intelligent Power Module and the comparison of predetermined threshold and be converted to the size of output circuit output voltage.

Second voltage and predeterminated voltage value that the first voltage of the first output circuit 444 being exported by voltage comparator or the second output circuit 445 are exported compare, generate the first enabling signal or the second enabling signal according to comparative result, the first enabling signal and the second enabling signal are as the input of trigger 448, according to the characteristic of trigger 448, generate first signal or secondary signal, and then the size of output circuit output voltage is converted into first signal or secondary signal, thereby the accurately switching of control circuit operating state.

Describe signal processing circuit according to an embodiment of the invention in detail below in conjunction with Fig. 4 C, Fig. 4 C shows the structural representation of signal processing circuit according to an embodiment of the invention.

As shown in Figure 4 C, signal processing circuit according to an embodiment of the invention, comprise that first signal treatment circuit 442 and secondary signal process 443 circuit, described first signal treatment circuit 442 comprises: the first delay circuit 442A, be connected between signal source and ground, input is connected to the output of described control chip, and the control signal of described control chip output is postponed to one-period; The first logical circuit 442B, the first input end of described the first logical circuit 442B is connected to the output of described the first delay circuit 442A, the second input of described the first logical circuit 442B is connected to the output of described control chip, for the described control signal after described control signal and delay one-period is compared; The first inverter 442C, the input of described the first inverter 442C is connected to the output of described the first logical circuit 442B, the output of described the first inverter 442C is connected to the control end of described the first switching device, anti-phase for the signal of described the first logical circuit 442B output is carried out, and use the first switching device described in the signal controlling after anti-phase; Described secondary signal treatment circuit 443 comprises: the second delay circuit 443A, be connected between signal source and ground, and input is connected to the output of described control chip, and the control signal of described control chip output is postponed to one-period; The second logical circuit 443B, the first input end of described the second logical circuit 443B is connected to the output of described the second delay circuit 443A, the second input of described the second logical circuit 443B is connected to the output of described control chip, for the described control signal after described control signal and delay one-period is compared; The second inverter 443C, the input of described the second inverter 443C is connected to the output of described the second logical circuit 443B, the output of described the second inverter 443C is connected to the control end of described second switch device, anti-phase for the signal of described the second logical circuit 443B output is carried out, and use second switch device described in the signal controlling after anti-phase.

By input signal is carried out to time delay one-period, and using the control signal after time delay with do not pass through the control signal of time delay as the input of the first logical circuit 442B or the second logical circuit 443B, carry out logical operation, control chip is inputed to the signal in adjacent two cycles of the control signal of Intelligent Power Module and carry out logical operation, and with inversion signal control first switching device of logic operation result and conducting or the cut-off of second switch device, to obtain the output voltage of output circuit, i.e. the first voltage and second voltage.

According to one embodiment of present invention, the gate circuit that described the first logical circuit 442B is logical AND, described the second logical circuit 443B is the gate circuit of logic XOR.

Inputing to the larger cycle of duty ratio in adjacent two cycles of control signal of Intelligent Power Module taking control chip is period 1 signal, the smaller cycle of duty be second round signal be example, the signal in adjacent two cycles that inputs to the control signal of Intelligent Power Module due to control chip is respectively as the input of the first logical circuit 442B or the second logical circuit 443B, therefore, in the time that the first logical circuit 442B is logical AND circuit, the duty ratio of logical AND circuit output signal is the duty ratio of signal second round; And in the time that the second logical circuit 443B is logic XOR circuit, the duty ratio of logic XOR circuit output signal be period 1 signal and second round signal duty ratio poor.

When the difference that inputs to the duty ratio in adjacent two cycles of the control signal of Intelligent Power Module at control chip is less than predetermined threshold, the second switching signal duty ratio of the second logical circuit 443B output is less than predetermined threshold, the second voltage that the second output circuit 445 is exported will be less than predeterminated voltage value, trigger 448 is will export secondary signal while continuing low level at the second input, only makes low-consumption power element 42 in running order, due to second round, the duty ratio of signal is less, period 1 signal and second round signal the difference of duty ratio larger, and in the time that the difference that control chip inputs to the duty ratio in adjacent two cycles of the control signal of Intelligent Power Module is more than or equal to predetermined threshold, the duty of the first switching signal of the first logical circuit 442B output is smaller, the first voltage that the first output circuit 444 is exported will be less than predeterminated voltage value, trigger 448 is will export first signal while continuing low level at first input end, make IGBT pipe and low-power consumption element 42 simultaneously in running order.

According to one embodiment of present invention, described the first delay circuit 442A comprises: the 3rd resistance and the first switching tube, described the 3rd resistance and described the first switching tube are connected between described signal source and ground, and the control end of described the first switching tube is connected to the output of described control chip; The 3rd electric capacity, is connected in parallel on the two ends of described the 3rd resistance and described the first switching tube; The 3rd inverter, the common port of the 3rd electric capacity and described the 3rd resistance described in the input of described the 3rd inverter, the output of described the 3rd inverter is connected to the input of described the first logical circuit 442B; Described the second delay circuit 443A comprises: the 4th resistance and second switch pipe, and described the 4th resistance and described second switch pipe string are associated between described signal source and ground, and the control end of described second switch pipe is connected to the output of described control chip; The 4th electric capacity, is connected in parallel on the two ends of described the 4th resistance and described second switch pipe; The 4th inverter, the common port of the 4th electric capacity and described the 4th resistance described in the input of described the 4th inverter, the output of described the 4th inverter is connected to the input of described the second logical circuit 443B.

By the control signal time delay one-period to control chip output, can carry out logical operation to the signal in adjacent two cycles of the control signal of control chip output.Wherein, conducting or the cut-off of switching tube in the control signal control delay circuit of control chip output, control the charging and discharging time that is formed oscillating circuit in delay circuit by resistance and electric capacity, by the size of regulating resistance and electric capacity, the delay cycle of adjustable delay circuit.

According to one embodiment of present invention, described state control circuit 441 comprises: the 3rd logical circuit (not shown), the first input end of described the 3rd logical circuit is connected to the output of described trigger 448, the second input is connected to the output of described control chip, output is connected to the first drive circuit, for in the situation that receiving described first signal, described the first drive circuit will be exported to from the control signal of described control chip, in the situation that receiving described secondary signal, stop and export described the first drive circuit to from the control signal of described control chip, the 4th logical circuit (not shown), the first input end of described the 4th logical circuit and the second input are all connected to the signal output part of described control chip, for exporting described the second drive circuit to from the control signal of described control chip, wherein, described the first drive circuit for described arbitrary IGBT pipe is driven, described the second drive circuit is for driving described low-power consumption switch element.

Control signal by first signal or secondary signal and control chip output is carried out logical operation, control the operating state of the first drive circuit, also control the operating state of arbitrary IGBT pipe in Intelligent Power Module, thereby make in the time receiving first signal, make IGBT pipe and low-power consumption switch element 42 simultaneously in running order, thereby avoid low-power consumption switch element to be punctured by overcurrent, contribute to guarantee the fail safe of intelligent power consumption module.In the time receiving secondary signal, only make low-power consumption switch element 42 in running order, thereby can avoid in prior art, because the smearing of IGBT pipe causes unnecessary working loss, contributing to reduce the overall power of Intelligent Power Module.

By the gate circuit of logical AND, how the control signal that no matter inputs to intelligent power control module is changed, low-power consumption switch element 42 is all in running order, and owing to being control signal with an input of the logical AND gate being connected of IGBT pipe, another input is first signal or secondary signal, thereby the operating state of IGBT pipe can be subject to the control of first signal and secondary signal, realize the switching of operating state.

Describe the circuit structure diagram of embodiments of the invention in detail below in conjunction with Fig. 5 to Fig. 8.

Fig. 5 shows the structural representation of Intelligent Power Module according to an embodiment of the invention.

As shown in Figure 5, Intelligent Power Module 4100 according to an embodiment of the invention, Fig. 5 is the circuit diagram after output gating circuit 4400 is simplified, output gating circuit 4400 is switching controls module.

The power positive end VCC end of output gating circuit 4400 is as the low-pressure area power supply anode VDD of described Intelligent Power Module 4100, and VDD is generally 15V; The first input end HIN1 of described output gating circuit 4400 goes up brachium pontis input UHIN mutually as the U of described Intelligent Power Module 4100; The second input HIN2 of described output gating circuit 4400 goes up brachium pontis input VHIN mutually as the V of described Intelligent Power Module 4100; The 3rd input HIN3 of described output gating circuit 4400 goes up brachium pontis input WHIN mutually as the W of described Intelligent Power Module 4100; The four-input terminal LIN1 of described output gating circuit 4400 descends brachium pontis input ULIN mutually as the U of described Intelligent Power Module 4100; The 5th input LIN2 of described output gating circuit 4400 descends brachium pontis input VLIN mutually as the V of described Intelligent Power Module 4100; The 6th input LIN3 of described output gating circuit 4400 descends brachium pontis input WLIN mutually as the W of described Intelligent Power Module 4100; The power supply negative terminal GND of described output gating circuit 4400 is as the low-pressure area power supply negative terminal COM of described Intelligent Power Module 4100.

The U phase higher-pressure region power supply anode VB1 of described output gating circuit 4400 is connected with one end of electric capacity 4133, and as the U phase higher-pressure region power supply anode UVB of described Intelligent Power Module 4100; The U phase higher-pressure region power supply negative terminal VS1 of described output gating circuit 4400 is connected with the other end of described electric capacity 4133, and as the U phase higher-pressure region power supply negative terminal UVS of described Intelligent Power Module 4100.

The V phase higher-pressure region power supply anode VB2 of described output gating circuit 4400 is connected with one end of electric capacity 4132, and as the V phase higher-pressure region power supply anode VVB of described Intelligent Power Module 4100; The V phase higher-pressure region power supply negative terminal VS2 of described output gating circuit 4400 is connected with the other end of described electric capacity 4132, and as the V phase higher-pressure region power supply negative terminal VVS of described Intelligent Power Module 4100.

The W phase higher-pressure region power supply anode VB3 of described output gating circuit 4400 is connected with one end of electric capacity 4131, and as the W phase higher-pressure region power supply anode WVB of described Intelligent Power Module 4100; The W phase higher-pressure region power supply negative terminal VS3 of described output gating circuit 4400 is connected with the other end of described electric capacity 4131, and as the W phase higher-pressure region power supply negative terminal WVS of described Intelligent Power Module 4100.

The UHO end of described output gating circuit 4400 is connected with the grid of IGBT pipe 4121, the collector electrode of described IGBT pipe 4121 is connected with the negative electrode of FRD pipe 4111 and connects the ceiling voltage point P end of described Intelligent Power Module 4100, and the emitter-base bandgap grading of described IGBT pipe 4121 and described FRD manage that 4111 anode is connected and the UVS that connects described Intelligent Power Module 4100 holds.

The VHO end of described output gating circuit 4400 is connected with the grid of IGBT pipe 4122, the collector electrode of described IGBT pipe 4122 is connected with the negative electrode of FRD pipe 4112 and connects the ceiling voltage point P end of described Intelligent Power Module 4100, and the emitter-base bandgap grading of described IGBT pipe 4122 and described FRD manage that 4112 anode is connected and the VVS that connects described Intelligent Power Module 4100 holds.

The VHO end of described output gating circuit 4400 is connected with the grid of IGBT pipe 4123, the collector electrode of described IGBT pipe 4123 is connected with the negative electrode of FRD pipe 4113 and connects the ceiling voltage point P end of described Intelligent Power Module 4100, and the emitter-base bandgap grading of described IGBT pipe 4123 and described FRD manage that 4113 anode is connected and the WVS that connects described Intelligent Power Module 4100 holds.

The ULO1 end of described Intelligent Power Module 4100 is connected with the grid of IGBT pipe 4124, and the ULO2 end of described Intelligent Power Module 4100 is connected with the grid of NMOS pipe 4114; The collector electrode of described IGBT pipe 4124 is connected with the drain electrode of described high pressure NMOS pipe 4114 and connects the UVS end of described Intelligent Power Module 4100, and the emitter-base bandgap grading of described IGBT pipe 4124 is connected with source electrode with the substrate of described high pressure NMOS pipe 4114 and the UN that connects described Intelligent Power Module 4100 holds.

The VLO1 end of described Intelligent Power Module 4100 is connected with the grid of IGBT pipe 4125, and the VLO2 end of described Intelligent Power Module 4100 is connected with the grid of NMOS pipe 4115; The collector electrode of described IGBT pipe 4125 is connected with the drain electrode of described high pressure NMOS pipe 4115 and connects the VVS end of described Intelligent Power Module 4100, and the emitter-base bandgap grading of described IGBT pipe 4124 is connected with source electrode with the substrate of described high pressure NMOS pipe 4115 and the VN that connects Intelligent Power Module 4100 holds.

The WLO1 end of described Intelligent Power Module 4100 is connected with the grid of IGBT pipe 4125, and the WLO2 end of described Intelligent Power Module 4100 is connected with the grid of NMOS pipe 4115; The collector electrode of described IGBT pipe 4125 is connected with the drain electrode of described high pressure NMOS pipe 4115 and connects the WVS end of described Intelligent Power Module 4100, and the emitter-base bandgap grading of described IGBT pipe 4125 is connected with source electrode with the substrate of described high pressure NMOS pipe 4115 and the WN that connects described Intelligent Power Module 4100 holds.

The effect of described output gating circuit 4400 is:

When entering the duty ratio gap in adjacent two cycles of control signal of described output gating circuit 4400 inputs when larger, the signal of LIN1 can be controlled the output of ULO1 and ULO2 simultaneously, the signal of LIN2 can be controlled the output of VLO1 and VLO2 simultaneously, and the signal of LIN3 can be controlled the output of WLO1 and WLO2 simultaneously; When enter described output gating circuit 4400 inputs control signal adjacent two cycles duty ratio gap hour, the output of the signal controlling ULO2 of LIN1, the output of the signal controlling VLO2 of LIN2, the output of the signal controlling WLO2 of LIN3.

The output of the signal controlling control UHO of HIN1, the output of the signal controlling control VHO of HIN2, the output of the signal controlling control WHO of HIN3.

Because when the duty ratio gap in adjacent two cycles of the control signal of described output gating circuit 4400 inputs is larger, representative needs described Intelligent Power Module 4100 to produce break-make speed faster, need described Intelligent Power Module 4100 to produce the current capacity strengthening, at this moment the signal of LIN1, LIN3, LIN3 is controlled respectively ULO1 and ULO2, VLO1 and VLO2, WLO1 and WLO2 simultaneously, under Synchronization Control, the break-make of the IGBT of brachium pontis pipe and high pressure NMOS pipe, makes described Intelligent Power Module 4100 that enough current capacities can be provided, the duty ratio gap in adjacent two cycles of the control signal of described output gating circuit 4400 inputs hour, representative needs the break-make speed of described Intelligent Power Module 4100 not high, only need described Intelligent Power Module 4100 that less current capacity is provided, at this moment LIN1, LIN3, the signal of LIN3 is only controlled respectively ULO2, VLO2, WLO2, only control the break-make of the high pressure NMOS pipe of lower brachium pontis, although the lower brachium pontis current capacity of described Intelligent Power Module 4100 is at this moment lower, but can produce switching speed faster, although upper brachium pontis still uses IGBT pipe as on-off element, there is smearing, but because reliable turn-off of lower brachium pontis, even if upper brachium pontis not yet turn-offs generation current loop again, therefore can reach the object that reduces system power dissipation.

Fig. 6 shows the electrical block diagram of switching controls module according to an embodiment of the invention.

As shown in Figure 6, the circuit of switching controls module according to an embodiment of the invention, Fig. 6 is will output gating circuit 4400(switching controls module) circuit diagram after specializing.

The present embodiment is that the input signal of WLIN is detected, by the judgement of the duty ratio to WLIN signal, output is switched, because ULIN, VLIN, WLIN signal full symmetric, so the method detecting by the input signal of ULIN, VLIN is with the method for WLIN.

The low-pressure area power supply anode VCC of described output gating circuit 4400 and the negative terminal of current source 5206, the negative terminal of current source 5211, the negative terminal of current source 5306, the negative terminal of current source 5311, the low-pressure area power supply anode of UH drive circuit 5001, the low-pressure area power supply anode of VH drive circuit 5001, the low-pressure area power supply anode of WH drive circuit 5003, the low-pressure area power supply anode of UL drive circuit 5004, the low-pressure area power supply anode of VL drive circuit 5005, the low-pressure area power supply anode of WL drive circuit 5006 is connected.

WLIN connects the input of not gate 5201, the input of not gate 5202; The input of the output termination not gate 5209 of described not gate 5201; The input of the output termination delay circuit 5217 of described not gate 5202, the input of the output termination not gate 5207 of described delay circuit 5217; The Power supply that described delay circuit 5217 is made up of VCC and GND; The input of the output termination not gate 5208 of described not gate 5207; The input of the output termination not gate 5209 of described not gate 5201; The output termination of described not gate 5208 and door one of them input of 5210, described in the output termination of described not gate 5209 with another input of door 5210; The input of described and door 5210 output termination not gate 5217; The grid of the output termination NMOS pipe 5213 of described not gate 5217; The substrate of described NMOS pipe 5213 is connected with source electrode and meets GND; One end of the drain electrode contact resistance 5212 of described NMOS pipe 5213; One end of the anode of current source 5211, electric capacity 5214 and the positive input terminal of voltage comparator 5216 described in another termination of described resistance 5212; The other end of described electric capacity 5214 is connected with GND; The anode of voltage source 5215 is connected with the negative input end of described voltage comparator 5216, and the negative terminal of described voltage source 5215 is connected with GND; The output of described voltage comparator 5216 is connected with the R end of rest-set flip-flop 5401.

WLIN connects the input of not gate 5301, the input of not gate 5302; The input of the output termination not gate 5309 of described not gate 5301; The input of the output termination delay circuit 5217 of described not gate 5202, the input of the output termination not gate 5207 of described delay circuit 5217; The Power supply that described delay circuit 5217 is made up of VCC and GND; The input of the output termination not gate 5308 of described not gate 5307; The input of the output termination not gate 5309 of described not gate 5301; One of them input of the output termination XOR gate 5310 of described not gate 5308, described in the output termination of described not gate 5309 with another input of door 5310; The input of described and door 5310 output termination not gate 5317; The grid of the output termination NMOS pipe 5313 of described not gate 5317; The substrate of described NMOS pipe 5313 is connected with source electrode and meets GND; One end of the drain electrode contact resistance 5312 of described NMOS pipe 5313; One end of the anode of current source 5311, electric capacity 5314 and the positive input terminal of voltage comparator 5316 described in another termination of described resistance 5312; The other end of described electric capacity 5314 is connected with GND; The anode of voltage source 5315 is connected with the negative input end of described voltage comparator 5316, and the negative terminal of described voltage source 5315 is connected with GND; The output of described voltage comparator 5316 is connected with the S end of rest-set flip-flop 5401.

The Q end of described rest-set flip-flop 5401 with door 5115, with door 5114, with door 5125, with door 5124, with door 5135, be connected with one end of door 5124.

UHIN is connected with the input of described UH drive circuit; VHIN is connected with the input of described VH drive circuit; WHIN is connected with the input of described WH drive circuit; ULIN is connected with the other end of door 5114 with described with the other end of door 5115 with described; VLIN is connected with the other end of door 5124 with described with the other end of door 5125 with described; WLIN is connected with the other end of door 5134 with described with the other end of door 5135 with described; Describedly be connected with the input of described UL drive circuit 15014 with the output of door 5115; Describedly be connected with the input of described UL drive circuit 25024 with the output of door 5114; Describedly be connected with the input of described VL drive circuit 15015 with the output of door 5125; Describedly be connected with the input of described VL drive circuit 25025 with the output of door 5124;

Describedly be connected with the input of described WL drive circuit 15016 with the output of door 5135;

Describedly be connected with the input of described WL drive circuit 25026 with the output of door 5134;

The low-pressure area power supply negative terminal of the low-pressure area power supply negative terminal of the low-pressure area power supply negative terminal of the low-pressure area power supply negative terminal of the low-pressure area power supply negative terminal of the low-pressure area power supply negative terminal of described UH drive circuit 5001, described VH drive circuit 5001, described WH drive circuit 5003, described UL drive circuit 5004, described VL drive circuit 5005, described WL drive circuit 5006 is connected, and connects GND.

The VB1 end of described output gating circuit 4400 is connected with the higher-pressure region power supply anode of described UH drive circuit 5001; The VS1 end of described output gating circuit 4400 is connected with the higher-pressure region power supply negative terminal of described UH drive circuit 5001.

The VB2 end of described output gating circuit 4400 is connected with the higher-pressure region power supply anode of described VH drive circuit 5002; The VS2 end of described output gating circuit 4400 is connected with the higher-pressure region power supply negative terminal of described VH drive circuit 5002.

The VB3 end of described output gating circuit 4400 is connected with the higher-pressure region power supply anode of described WH drive circuit 5003; The VS3 end of described output gating circuit 4400 is connected with the higher-pressure region power supply negative terminal of described WH drive circuit 5003.

Wherein, the function of described UH drive circuit 5001 is identical with the described UH drive circuit 101 of prior art, the function of described VH drive circuit 5002 is identical with the described VH drive circuit 102 of prior art, the function of described WH drive circuit 5003 is identical with the described WH drive circuit 103 of prior art, the function of described UL drive circuit 15014 is identical with the described UL drive circuit 104 of prior art, the function of described VL drive circuit 15015 is identical with the described VL drive circuit 105 of prior art, the function of described WL drive circuit 15016 is identical with the described WL drive circuit 106 of prior art.

The operation principle of the present embodiment is described below in conjunction with the concrete oscillogram of Fig. 7.

Can find out from Fig. 3 A and Fig. 3 B, when compressor operating is during at high frequency, the difference of the duty ratio during adjacent two week is 60%, when compressor operating is during at low frequency, the difference of the duty ratio during adjacent two week is 20%, this specific embodiment carries out parameter designing according to above condition, according to different driven compressor algorithms, likely after several cycles of interval, just can embody compressor operating difference between cycle duty ratio under different frequency, at this moment, adjust accordingly according to the design principle of the present embodiment.

Fig. 7 shows the waveform schematic diagram of control signal while carrying out sequencing control according to embodiments of the invention Intelligent Power Module.

As shown in Figure 7, the input signal of WLIN, through described delay circuit 5217, makes signal delay one-period arrive A203, arrives A211 through described not gate 5208, thereby obtains postponing than WLIN the signal of one-period at A211 point; And the input signal of WLIN is after described not gate 5201 and described not gate 5209, obtain the on all four signal with WLIN, after described and door 5210, when compressor operating is during at high frequency, obtain the signal of 20% duty ratio at A206, when compressor operating is during at low frequency, obtain the signal of 40% duty ratio at A206.

The input signal of WLIN, through described delay circuit 5317, makes signal delay one-period arrive A303, arrives A311 through described not gate 5308, thereby obtains postponing than WLIN the signal of one-period at A311 point; And the input signal of WLIN is after described not gate 5301 and described not gate 5309, obtain the on all four signal with WLIN, after described XOR gate 5310, when compressor operating is during at high frequency, obtain the signal of 60% duty ratio at A306, when compressor operating is during at low frequency, obtain the signal of 20% duty ratio at A306.

The signal of A206 is after described not gate 5217 is anti-phase, arrive the charging circuit being formed by described current source 5211, described resistance 5212, described NMOS pipe 5213, described electric capacity 5214, when compressor operating is during at high frequency, the time that had 20% cycle is that electric capacity 5214 charges, when compressor operating is during at low frequency, the time that had 40% cycle is that electric capacity 5214 charges.

For described voltage source 5215 designs suitable magnitude of voltage VA209, make described electric capacity 5214 need the charging interval in 30% cycle just can make the voltage of described electric capacity 5214 reach this value; , when compressor operating is during at low frequency, the output of described voltage comparator 5216 there will be high level, otherwise keeps low level always.

The signal of A306 is after described not gate 5317 is anti-phase, arrive the charging circuit being formed by described current source 5311, described resistance 5312, described NMOS pipe 5313, described electric capacity 5314, when compressor operating is during at high frequency, the time that had 60% cycle is that electric capacity 5214 charges, when compressor operating is during at low frequency, the time that had 20% cycle is that electric capacity 5214 charges.

For described voltage source 5315 designs suitable magnitude of voltage VA309, make described electric capacity 5314 need the charging interval in 30% cycle just can make the voltage of described electric capacity 5314 reach this value; , when compressor operating is during at high frequency, the output of described voltage comparator 5316 there will be high level, otherwise keeps low level always.

When compressor becomes while being operated in high frequency from being operated in low frequency, the Q output of described rest-set flip-flop becomes high level and keeps; When compressor becomes while being operated in low frequency from being operated in high frequency, the Q output of described rest-set flip-flop becomes low level and keeps.

In the time that the Q of described rest-set flip-flop output is high level, described and door 5115, described and door 5125, output described and 5135 are consistent with the input signal of ULIN, VLIN, WLIN respectively, the signal that is ULO1, VLO1, WLO1 is the same with the signal of ULO2, VLO2, WLO2 respectively, controlled by ULIN, VLIN, WLIN; And in the time that the Q of described rest-set flip-flop output is low level, described and door 5115, describedly remain on low level with door 5125, output described and 5135, the signal that is ULO1, VLO1, WLO1 remains on low level, only has the signal of ULO2, VLO2, WLO2 controlled by ULIN, VLIN, WLIN; Thereby reached when compressor operating is in high frequency IGBT and the low power consumption control element break-make simultaneously of brachium pontis at present, when compressor operating low frequency at present brachium pontis only have the object of low power consumption control element break-make.

Further illustrate the parameter designing of the each Primary Component of the present invention below in conjunction with Fig. 8, Fig. 8 shows the structural representation of delay circuit according to an embodiment of the invention.

It is identical that described delay circuit 5217 and described delay circuit 5317 can be designed to, the explanation as an example of delay circuit 5217 example, and described delay circuit 5217 is formed by 20 units in series as shown in Figure 8.

A2011 connects the grid of NMOS pipe 5203; The substrate of described NMOS pipe 5203 is connected with source electrode and meets GND; One end of the drain electrode connecting resistance 5204 of described NMOS pipe 5203, the anode of current source 5206, one end of electric capacity 5205, the input of not gate 5207 described in another termination of described resistance 5204; The output termination A2031 of described not gate 5207.

The value of described current source 5206, described resistance 5204, described NMOS pipe 5203, described electric capacity 5205, described not gate 5207.

The threshold value Vth of described not gate 5207 is designed to 5V, and the capacitance Cd of described electric capacity 5205 is designed to 100pF, and the electric current I d of described current source 5206, the time td, the voltage Vd of described electric capacity 5205 that charge for described electric capacity 5205 exist following relation:

Id = \frac{Cd \cdot Vd}{td}

In the time of td=0.05 × 1/6kHz, Vd reaches Vth=5V, and substitution above formula obtains Id=60uA.

The breadth length ratio of described NMOS pipe 5203 designs very littlely, as 2 μ m/1 μ m, when described NMOS manages 5203 conductings and flows through the electric current of uA level, its conducting resistance almost can be ignored, if the time that described in when described NMOS manages 5203 conducting, electric capacity 5205 discharges by described resistance 5204 is tf, there is following relation with the resistance Rd of described resistance:

Rd = \frac{- tf}{Cd \cdot \ln \frac{Vd}{VCC}}

In the time of tf=0.05 × 1/6kHz, Vd drops to Vth=5V, and VCC is generally 15V, and substitution above formula obtains Rd=15k Ω.

Because 0.05 cycle of unit time delay, therefore more than 20 unit can 1 cycle of time delay.

The value of described current source 5211, described resistance 5212, described NMOS pipe 5213, described electric capacity 5214, described voltage source 5215 can be designed to identical with the value of described current source 5311, described resistance 5312, described NMOS pipe 5313, described electric capacity 5314, described voltage source 5315 respectively, and the value of described current source 5211, described resistance 5212, described NMOS pipe 5213, described electric capacity 5214, described voltage source 5215 is below described:

The value Vthm of described current source 5215 is designed to 5V, and the capacitance Cm of described electric capacity 5214 is designed to 100pF, and the electric current I m of described current source 5211, the time tm, the voltage Vm of described electric capacity 5214 that charge for described electric capacity 5214 exist following relation:

Im = \frac{Cm \cdot Vm}{tm}

In the time of td=0.3 × 1/6kHz, Vm reaches Vthm=5V, and substitution above formula obtains Id=10uA;

The breadth length ratio of described NMOS pipe 5213 designs very littlely, as 1 μ m/0.5 μ m, when described NMOS manages 5213 conductings and flows through the electric current of uA level, its conducting resistance almost can be ignored, the resistance Rm of described resistance can be designed to 100 Ω, the time that described in when establishing described NMOS and managing 5213 conducting, electric capacity 5205 discharges by described resistance 5212 is very short, only has several millesimal cycles, can ensure the rapid discharge waveform as Fig. 7.

More than be described with reference to the accompanying drawings technical scheme of the present invention, the present invention proposes a kind of power control circuit, a kind of Intelligent Power Module and a kind of frequency-conversion domestic electric appliances, can realize following technique effect:

In the time that Intelligent Power Module need to produce larger drive current, Intelligent Power Module can provide the on-off element with enough current capacities, because when system needs large drive current, always wish to obtain enough energy fast and pay close attention to less to power consumption, even so switching loss is now higher, do not affect overall system performance evaluation yet.

In the time that Intelligent Power Module needs less drive current, Intelligent Power Module can provide the on-off element that switching loss is less, because when system needs little drive current, always wish to obtain energy consumption still less, so, in the situation that current capacity meets system requirements, less switching loss can improve overall system performance evaluation.

In the time of little electric current, Intelligent Power Module of the present invention can switch to the pattern of only having the low-power consumption element work that switching loss is less in time, can effectively reduce the energy consumption of Intelligent Power Module; And in the time of large electric current, Intelligent Power Module of the present invention can switch to again in time to be had the on-off element (IGBT pipe) of larger current capacity and has the pattern that the on-off element (low-power consumption element) of small electric stream ability is worked simultaneously, avoid the element damage causing because electric current is excessive, effectively improve the robustness of Intelligent Power Module, avoid Intelligent Power Module because pursuing the negative effects such as low energy consumption causes that overcurrent punctures, thereby the combination property of Intelligent Power Module is improved.

On-off element while using high pressure NMOS pipe as little electric current, can directly utilize the parasitic diode of high pressure NMOS pipe self as anti-paralleled diode, make lower brachium pontis without re-using FRD pipe, aspect on-off element, compared with prior art, cost increase is very limited in the present invention; In addition, switch different on-off elements according to different current capacity demands, no longer large current switching element is proposed to harsh switching characteristic requirement, can low cost realize the little energy consumption under the little electric current of Intelligent Power Module.

The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. a power control circuit, is characterized in that, comprising:

Low-power consumption switch element, is connected in parallel to the arbitrary IGBT pipe in Intelligent Power Module, to form switch module;

Switching controls module, be connected to control chip corresponding to described Intelligent Power Module, the duty ratio of the signal in adjacent two cycles of the control signal of exporting for detection of described control chip, and calculate the duty cycle difference of the signal in described adjacent two cycles, in the situation that described duty cycle difference is more than or equal to predetermined threshold, make described arbitrary IGBT pipe and described low-power consumption switch element simultaneously in running order, in the situation that described duty cycle difference is less than predetermined threshold, only make described low-power consumption switch element in running order.

2. power control circuit according to claim 1, it is characterized in that, described switching controls module, in the situation that described difference is more than or equal to predetermined threshold, makes described arbitrary IGBT pipe and described low-power consumption switch element simultaneously in running order, and described switching controls module comprises:

Signal output apparatus, is connected to described control chip, for export first signal in the situation that described difference is more than or equal to predetermined threshold, and in the situation that described difference is less than predetermined threshold, exports secondary signal;

State control circuit, be connected to described signal output apparatus, for in the time that described state control circuit receives first signal, control described arbitrary IGBT pipe and described low-power consumption switch element simultaneously in running order, and in the time that described state control circuit receives secondary signal, control described low-power consumption switch element in running order.

3. power control circuit according to claim 2, is characterized in that, described signal output apparatus comprises:

First signal treatment circuit, is connected to described control chip, the control signal of described control chip output is processed, to obtain the first switching signal;

Secondary signal treatment circuit, is connected to described control chip, the control signal of described control chip output is processed, to obtain the second switching signal;

The first output circuit, described the first output circuit comprises:

The first electric capacity, described the first electric capacity is connected between signal source and ground;

The first switching device and the first resistance, after described the first switching device is connected with described the first resistance, be parallel to the two ends of described the first electric capacity, described the first switching device is also connected to described first signal treatment circuit, for carrying out conducting or cut-off according to described the first switching signal;

The second output circuit, described the second output circuit comprises:

The second electric capacity, described the second electric capacity is connected between signal source and ground;

Second switch device and the second resistance, after described second switch device is connected with described the second resistance, be parallel to the two ends of described the second electric capacity, described second switch device is also connected to described secondary signal treatment circuit, for carrying out conducting or cut-off according to described the second switching signal;

The first voltage comparator, the first input end of described the first voltage comparator is connected to common port, the second input input predeterminated voltage value of described the first electric capacity and described the first resistance, for the first voltage and the predeterminated voltage value of described the first output circuit output are compared, and export the first enabling signal according to comparative result, wherein, in the time that the first voltage of described the first output circuit output is more than or equal to predeterminated voltage value, output high level, in the time that the first voltage of described the first output circuit output is less than predeterminated voltage value, output low level;

Second voltage comparator, the first input end of described second voltage comparator is connected to common port, second input of described the second electric capacity and described the second resistance and inputs described predeterminated voltage value, for second voltage and the predeterminated voltage value of described the second output circuit output are compared, and export the second enabling signal according to comparative result, wherein, in the time that the second voltage of described the second output circuit output is more than or equal to predeterminated voltage value, output high level, in the time that the second voltage of described the second output circuit output is less than predeterminated voltage value, output low level;

Trigger, the first end of described trigger is connected to the output of described the first voltage comparator, the second end of described trigger is connected to the output of described second voltage comparator, for exporting described first signal or described secondary signal according to the first enabling signal and the second enabling signal that receive.

4. power control circuit according to claim 3, is characterized in that, described first signal treatment circuit comprises:

The first delay circuit, is connected between signal source and ground, and input is connected to the output of described control chip, and the control signal of described control chip output is postponed to one-period;

The first logical circuit, the first input end of described the first logical circuit is connected to the output of described the first delay circuit, the second input of described the first logical circuit is connected to the output of described control chip, for the described control signal after described control signal and delay one-period is compared;

The first inverter, the input of described the first inverter is connected to the output of described the first logical circuit, the output of described the first inverter is connected to the control end of described the first switching device, anti-phase for the signal of described the first logical circuit output is carried out, and use the first switching device described in the signal controlling after anti-phase;

Described secondary signal treatment circuit comprises:

The second delay circuit, is connected between signal source and ground, and input is connected to the output of described control chip, and the control signal of described control chip output is postponed to one-period;

The second logical circuit, the first input end of described the second logical circuit is connected to the output of described the second delay circuit, the second input of described the second logical circuit is connected to the output of described control chip, for the described control signal after described control signal and delay one-period is compared;

The second inverter, the input of described the second inverter is connected to the output of described the second logical circuit, the output of described the second inverter is connected to the control end of described second switch device, anti-phase for the signal of described the second logical circuit output is carried out, and use second switch device described in the signal controlling after anti-phase.

5. power control circuit according to claim 4, is characterized in that, the gate circuit that described the first logical circuit is logical AND, and described the second logical circuit is the gate circuit of logic XOR.

6. power control circuit according to claim 4, is characterized in that,

Described the first delay circuit comprises:

The 3rd resistance and the first switching tube, described the 3rd resistance and described the first switching tube are connected between described signal source and ground, and the control end of described the first switching tube is connected to the output of described control chip;

The 3rd electric capacity, is connected in parallel on the two ends of described the 3rd resistance and described the first switching tube;

The 3rd inverter, the common port of the 3rd electric capacity and described the 3rd resistance described in the input of described the 3rd inverter, the output of described the 3rd inverter is connected to the input of described the first logical circuit;

Described the second delay circuit comprises:

The 4th resistance and second switch pipe, described the 4th resistance and described second switch pipe string are associated between described signal source and ground, and the control end of described second switch pipe is connected to the output of described control chip;

The 4th electric capacity, is connected in parallel on the two ends of described the 4th resistance and described second switch pipe;

The 4th inverter, the common port of the 4th electric capacity and described the 4th resistance described in the input of described the 4th inverter, the output of described the 4th inverter is connected to the input of described the second logical circuit.

7. power control circuit according to claim 2, is characterized in that, described state control circuit comprises:

The 3rd logical circuit, the first input end of described the 3rd logical circuit is connected to the output of described trigger, output, the output that the second input is connected to described control chip is connected to the first drive circuit, for in the situation that receiving described first signal, described the first drive circuit will be exported to from the control signal of described control chip, in the situation that receiving described secondary signal, stop and export described the first drive circuit to from the control signal of described control chip;

The 4th logical circuit, the first input end of described the 4th logical circuit and the second input are all connected to the signal output part of described control chip, for exporting described the second drive circuit to from the control signal of described control chip;

Wherein, described the first drive circuit for described arbitrary IGBT pipe is driven, described the second drive circuit is for driving described low-power consumption switch element.

8. power control circuit according to claim 7, is characterized in that, the gate circuit that described the 3rd logical circuit and described the 4th logical circuit are logical AND.

9. an Intelligent Power Module, is characterized in that, comprises at least one power control circuit as described in any one in claim 1 to 8.

10. a frequency-conversion domestic electric appliances, is characterized in that, comprises Intelligent Power Module as claimed in claim 9.