CN204559408U

CN204559408U - Intelligent power module

Info

Publication number: CN204559408U
Application number: CN201520167941.4U
Authority: CN
Inventors: 冯宇翔
Original assignee: Midea Group Co Ltd; Guangdong Midea Refrigeration Equipment Co Ltd
Current assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Priority date: 2015-03-23
Filing date: 2015-03-23
Publication date: 2015-08-12
Anticipated expiration: 2025-03-23

Abstract

The utility model proposes a kind of Intelligent Power Module, comprise the first sampling resistor, the first end of the first sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the first voltage signal acquisition end of Intelligent Power Module of brachium pontis under U phase, and the second end of the first sampling resistor is as U phase low reference voltage end; Second sampling resistor, the first end of the second sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the second voltage signal acquisition end of Intelligent Power Module of brachium pontis under V phase, and the second end of the second sampling resistor is as V phase low reference voltage end; 3rd sampling resistor, the first end of the 3rd sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the tertiary voltage signals collecting end of Intelligent Power Module of brachium pontis under W phase, and the second end of the 3rd sampling resistor is as W phase low reference voltage end.By the technical solution of the utility model, environmentally can change the signal time regulating homophase upper and lower bridge arm voluntarily, to avoid the generation of the situation of conducting simultaneously, make Intelligent Power Module be operated in safe condition.

Description

Intelligent Power Module

Technical field

The utility model relates to power drive control technology field, in particular to a kind of Intelligent Power Module.

Background technology

Intelligent Power Module (IPM, Intelligent Power Module) is a kind of power drive series products in conjunction with power electronic technology and integrated circuit technique.Intelligent Power Module integrates device for power switching and high-voltage driving circuit, and is built-in with overvoltage, overcurrent and the failure detector circuit such as overheated.The state detection signal of system by receiving the control signal of MCU and driving subsequent conditioning circuit work, is fed back to MCU again by Intelligent Power Module on the one hand on the other hand.Compared with traditional discrete scheme, Intelligent Power Module wins increasing market with its advantage such as high integration, high reliability, being particularly suitable for the frequency converter of drive motors and various inverter, is the desired power level electronic device for frequency control, metallurgical machinery, electric traction, servo-drive and frequency-conversion domestic electric appliances.

The circuit structure of existing Intelligent Power Module 10 as shown in Figure 1, wherein:

HVIC (High Voltage Integrated Circuit, high voltage integrated circuit) the power end VCC of pipe 101 to power anode VDD as the low-pressure area of Intelligent Power Module, the voltage at VDD place is generally 15V, HVIC pipe 101 inside includes boostrap circuit, and the structure of this boostrap circuit is as follows:

The power end VCC of HVIC pipe 101 is connected with the anode of bootstrap diode D1, bootstrap diode D2, bootstrap diode D3, the negative electrode of bootstrap diode D1 and first of the HVIC pipe 101 anode VB1 that powers is connected, and the negative electrode of bootstrap diode D2 and second of the HVIC pipe 101 anode VB2 that powers is connected, and the negative electrode of bootstrap diode D3 and the 3rd of HVIC pipe 101 the anode VB3 that powers is connected, first input end IN1, the second input IN2 of HVIC pipe 101 and the 3rd input IN3 are respectively as U phase input UIN, V phase input VIN of Intelligent Power Module 10 and W phase input WIN, at this, the voltage range of three road input signals of U, V, W three-phase of Intelligent Power Module 10 is 0 ~ 5V, the earth terminal GND of HVIC pipe 101 to power negative terminal COM as the low-pressure area of Intelligent Power Module 10, first power supply anode VB1 of HVIC pipe 101 to power anode UVB be connected to one end of filter capacitor C1 as the U phase higher-pressure region of Intelligent Power Module 10, first higher-pressure region control end HO1 of HVIC pipe 101 is connected with the grid of IGBT pipe Q1, the emitter-base bandgap grading of the first power supply negative terminal VS1 and described IGBT pipe Q1 of HVIC pipe 101, the anode of FRD pipe D4, the collector electrode of IGBT pipe Q4, the negative electrode of FRD pipe D7 and the other end of filter capacitor C1 are connected, and to power negative terminal UVS as the U phase higher-pressure region of Intelligent Power Module 10, the U phase higher-pressure region that filter capacitor C1 the is connected to Intelligent Power Module 10 anode UVB that powers powers between negative terminal UVS with U phase higher-pressure region, second power supply anode VB2 of HVIC pipe 101 to power anode VVB be connected to one end of filter capacitor C2 as the V phase higher-pressure region of Intelligent Power Module, second higher-pressure region control end HO2 of HVIC pipe 101 is connected with the grid of IGBT pipe Q2, the emitter-base bandgap grading of the second power supply negative terminal VS2 and IGBT pipe Q2 of HVIC pipe 101, the anode of FRD pipe D5, the collector electrode of IGBT pipe Q5, the negative electrode of FRD pipe D8 and the other end of filter capacitor C2 are connected, and to power negative terminal VVS as the V phase higher-pressure region of Intelligent Power Module, the V phase higher-pressure region that filter capacitor C2 the is connected to Intelligent Power Module anode VVB that powers powers between negative terminal VVS with V phase higher-pressure region, 3rd power supply anode VB3 of HVIC pipe 101 to power anode WVB be connected to one end of filter capacitor C3 as the W phase higher-pressure region of Intelligent Power Module, the third high nip control end HO3 of HVIC pipe 101 is connected with the grid of IGBT pipe Q3, the emitter-base bandgap grading of the 3rd power supply negative terminal VS3 and IGBT pipe Q3 of HVIC pipe 101, the anode of FRD pipe D6, the collector electrode of IGBT pipe Q6, the negative electrode of FRD pipe D9 and the other end of filter capacitor C3 are connected, and to power negative terminal WVS as the W phase higher-pressure region of Intelligent Power Module, the W phase higher-pressure region that filter capacitor C3 the is connected to Intelligent Power Module anode WVB that powers powers between negative terminal WVS with W phase higher-pressure region, first low-pressure area control end LO1, the second low-pressure area control end LO2 of HVIC pipe 101 and the 3rd low-pressure area control end LO3 are connected with the grid of the grid of IGBT pipe Q4, the grid of IGBT pipe Q5 and IGBT pipe Q6 respectively, the emitter-base bandgap grading of IGBT pipe Q4 is connected with the anode of FRD pipe D7, and as the U phase low reference voltage end UN of Intelligent Power Module, the emitter-base bandgap grading of IGBT pipe Q5 is connected with the anode of FRD pipe D8, and as the V phase low reference voltage end VN of Intelligent Power Module, the emitter-base bandgap grading of IGBT pipe Q5 is connected with the anode of FRD pipe D9, and as the W phase low reference voltage end WN of Intelligent Power Module, the collector electrode of the collector electrode of IGBT pipe Q1, the negative electrode of FRD pipe D4, IGBT pipe Q2, the negative electrode of FRD pipe D5, the collector electrode of IGBT pipe Q3, the negative electrode of FRD pipe D6 connect altogether and as the high voltage input P of Intelligent Power Module, P generally accesses 300V voltage.

The effect of HVIC pipe 101 is: VDD is the power supply anode of HVIC pipe 101, and GND is the power supply negative terminal of HVIC pipe 101, and VDD-GND voltage is generally 15V;

The logic input signal of 0 of input UIN, VIN, WIN or 5V is passed to output HO1, HO2, HO3 respectively, the inversion signal of UIN, VIN, WIN passes to output LO1, LO2, LO3 respectively, the logic output signal of what wherein HO1, HO2 and HO3 exported is VS ~ VS+15V, LO1, LO2, LO3 are the logic output signals of 0 ~ 15V; The inside that UIN, VIN, WIN enter HVIC pipe 101 is divided into two contrary signals of phase place, such as being divided into HIN1 and LIN1, HIN2 and LIN2, HIN3 and LIN3 respectively, is then that input signal HIN1 and LIN1, HIN2 and LIN2, HIN3 and LIN3 of same phase can not be high level simultaneously.

When practical application, as shown in Figure 2, external capacitor C4 is connected between UVB and UVS the mode of connection of Intelligent Power Module 10, and external capacitor C5 is connected between VVB and VVS, and external capacitor C6 is connected between WVB and WVS; At this, filter capacitor C1, filter capacitor C2, filter capacitor C3 mainly strobe, and external capacitor C4, external capacitor C5, external capacitor C6 mainly play storing electricity effect; UN, VN, WN are connected to the first end of resistance R and the Pin7 of MCU pipe 20 altogether, second end of resistance R and COM are connected to ground altogether, the Pin1 of MCU pipe 20 holds with the UIN of Intelligent Power Module 10 and is connected, the Pin2 of MCU pipe 20 holds with the VIN of Intelligent Power Module 10 and is connected, the Pin3 of MCU pipe 20 holds with the WIN of Intelligent Power Module 10 and is connected, the vdd terminal of Intelligent Power Module 10 generally meets 15V, and the P end of Intelligent Power Module 10 generally meets 300V.

Below the operation principle that Intelligent Power Module 10 is described for U phase:

When the Pin1 of MCU pipe 20 sends low level signal, the HO1 of this low level signal HVIC pipe 101 is low level, makes the LO1 of HVIC pipe 101 be high level, thus IGBT pipe Q4 conducting and described IGBT pipe Q1 ends, thus VS1 voltage is about 0V; Bootstrap diode D1 forward bias, VCC charges to filter capacitor C1 and external capacitor C4, when time long enough or the dump energy before filter capacitor C1 and external capacitor C4 are charged abundant time, VB1 obtains the voltage close to 15V to VS1.

When the Pin1 of described MCU pipe 20 sends high level signal, this high level signal makes the HO1 of HVIC pipe 101 be high level, the LO1 of HVIC pipe 101 is made to be low level, thus IGBT pipe Q4 ends and IGBT pipe Q1 conducting, thus VS1 voltage is about 300V, VB1 voltage is lifted to about 315V, the work of U phase higher-pressure region is maintained by the electricity of filter capacitor C1 and external capacitor C4, if HIN1 is the duration of high level, electricity that is enough short or filter capacitor C1 and external capacitor C4 storage is abundant, VB1 can remain on more than 14V to the voltage of VS1 in the course of work of U phase higher-pressure region.

And in actual applications, because U, V, the circuit of W three-phase upper and lower bridge arm is inconsistent, so the time that two signals that phase place is contrary in theory arrive two outputs of HVIC pipe 101 is not quite identical, when the phase difference of the signal of the upper and lower bridge arm of same phase is not strict 180 °, the phenomenon of upper and lower bridge arm conducting simultaneously can be caused, for U phase, as shown in Figure 3, dotted line institute's frame region, there will be upper and lower bridge arm conducting simultaneously phenomenon, 5 μ s are greater than when the duration of dashed region, there will be IGBT pipe by overheated risk of burning, burn once IGBT pipe is overheated, Intelligent Power Module can be caused to explode, fire is even caused to occur, in addition, even if the duration of dashed region is no more than 5 μ s, each switch also can produce the phenomenon of of short duration upper and lower bridge arm conducting simultaneously, IGBT pipe is caused to generate heat serious, not only affect energy consumption, and the IGBT pipe range phase can be caused to be in weariness working state, service life reduction, make Intelligent Power Module there is potential safety hazard, Intelligent Power Module entirety can be caused burn or more serious consequence under certain condition excites.

Although, part Intelligent Power Module is designed by time delay, the duty ratio of one of them brachium pontis of same phase is made to be less than the duty ratio of another brachium pontis, but, but in order to ensure that Intelligent Power Module normally works, the duty ratio of homophase two brachium pontis can not differ too large, and this just causes along with the change of applied environment and the aging of element, the situation of homophase upper and lower bridge arm simultaneously conducting can be engendered, and then cause performance degradation in Intelligent Power Module Long-Time Service process, accelerate to reach useful life.

Therefore, need a kind of new Intelligent Power Module, environmentally can change the signal time regulating homophase upper and lower bridge arm voluntarily, to avoid the generation of the situation of conducting simultaneously, make Intelligent Power Module be operated in safe condition, and then extend the useful life of Intelligent Power Module.

Utility model content

The utility model is intended at least to solve one of technical problem existed in prior art or correlation technique.

For this reason, an object of the present utility model is to propose a kind of Intelligent Power Module, environmentally can change the signal time regulating homophase upper and lower bridge arm voluntarily, to avoid the generation of the situation of conducting simultaneously.

For realizing at least one object above-mentioned, according to the embodiment of the utility model first aspect, propose a kind of Intelligent Power Module, comprise: the first sampling resistor, the first end of described first sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the first voltage signal acquisition end of described Intelligent Power Module of the lower brachium pontis of U phase of described Intelligent Power Module, and the second end of described first sampling resistor is as the U phase low reference voltage end of described Intelligent Power Module; Second sampling resistor, the first end of described second sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the second voltage signal acquisition end of described Intelligent Power Module of the lower brachium pontis of V phase of described Intelligent Power Module, and the second end of described second sampling resistor is as the V phase low reference voltage end of described Intelligent Power Module; 3rd sampling resistor, the first end of described 3rd sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the tertiary voltage signals collecting end of described Intelligent Power Module of the lower brachium pontis of W phase of described Intelligent Power Module, and the second end of described 3rd sampling resistor is as the W phase low reference voltage end of described Intelligent Power Module.

According to the Intelligent Power Module of embodiment of the present utility model, by the first voltage signal acquisition end of this Intelligent Power Module, second voltage signal acquisition end and tertiary voltage signals collecting end gather respectively and monitor the first sampling resistor being positioned at Intelligent Power Module U phase, the curent change of the second sampling resistor of V phase and the 3rd sampling resistor of W phase, to control the pressure drop that the first sampling resistor produces to the 3rd sampling resistor, the IGBT of the upper and lower bridge arm circuit of U phase is managed, the IGBT pipe of the IGBT pipe of the upper and lower bridge arm circuit of V phase and the upper and lower bridge arm circuit of W phase respectively can not while conducting, Intelligent Power Module is made to be operated in safe condition, and then extend the useful life of Intelligent Power Module.

According to an embodiment of the present utility model, in technique scheme, preferably, when in the U phase of described Intelligent Power Module, the IGBT of brachium pontis manages the IGBT pipe conducting simultaneously of the lower brachium pontis with described U phase, the pressure drop of described first sampling resistor that described first voltage signal acquisition end collects is abnormal; Or when in the V phase of described Intelligent Power Module, the IGBT of brachium pontis manages the IGBT pipe conducting simultaneously of the lower brachium pontis with described V phase, the pressure drop of described second sampling resistor that described second voltage signal acquisition end collects is abnormal; Or when in the W phase of described Intelligent Power Module, the IGBT of brachium pontis manages the IGBT pipe conducting simultaneously of the lower brachium pontis with described W phase, the pressure drop of described 3rd sampling resistor that described tertiary voltage signals collecting end collects is abnormal.

According to the Intelligent Power Module of embodiment of the present utility model, when the IGBT of the upper and lower bridge arm circuit of U phase manage, the IGBT pipe of the IGBT pipe of the upper and lower bridge arm circuit of V phase and the upper and lower bridge arm circuit of W phase respectively conducting time, the pressure drop that corresponding sampling resistor produces is controlled, and when the IGBT of the upper and lower bridge arm circuit of U phase manage, the IGBT pipe conducting simultaneously of the IGBT pipe of the upper and lower bridge arm circuit of V phase and the upper and lower bridge arm circuit of W phase time, the electric current flowing through corresponding sampling resistor can become very large instantaneously, the pressure drop that then corresponding sampling resistor produces also can increase instantaneously, occurs abnormal.

According to an embodiment of the present utility model, in technique scheme, preferably, also comprise: HVIC manages, the power end of described HVIC pipe to be powered anode as the low-pressure area of described Intelligent Power Module, the first input end of described HVIC pipe, second input and the 3rd input are respectively the U phase input of described Intelligent Power Module, V phase input and W phase input, the four-input terminal of described HVIC pipe, 5th input and the 6th input are respectively the described first voltage signal acquisition end of described Intelligent Power Module, described second voltage signal acquisition end, described tertiary voltage signals collecting end, the earth terminal of described HVIC pipe to be powered negative terminal as the low-pressure area of described Intelligent Power Module.

According to an embodiment of the present utility model, in technique scheme, preferably, also comprise: U phase adjustment circuit, V phase adjustment circuit and W phase adjustment circuit, and described U phase adjustment circuit, described V phase adjustment circuit are identical with the circuit structure of described W phase adjustment circuit.

According to the Intelligent Power Module of embodiment of the present utility model, first voltage signal acquisition end of this Intelligent Power Module, second voltage signal acquisition end and tertiary voltage signals collecting end can be served as by three input correspondences of HVIC pipe respectively, and when three sampling resistor pressure drops are abnormal, by U phase adjustment circuit, V phase adjustment circuit and W phase adjustment circuit respectively automatic real-time online adjust and drive the IGBT of the upper and lower bridge arm circuit of U phase to manage, the cycle of the signal of the IGBT pipe of the IGBT pipe of the upper and lower bridge arm circuit of V phase and the upper and lower bridge arm circuit of W phase, the IGBT of the upper and lower bridge arm circuit of U phase is managed, the IGBT pipe conducting no longer simultaneously respectively of the IGBT pipe of the upper and lower bridge arm circuit of V phase and the upper and lower bridge arm circuit of W phase, and then make Intelligent Power Module be operated in safe condition, to extend the useful life of Intelligent Power Module.

According to an embodiment of the present utility model, in technique scheme, preferably, described U phase adjustment circuit specifically comprises: Schmidt trigger, the input of described Schmidt trigger is connected to the described first input end of described HVIC pipe, and the output of described Schmidt trigger is connected to the input of the first not gate and the input of the second not gate; The output of described first not gate is connected to the input of the 3rd not gate, and the output of described 3rd not gate is connected to the input of the 4th not gate; First delay adjustment circuit, the first end of described first delay adjustment circuit is connected to the described four-input terminal of described HVIC, second end ground connection of described first delay adjustment circuit, and the three-terminal link of described first delay adjustment circuit is to the output of described 3rd not gate; Second delay adjustment circuit, the first end of described second delay adjustment circuit is connected to the described four-input terminal of described HVIC, second end ground connection of described second delay adjustment circuit, and the three-terminal link of described first delay adjustment circuit is to the output of described 3rd not gate; The output of described 4th not gate is connected to the input of the 5th not gate; The output of described 5th not gate is connected to the first input end and first and the first input end of door of XOR gate; The output of described second not gate is connected to the input of the 6th not gate, and the output of described 6th not gate is connected to the input of the 7th not gate, and the output of described 7th not gate is connected to second input and second and the first input end of door of described XOR gate; The output of described XOR gate be connected to described first with the second input of door, described second with the second input of door; And described first with the output of door the first output as described U phase adjustment circuit; Described second with the output of door the second output as described U phase adjustment circuit.

According to an embodiment of the present utility model, in technique scheme, preferably, described first delay adjustment circuit is identical with the circuit structure of described second delay adjustment circuit.

According to an embodiment of the present utility model, in technique scheme, preferably, described first delay adjustment circuit specifically comprises: voltage comparator, the positive input terminal of described voltage comparator is as the described first end of described first delay adjustment circuit, the negative input end of described voltage comparator is connected to the anode of voltage source, and the output of described voltage comparator is connected to the S end of rest-set flip-flop; The negative terminal of described voltage source is as described second end of described first delay adjustment circuit; The R of described rest-set flip-flop holds ground connection, and the Q end of described rest-set flip-flop is connected to the input of the 8th not gate; Output and the grid being connected to NMOS tube of described 8th not gate; The substrate of described NMOS tube is connected with the source electrode of described NMOS tube, the first end of electric capacity and ground connection; Second end of described electric capacity is as described 3rd end of described first delay adjustment circuit.

According to an embodiment of the present utility model, in technique scheme, preferably, the value of described electric capacity is 3pF, and the voltage source of described first delay adjustment circuit is different from the value of the voltage source of described second delay adjustment circuit.

According to the Intelligent Power Module of embodiment of the present utility model, the preferred value of electric capacity is 3pF, can certainly adopt other capacitances according to actual conditions; And the voltage source of the first delay adjustment circuit and the value of the voltage source of the second delay adjustment circuit can be different, such as, the voltage source value of the first delay adjustment circuit can be 0.2V, and the value of the voltage source of the second delay adjustment circuit can be 0.3V.

According to an embodiment of the present utility model, in technique scheme, preferably, the resistance of described first sampling resistor, described second sampling resistor and described 3rd sampling resistor is 10m Ω.

According to the Intelligent Power Module of embodiment of the present utility model, the preferred resistance of three sampling resistors is 10m Ω, can certainly adopt other resistances according to actual conditions.

According to an embodiment of the present utility model, in technique scheme, preferably, the power voltage of anode of the described low-pressure area of described Intelligent Power Module is 15V.

According to the embodiment of the utility model second aspect, also proposed a kind of air conditioner, comprising: as the Intelligent Power Module described in above-mentioned any one embodiment.

Additional aspect of the present utility model and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present utility model.

Accompanying drawing explanation

Above-mentioned and/or additional aspect of the present utility model and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:

Fig. 1 shows the electrical block diagram of the Intelligent Power Module in correlation technique;

Fig. 2 shows the electrical block diagram in actual applications of the Intelligent Power Module shown in Fig. 1;

Fig. 3 shows each waveform voltage signal figure involved in the course of work of the Intelligent Power Module shown in Fig. 1 after electrifying startup;

Fig. 4 shows the electrical block diagram of the Intelligent Power Module according to an embodiment of the present utility model;

Fig. 5 shows the U phase adjustment circuit structural representation of the Intelligent Power Module shown in Fig. 4;

The level signal oscillogram that the U phase adjustment circuit that Fig. 6 shows the Intelligent Power Module shown in Fig. 5 is involved in the course of the work.

Embodiment

In order to more clearly understand above-mentioned purpose of the present utility model, feature and advantage, below in conjunction with the drawings and specific embodiments, the utility model is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.

Set forth a lot of detail in the following description so that fully understand the utility model; but; the utility model can also adopt other to be different from other modes described here and implement, and therefore, protection range of the present utility model is not by the restriction of following public specific embodiment.

The utility model proposes a kind of Intelligent Power Module, comprise: comprising: the first sampling resistor, the first end of described first sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the first voltage signal acquisition end of described Intelligent Power Module of the lower brachium pontis of U phase of described Intelligent Power Module, and the second end of described first sampling resistor is as the U phase low reference voltage end of described Intelligent Power Module; Second sampling resistor, the first end of described second sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the second voltage signal acquisition end of described Intelligent Power Module of the lower brachium pontis of V phase of described Intelligent Power Module, and the second end of described second sampling resistor is as the V phase low reference voltage end of described Intelligent Power Module; 3rd sampling resistor, the first end of described 3rd sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the tertiary voltage signals collecting end of described Intelligent Power Module of the lower brachium pontis of W phase of described Intelligent Power Module, and the second end of described 3rd sampling resistor is as the W phase low reference voltage end of described Intelligent Power Module.

Particularly, as shown in Figure 4, Intelligent Power Module 40, comprise: the first sampling resistor R1 is to the 3rd sampling resistor R3, the first end of described first sampling resistor R1 is connected to the emitter-base bandgap grading of IGBT pipe Q4 ' and the first voltage signal acquisition end of described Intelligent Power Module 40 of the lower brachium pontis of U phase of described Intelligent Power Module 40, and second end of described first sampling resistor R1 is as the U phase low reference voltage end UN ' of described Intelligent Power Module 40; The first end of described second sampling resistor R2 is connected to the emitter-base bandgap grading of IGBT pipe Q5 ' and the second voltage signal acquisition end of described Intelligent Power Module 40 of the lower brachium pontis of V phase of described Intelligent Power Module 40, and second end of described second sampling resistor R2 is as the V phase low reference voltage end VN ' of described Intelligent Power Module 40; 3rd sampling resistor R3, the first end of described 3rd sampling resistor R3 is connected to the emitter-base bandgap grading of IGBT pipe Q6 ' and the tertiary voltage signals collecting end of described Intelligent Power Module 40 of the lower brachium pontis of W phase of described Intelligent Power Module 40, and second end of described 3rd sampling resistor R3 is as the W phase low reference voltage end WN ' of described Intelligent Power Module.

According to the Intelligent Power Module 40 of above-described embodiment of the present utility model, following technical characteristic can also be had:

Particularly, as shown in Figure 4, the IGBT pipe Q2 ' of brachium pontis and the IGBT pipe Q3 ' of brachium pontis in described W phase in the IGBT pipe Q1 ' of brachium pontis, described V phase in the described U phase of described Intelligent Power Module 40.

The Intelligent Power Module 40 that the utility model proposes is described in detail below in conjunction with Fig. 1.

As shown in Figure 4, according to the Intelligent Power Module 40 of embodiment of the present utility model, comprising: HVIC pipe 401, and also comprise: a FRD pipe D1 ' to the 6th FRD pipe D6 ' and the first filter capacitor C1 ' is to the 3rd filter capacitor C3 ', wherein, the power end VCC ' of described HVIC pipe 401 to power anode VDD ' (being generally 15V) as the low-pressure area of described Intelligent Power Module 40, the first input end IN1 ' of described HVIC pipe 401, second input IN2 ' and the 3rd input IN3 ' is respectively the U phase input UIN ' of described Intelligent Power Module 40, V phase input VIN ' and W phase input the WIN ' (U of described Intelligent Power Module 40, V, three tunnel inputs of W three-phase receive the input signal of 0V or 5V), the earth terminal GND ' of described HVIC pipe 401 to power negative terminal COM ' as the low-pressure area of described Intelligent Power Module 40, first power supply anode VB1 ' of described HVIC pipe 401 is connected with one end of described first filter capacitor C1 ' and powers anode UVB ' as the U phase higher-pressure region of described Intelligent Power Module 40, first higher-pressure region output HO1 ' of described HVIC pipe 401 is connected with the grid of the IGBT pipe Q1 ' of the upper bridge arm circuit of described U phase, first power supply negative terminal VS1 ' of described HVIC pipe 401 and the emitter-base bandgap grading of the IGBT pipe Q1 ' of the upper bridge arm circuit of described U phase, the anode of a described FRD pipe D1 ', the collector electrode of the IGBT pipe Q4 ' of the lower bridge arm circuit of described U phase, the negative electrode of described 4th FRD pipe D4 ' and the other end of described first filter capacitor C1 ' connect altogether and to power negative terminal UVS ' as the U phase higher-pressure region of described Intelligent Power Module 40, described first filter capacitor C1 ' is connected to the described U phase higher-pressure region anode UVB ' that powers and powers between negative terminal UVS ' with described U phase higher-pressure region, second power supply anode VB2 ' of described HVIC pipe 401 is connected with one end of described second filter capacitor C2 ' and powers anode VVB ' as the V phase higher-pressure region of described Intelligent Power Module 40, second higher-pressure region output HO2 ' of described HVIC pipe 401 is connected with the grid of the IGBT pipe Q2 ' of the upper bridge arm circuit of described V phase, second power supply negative terminal VS2 ' of described HVIC pipe 401 and the emitter-base bandgap grading of the IGBT pipe Q2 ' of the upper bridge arm circuit of described V phase, the anode of described 2nd FRD pipe D2 ', the collector electrode of the IGBT pipe Q5 ' of the lower bridge arm circuit of described V phase, the negative electrode of described 5th FRD pipe D5 ' and the other end of described second filter capacitor C2 ' connect altogether and to power negative terminal VVS ' as the V phase higher-pressure region of described Intelligent Power Module 40, described second filter capacitor C2 ' is connected to the described V phase higher-pressure region anode VVB ' that powers and powers between negative terminal VVS ' with described V phase higher-pressure region, 3rd power supply anode VB3 ' of described HVIC pipe 401 is connected with one end of described 3rd filter capacitor C3 ' and powers anode WVB ' as the W phase higher-pressure region of described Intelligent Power Module 40, the third high nip output HO3 ' of described HVIC pipe 401 and the grid of the IGBT pipe Q3 ' of the upper bridge arm circuit of described W phase, 3rd power supply negative terminal VS3 ' of described HVIC pipe 401 and the emitter-base bandgap grading of the IGBT pipe Q3 ' of the upper bridge arm circuit of described W phase, the anode of described 3rd FRD pipe D3 ', the collector electrode of the IGBT pipe Q6 ' of the lower bridge arm circuit of described W phase, the negative electrode of described 6th FRD pipe D6 ' and the other end of described 3rd filter capacitor C3 ' connect altogether and to power negative terminal WVS ' as the W phase higher-pressure region of described Intelligent Power Module 40, described 3rd filter capacitor C3 ' is connected to the described W phase higher-pressure region anode WVB ' that powers and powers between negative terminal WVS ' with described W phase higher-pressure region, the collector electrode of the IGBT pipe Q1 ' of the upper bridge arm circuit of described U phase and the collector electrode of the IGBT pipe Q3 ' of the collector electrode of the IGBT pipe Q2 ' of the described negative electrode of a FRD pipe D1 ', the upper bridge arm circuit of described V phase, the negative electrode D2 ' of described 2nd FRD pipe, the upper bridge arm circuit of described W phase, the negative electrode of described 3rd FRD pipe D3 ' connect and altogether as the high voltage input P ' (generally meeting 300V) of described Intelligent Power Module 40, first low-pressure area output LO1 ', the second low-pressure area output LO2 ' of described HVIC pipe 401 and the 3rd low-pressure area output LO3 ' are connected with the grid of the grid of IGBT pipe Q5 ' of the grid of the IGBT pipe Q4 ' of the lower bridge arm circuit of described U phase, the lower bridge arm circuit of described V phase and the IGBT pipe Q6 ' of the lower bridge arm circuit of described W phase respectively, and one end that one end of described first sampling resistor R1 is connected to the four-input terminal IN4 ' (the first voltage signal acquisition end) of described HVIC pipe 401, one end of described second sampling resistor R2 is connected to the 5th input IN5 ' of described HVIC pipe 401 (the second voltage signal acquisition end) and described 3rd sampling resistor R3 is connected to the 6th input IN6 ' (tertiary voltage signals collecting end) of described HVIC pipe 401, described HVIC pipe 401 is by described four-input terminal IN4 ', described 5th input IN5 ' and described 6th input IN6 ' monitors described first sampling resistor R1 respectively, the pressure drop at described second sampling resistor R2 and described 3rd sampling resistor R3 two ends, with the signal period of the IGBT pipe Q4 ' of the lower bridge arm circuit of the IGBT pipe Q1 ' and described U phase that adjust brachium pontis in described U phase respectively, the signal period of the IGBT pipe Q5 ' of the IGBT pipe Q2 ' of the upper bridge arm circuit of described V phase and the lower bridge arm circuit of described V phase, the signal period of the IGBT pipe Q6 ' of the IGBT pipe Q3 ' of the upper bridge arm circuit of described W phase and the lower bridge arm circuit of described W phase, make IGBT pipe Q1 ' and IGBT pipe Q4 ', IGBT pipe Q2 ' and IGBT pipe Q5 ', conducting when IGBT pipe Q3 ' and IGBT pipe Q6 ' is all different.

According to an embodiment of the present utility model, in technique scheme, preferably, described HVIC pipe 401 comprises boostrap circuit, described boostrap circuit comprises: the first bootstrap diode D7 ' is to the 3rd bootstrap diode D9 ', and described first bootstrap diode D7 ' is connected to the anode of described 3rd bootstrap diode D9 ' with the described power end VCC ' of described HVIC pipe 401; Negative electrode and described first of the described HVIC pipe 401 of described first bootstrap diode D7 ' the anode VB1 ' that powers is connected; Negative electrode and described second of the described HVIC pipe 401 of described second bootstrap diode D8 ' the anode VB2 ' that powers is connected; The negative electrode of described 3rd bootstrap diode D9 ' and the described 3rd of described HVIC pipe 401 the anode VB3 ' that powers is connected.

According to an embodiment of the present utility model, in technique scheme, preferably, when the described first input end IN1 ' of described HVIC pipe 401 is for high level signal, the described first higher-pressure region output HO1 ' of described HVIC pipe 401, described second higher-pressure region output HO2 ' and described third high nip output HO3 ' is high level and described first low-pressure area output LO1 ', described second low-pressure area output LO2 ' and described 3rd low-pressure area output LO3 ' is low level, then the IGBT pipe Q4 ' of the IGBT pipe Q1 ' conducting of the upper bridge arm circuit of described U phase and the lower bridge arm circuit of described U phase ends, the IGBT pipe Q5 ' of the IGBT pipe Q2 ' conducting of the upper bridge arm circuit of described V phase and the lower bridge arm circuit of described V phase ends and the IGBT pipe Q3 ' conducting of upper bridge arm circuit of described W phase and the IGBT pipe Q6 ' of the lower bridge arm circuit of described W phase end, to make described first sampling resistor R1, the pressure drop that described second sampling resistor R2 and described 3rd sampling resistor R3 produces is controlled, or when the described first input end IN1 ' of described HVIC pipe 401 is for low level signal, the described first higher-pressure region output HO1 ' of described HVIC pipe 401, described second higher-pressure region output HO2 ' and described third high nip output HO3 ' is low level and described first low-pressure area output LO1 ', described second low-pressure area output LO2 ' and described 3rd low-pressure area output LO3 ' is high level, the then IGBT pipe Q4 ' conducting of the IGBT pipe Q1 ' conducting of the upper bridge arm circuit of described U phase and the lower bridge arm circuit of described U phase, the IGBT pipe Q6 ' conducting of the IGBT pipe Q3 ' conducting of the IGBT pipe Q5 ' conducting of the IGBT pipe Q2 ' conducting of the upper bridge arm circuit of described V phase and the lower bridge arm circuit of described V phase and the upper bridge arm circuit of described W phase and the lower bridge arm circuit of described W phase, to make described first sampling resistor R1, the pressure drop that described second sampling resistor R2 and described 3rd sampling resistor R3 produces is controlled.

Operation principle according to the Intelligent Power Module 40 of embodiment of the present utility model is: when the IGBT pipe Q1 ' of the upper bridge arm circuit of the U phase of U phase and the lower bridge arm circuit of U phase IGBT pipe Q4 ' respectively conducting time, flow through the current controlled of the first sampling resistor R1, then the pressure drop of the first sampling resistor R1 generation is controlled; And when the IGBT pipe Q4 ' conducting simultaneously of the IGBT pipe Q1 ' of the upper bridge arm circuit of U phase and the lower bridge arm circuit of U phase, the electric current flowing through the first sampling resistor R1 can become very large instantaneously, then the pressure drop that the first sampling resistor R1 produces also can increase instantaneously; The four-input terminal IN4 ' of HVIC pipe 401 is for monitoring the pressure drop at the first sampling resistor R1 two ends, automatic real-time online adjusts and drives the cycle of the signal of the IGBT pipe Q4 ' of the IGBT pipe Q1 ' of the upper bridge arm circuit of U phase and the lower bridge arm circuit of U phase, make the IGBT pipe Q4 ' conducting no longer simultaneously of the IGBT pipe Q1 ' of the upper bridge arm circuit of U phase and the lower bridge arm circuit of U phase, and then make Intelligent Power Module 40 be operated in safe condition, to extend the useful life of Intelligent Power Module.

Similarly, when the IGBT pipe Q2 ' of the upper bridge arm circuit of V phase and the lower bridge arm circuit of V phase IGBT pipe Q5 ' respectively conducting time, flow through the current controlled of the second sampling resistor R2, then the pressure drop that produces of the second sampling resistor R2 is controlled; And during the IGBT pipe Q5 ' of the IGBT pipe Q2 ' of the upper bridge arm circuit of V phase and the lower bridge arm circuit of V phase conducting simultaneously, the electric current flowing through the second sampling resistor R2 can become very large instantaneously, then the pressure drop that the second sampling resistor R2 produces also can increase instantaneously; 5th input IN5 ' of HVIC pipe is for monitoring the pressure drop at the second sampling resistor R2 two ends, automatic real-time online adjusts and drives the cycle of the signal of the IGBT pipe Q5 ' of the IGBT pipe Q2 ' of the upper bridge arm circuit of V phase and the lower bridge arm circuit of V phase, make the IGBT pipe Q5 ' conducting no longer simultaneously of the IGBT pipe Q2 ' of the upper bridge arm circuit of V phase and the lower bridge arm circuit of V phase, and then make Intelligent Power Module be operated in safe condition, to extend the useful life of Intelligent Power Module;

Similarly, when the IGBT pipe Q3 ' of the upper bridge arm circuit of W phase and the lower bridge arm circuit of W phase IGBT pipe Q6 ' respectively conducting time, flow through the current controlled of the 3rd sampling resistor R3, then the pressure drop that produces of the 3rd sampling resistor R3 is controlled; When the IGBT pipe Q6 ' conducting simultaneously of the IGBT pipe Q3 ' of the upper bridge arm circuit of W phase and the lower bridge arm circuit of W phase, the electric current flowing through the 3rd sampling resistor R3 can become very large instantaneously, then the pressure drop that the 3rd sampling resistor R3 produces also can increase instantaneously; 6th input IN6 ' of HVIC pipe monitors the pressure drop at the 3rd sampling resistor R3 two ends, automatic real-time online adjusts and drives the cycle of the signal of the IGBT pipe Q6 ' of the IGBT pipe Q3 ' of the upper bridge arm circuit of W phase and the lower bridge arm circuit of W phase, make the IGBT pipe Q6 ' conducting no longer simultaneously of the IGBT pipe Q3 ' of the upper bridge arm circuit of W phase and the lower bridge arm circuit of W phase, and then make Intelligent Power Module be operated in safe condition, to extend the useful life of Intelligent Power Module.

Because U, V, W tri-phase adjustment circuits are identical, the utility model with the circuit structure of U phase adjustment circuit for specific embodiment is described further.

As shown in Figure 5, the U phase operating circuit of described Intelligent Power Module 40 comprises: Schmidt trigger U1, the first not gate U2, the second not gate U3, the 3rd not gate U4, the 4th not gate U5, the first delay adjustment circuit, the second delay adjustment circuit, the 5th not gate U6, the 6th not gate U7, the 7th not gate U8, XOR gate U11, first and door U12, second and door U13; Wherein, first delay adjustment circuit is identical with the circuit structure of the second delay adjustment circuit, and described first delay control circuit comprises: the 8th not gate U9, NMOS tube NM1, the second NMOS tube NM2, the first electric capacity C4 ', voltage comparator U10, the first voltage source V 1, rest-set flip-flop RS1.

Particularly, the described first input end IN1 ' of described HVIC pipe 401 is connected with the input of described Schmidt trigger U1, the output of described Schmidt trigger U1 simultaneously with the input of described first not gate U2, the input of described second not gate U3 is connected, the output of described first not gate U2 is connected with the input of described 3rd not gate U4, the described output terminals A of the 3rd not gate U4 and the drain electrode of described NMOS tube NM1, one end of described first electric capacity C4 ' is connected with the input of described 4th not gate U5, the output of described 4th not gate U5 is connected with the input of described 5th not gate U6, the described output C of the 5th not gate U6 and the first input end of described XOR gate U11, described first is connected with the first input end of door U12, the output of described second not gate U3 is connected with the input of described 6th not gate U7, the output of described 6th not gate U7 is connected with the input of described 7th not gate U8, the described output B of the 7th not gate U8 and second input of described XOR gate U11, described second is connected with the first input end of door U13, the output D and described first of described XOR gate U11 and second input of door U12, described second is connected with second input of door U13, described first with the output of door U12 the first output as described U phase adjustment circuit, described second with the output of door U13 the second output as described U phase adjustment circuit, the described four-input terminal IN4 ' of described HVIC pipe 401 is connected with the positive input terminal of described voltage comparator U10, the negative input end of described voltage comparator U10 is connected with the anode of described first voltage source V 1, the negativing ending grounding of described first voltage source V 1, the output of described voltage comparator U10 is held with the S of described rest-set flip-flop RS1 and is connected, the R of described rest-set flip-flop RS1 holds ground connection, the Q end of described rest-set flip-flop RS1 is connected with the input of described 8th not gate U9, the output of described 8th not gate U9 is connected with the grid of described NMOS tube NM1, the substrate of described NMOS tube NM1 and the source electrode of described NMOS tube NM1, the other end of described first electric capacity C4 ' is connected and ground connection, as described in frame as empty in Fig. 5 is depicted as, the circuit structure of the second delay adjustment circuit, according to actual needs, can arrange more delay adjustment circuit, time delay can be changed in the larger context.

If get the Intelligent Power Module 40 of 15A, then key parameter value can be as follows:

First sampling resistor R1 value 10m Ω, the first voltage source V 1 value 0.2V, the second voltage source V 2 value 0.3V, the first electric capacity C4 ' and the second electric capacity C5' value 3pF, so:

When IGBT pipe Q1 ' and IGBT pipe Q4 ' is different during conducting, flow through the electric current <15A of the first sampling resistor R1, the then pressure drop <0.15V of the first sampling resistor R1, this pressure drop is less than the voltage of the first voltage source V 1 and the second voltage source V 2, and the first electric capacity C4 ' and the second electric capacity C5' stays out of;

When there is conducting simultaneously in IGBT pipe Q1 ' and IGBT pipe Q4 ', when flowing through the electric current slightly >20A of the first sampling resistor R1, then the first sampling resistor R1 pressure drop >0.2V and be less than 0.3V, at this moment the first electric capacity C4 ' offering circuit, approximately produces the time delay of 10ns;

When there is conducting simultaneously in IGBT pipe Q1 ' and IGBT pipe Q4 ', when flowing through the electric current slightly >30A of the first sampling resistor R1, the then pressure drop >0.3V of the first sampling resistor R1, at this moment the first electric capacity C4 ' and the second electric capacity C5' offering circuit, approximately produces the time delay of 20ns;

At this, the pressure drop that first sampling resistor R1 produces, the duration that conducting simultaneously occurs with IGBT pipe Q1 ' and IGBT pipe Q4 ' has direct relation, so by regulation time T, can avoid IGBT pipe Q1 ' and IGBT pipe Q4 ' that conducting simultaneously occurs, the involved in the course of the work level signal oscillogram of the U phase operating circuit of Intelligent Power Module 40 as shown in Figure 6.

More than be described with reference to the accompanying drawings the technical solution of the utility model, when the current anomaly of a certain phase of Intelligent Power Module increases, by the current anomaly signal flowing through corresponding sampling resistor being detected in real time, the switching time of the IGBT pipe of timely adjustment place phase, to correct the exception of upper and lower bridge arm conducting simultaneously, Intelligent Power Module is suppressed to continue abnormal heating, because Intelligent Power Module is carried out in real time to the adjustment of upper and lower bridge arm drive singal, when then changing at applied environment or make because of device aging signal transmission time delay change, still self-control can be carried out, safe condition is operated in make Intelligent Power Module, increase the service life.

In the description of this specification, specific features, structure, material or feature that the description of term " embodiment ", " specific embodiment " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present utility model or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.

In the utility model, term " first ", " second " ..., " the tenth " object only for describing, and can not be interpreted as instruction or hint relative importance.For the ordinary skill in the art, the concrete meaning of above-mentioned term in the utility model can be understood as the case may be.

The foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, for a person skilled in the art, the utility model can have various modifications and variations.All within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.

Claims

1. an Intelligent Power Module, is characterized in that, comprising:

First sampling resistor, the first end of described first sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the first voltage signal acquisition end of described Intelligent Power Module of the lower brachium pontis of U phase of described Intelligent Power Module, and the second end of described first sampling resistor is as the U phase low reference voltage end of described Intelligent Power Module;

Second sampling resistor, the first end of described second sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the second voltage signal acquisition end of described Intelligent Power Module of the lower brachium pontis of V phase of described Intelligent Power Module, and the second end of described second sampling resistor is as the V phase low reference voltage end of described Intelligent Power Module;

3rd sampling resistor, the first end of described 3rd sampling resistor is connected to the emitter-base bandgap grading of IGBT pipe and the tertiary voltage signals collecting end of described Intelligent Power Module of the lower brachium pontis of W phase of described Intelligent Power Module, and the second end of described 3rd sampling resistor is as the W phase low reference voltage end of described Intelligent Power Module.

2. Intelligent Power Module according to claim 1, is characterized in that,

When in the U phase of described Intelligent Power Module, the IGBT of brachium pontis manages the IGBT pipe conducting simultaneously of the lower brachium pontis with described U phase, the pressure drop of described first sampling resistor that described first voltage signal acquisition end collects is abnormal; Or

When in the V phase of described Intelligent Power Module, the IGBT of brachium pontis manages the IGBT pipe conducting simultaneously of the lower brachium pontis with described V phase, the pressure drop of described second sampling resistor that described second voltage signal acquisition end collects is abnormal; Or

When in the W phase of described Intelligent Power Module, the IGBT of brachium pontis manages the IGBT pipe conducting simultaneously of the lower brachium pontis with described W phase, the pressure drop of described 3rd sampling resistor that described tertiary voltage signals collecting end collects is abnormal.

3. Intelligent Power Module according to claim 1, is characterized in that, also comprises:

HVIC manages, the power end of described HVIC pipe to be powered anode as the low-pressure area of described Intelligent Power Module, the first input end of described HVIC pipe, second input and the 3rd input are respectively the U phase input of described Intelligent Power Module, V phase input and W phase input, the four-input terminal of described HVIC pipe, 5th input and the 6th input are respectively the described first voltage signal acquisition end of described Intelligent Power Module, described second voltage signal acquisition end, described tertiary voltage signals collecting end, the earth terminal of described HVIC pipe to be powered negative terminal as the low-pressure area of described Intelligent Power Module.

4. Intelligent Power Module according to claim 3, it is characterized in that, also comprise: U phase adjustment circuit, V phase adjustment circuit and W phase adjustment circuit, and described U phase adjustment circuit, described V phase adjustment circuit are identical with the circuit structure of described W phase adjustment circuit.

5. Intelligent Power Module according to claim 4, is characterized in that, described U phase adjustment circuit specifically comprises:

Schmidt trigger, the input of described Schmidt trigger is connected to the described first input end of described HVIC pipe, and the output of described Schmidt trigger is connected to the input of the first not gate and the input of the second not gate;

The output of described first not gate is connected to the input of the 3rd not gate, and the output of described 3rd not gate is connected to the input of the 4th not gate;

First delay adjustment circuit, the first end of described first delay adjustment circuit is connected to the described four-input terminal of described HVIC, second end ground connection of described first delay adjustment circuit, and the three-terminal link of described first delay adjustment circuit is to the output of described 3rd not gate;

Second delay adjustment circuit, the first end of described second delay adjustment circuit is connected to the described four-input terminal of described HVIC, second end ground connection of described second delay adjustment circuit, and the three-terminal link of described first delay adjustment circuit is to the output of described 3rd not gate;

The output of described 4th not gate is connected to the input of the 5th not gate;

The output of described 5th not gate is connected to the first input end and first and the first input end of door of XOR gate;

The output of described second not gate is connected to the input of the 6th not gate, and the output of described 6th not gate is connected to the input of the 7th not gate, and the output of described 7th not gate is connected to second input and second and the first input end of door of described XOR gate;

The output of described XOR gate be connected to described first with the second input of door, described second with the second input of door; And

Described first with the output of door the first output as described U phase adjustment circuit;

Described second with the output of door the second output as described U phase adjustment circuit.

6. Intelligent Power Module according to claim 5, is characterized in that, described first delay adjustment circuit is identical with the circuit structure of described second delay adjustment circuit.

7. Intelligent Power Module according to claim 6, is characterized in that, described first delay adjustment circuit specifically comprises:

Voltage comparator, the positive input terminal of described voltage comparator is as the described first end of described first delay adjustment circuit, and the negative input end of described voltage comparator is connected to the anode of voltage source, and the output of described voltage comparator is connected to the S end of rest-set flip-flop;

The negative terminal of described voltage source is as described second end of described first delay adjustment circuit;

The R of described rest-set flip-flop holds ground connection, and the Q end of described rest-set flip-flop is connected to the input of the 8th not gate;

Output and the grid being connected to NMOS tube of described 8th not gate;

The substrate of described NMOS tube is connected with the source electrode of described NMOS tube, the first end of electric capacity and ground connection;

Second end of described electric capacity is as described 3rd end of described first delay adjustment circuit.

8. Intelligent Power Module according to claim 7, is characterized in that,

The value of described electric capacity is 3pF, and the voltage source of described first delay adjustment circuit is different from the value of the voltage source of described second delay adjustment circuit.

9. Intelligent Power Module according to any one of claim 1 to 8, is characterized in that,

The resistance of described first sampling resistor, described second sampling resistor and described 3rd sampling resistor is 10m Ω.

10. the Intelligent Power Module according to any one of claim 3 to 8, is characterized in that,

The power voltage of anode of the described low-pressure area of described Intelligent Power Module is 15V.