CN105356785B - SPM and air conditioner - Google Patents

Abstract

The invention provides an intelligent power module and an air conditioner. The intelligent power module includes: a three-phase upper bridge arm signal input terminal, a three-phase lower bridge arm signal input terminal, a current detection terminal and a PFC control input terminal; the HVIC tube is provided with The first port corresponding to the current detection end and the second port corresponding to the PFC control input end; the first input end of the adaptive circuit is connected to the first port, the second input end of the adaptive circuit is connected to the second port, and the adaptive circuit The output end of the HVIC tube is used as the enable end of the HVIC tube; wherein, when the input signal of the second input end is on the rising edge, the adaptive circuit outputs the enable signal of the corresponding level according to the result of two detections of the input signal of the first input end ; When the input signal at the second input terminal is not at a rising edge, the adaptive circuit outputs an enabling signal of a corresponding level according to a detection result of the input signal at the first input terminal.

Description

Smart Power Modules and Air Conditioners

technical field

The present invention relates to the technical field of intelligent power modules, in particular to an intelligent power module and an air conditioner.

Background technique

Intelligent Power Module (IPM) is a power driver that integrates power electronic discrete devices and integrated circuit technology. The intelligent power module includes power switching devices and high-voltage drive circuits, and has overvoltage, overcurrent and overheating and other fault detection circuits. The logic input terminal of the intelligent power module receives the control signal of the main controller, and the output terminal drives the compressor or subsequent circuits to work, and at the same time sends the detected system status signal back to the main controller. Compared with traditional discrete solutions, intelligent power modules have the advantages of high integration, high reliability, self-test and protection circuits, etc., and are especially suitable for inverters and various inverter power supplies for driving motors. Ideal power electronic devices for traction, servo drives, and inverter appliances.

A schematic structural diagram of an existing intelligent power module circuit is shown in FIG. 1 , and the MTRIP port is used as a current detection terminal to protect the intelligent power module 100 according to the magnitude of the detected current. The PFCIN port serves as a PFC (Power Factor Correction, power factor correction) control input port of the intelligent power module.

During the working process of the intelligent power module, the PFCINP terminal frequently switches between high and low levels according to a certain frequency, so that the IGBT tube 127 is continuously in the switching state and the FRD tube 131 is in the freewheeling state. The frequency is generally LIN1~LIN3, HIN1~ 2 to 4 times the switching frequency of HIN3, and has no direct connection with the switching frequency of LIN1 ~ LIN3, HIN1 ~ HIN3.

As shown in Figure 2, UN, VN, and WN are connected to one end of the milliohm resistor 138, the other end of the milliohm resistor 138 is connected to GND, and MTRIP is the current detection pin, connected to one end of the milliohm resistor 138, by detecting the milliohm resistor Voltage drop is used to calculate the current, as shown in FIG. 3 . When the current is too large, the smart power module 100 is stopped to avoid permanent damage to the smart power module 100 after overheating due to overcurrent.

-VP, COM, UN, VN, WN have electrical connections in actual use. Therefore, voltage noise during switching of IGBT tubes 121-127 and current noise during freewheeling of FRD tubes 111-FRD 116 and FRD tube 131 will be coupled with each other, affecting input pins in low-voltage regions.

Among the input pins, the thresholds of HIN1~HIN3, LIN1~LIN3, and PFCINP are generally around 2.3V, while the threshold voltage of ITRIP is generally only below 0.5V. Therefore, ITRIP is the pin that is most susceptible to interference. When the ITRIP is triggered, the intelligent power module 100 will stop working, and because no overcurrent actually occurs at this time, the triggering of the ITRIP at this time is a false trigger. As shown in Figure 4, when PFCIN is at a high level and the IGBT tube 127 is turned on at the moment, due to the existence of the reverse recovery current of the FRD tube 131, the current waveform of I ₁₃₁ is superimposed, and the current has a large oscillating noise. - The electrical connection of VP, COM, UN, VN, and WN in the peripheral circuit, the oscillation noise will cause a certain voltage increase at the MTRIP end. Assume that the trigger condition of MTRIP is: voltage>Vth, and duration>Tth; in Figure 4, if Ta<Tth<Tb, then the voltage in the first three cycles is too high enough to cause false triggering of MTRIP, until the second Four cycles, MTRIP will generate a false trigger.

The length of the reverse recovery time of the FRD tube is related to the temperature. The higher the temperature, the longer the reverse recovery time. Therefore, as the system continues to work, the temperature of the intelligent power module 100 continues to rise, and the probability of MTRIP being triggered increases. , in some harsh applications, it will eventually produce false triggers and make the system stop working. Although this false trigger will recover after a period of time without causing damage to the system, it will undoubtedly cause confusion for users. For example, in the application of inverter air conditioners, the higher the ambient temperature is, the more the user needs the continuous operation of the air conditioning system, but the high ambient temperature will increase the reverse recovery time of the FRD tube, and the probability of MTRIP being falsely triggered will increase. When MTRIP is triggered by mistake, the air conditioning system will stop working for 3 to 5 minutes due to the mistaken belief that overcurrent has occurred, so that users cannot obtain cold air during this period. This is one of the main reasons why the air conditioning system receives complaints from customers due to insufficient cooling capacity. .

Therefore, how to effectively reduce the probability of false triggering of the smart power module on the premise of ensuring high reliability and high adaptability of the smart power module has become a technical problem to be solved urgently.

Contents of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

Therefore, an object of the present invention is to propose a new intelligent power module, which can effectively reduce the probability of false triggering of the intelligent power module on the premise of ensuring high reliability and high adaptability of the intelligent power module.

Another object of the present invention is to provide an air conditioner.

In order to achieve the above object, according to the embodiment of the first aspect of the present invention, an intelligent power module is proposed, including: a three-phase upper bridge arm signal input terminal, a three-phase lower bridge arm signal input terminal, a three-phase low voltage reference terminal , the current detection terminal and the PFC control input terminal; the HVIC tube, the HVIC tube is provided with terminals respectively connected to the signal input terminal of the three-phase upper bridge arm and the signal input terminal of the three-phase lower bridge arm, and corresponding to The first port of the current detection terminal and the second port corresponding to the PFC control input terminal, the first port is connected to the current detection terminal through a connection line, and the second port is connected to the PFC control terminal through a connection line The input terminals are connected; the sampling resistor, the three-phase low voltage reference terminal and the current detection terminal are connected to the first terminal of the sampling resistor, and the second terminal of the sampling resistor is connected to the low voltage of the intelligent power module District power supply negative terminal; self-adaptive circuit, the positive pole and negative pole of the power supply of the adaptive circuit are respectively connected to the positive terminal and negative terminal of the low-voltage district power supply of the intelligent power module, the first input terminal of the self-adaptive circuit Connected to the first port, the second input terminal of the adaptive circuit is connected to the second port, and the output terminal of the adaptive circuit is used as the enabling terminal of the HVIC tube;

Wherein, when the input signal of the second input terminal is at a rising edge, the adaptive circuit outputs an enable signal of a corresponding level according to the results of two detections of the input signal of the first input terminal; When the input signal at the second input terminal is not at a rising edge, the circuit outputs an enable signal of a corresponding level according to a detection result of the input signal at the first input terminal.

According to the intelligent power module of the embodiment of the present invention, since the second port (ie PFCINP) is at a high level moment, if the voltage fluctuation of the first port (ITRIP) is caused by circuit noise, then the ITRIP voltage is a continuously reduced Therefore, by setting the adaptive circuit, when the input signal of the second input terminal (ie, the PFC control input terminal) is on the rising edge, according to the result of two detections of the input signal of the first input terminal (current detection terminal) Output the enable signal of the corresponding level, so that at the moment when PFCINP is high, the possibility of malfunction caused by circuit noise can be filtered out through secondary detection; and if the voltage fluctuation of ITRIP comes from a real overcurrent, then the voltage of ITRIP is It is a process of continuous increase, and timely output of low level after the second detection confirmation can ensure that the intelligent power module stops working and forms protection.

When the input signal at the second input terminal is not at a rising edge, an enable signal of a corresponding level is output according to the result of a detection of the input signal at the first input terminal, so that after the PFCINP high level passes, the intelligent power module can perform normal operation. Detection and judgment, so as to provide timely protection for the intelligent power module when the current signal detected by the current detection terminal is too large.

The intelligent power module according to the above-mentioned embodiments of the present invention may also have the following technical features:

According to an embodiment of the present invention, when the input signal of the second input terminal is on the rising edge of the adaptive circuit, when the results of two detections of the input signal of the first input terminal are all voltage values higher than the predetermined value, output the enabling signal of the first level to prohibit the operation of the HVIC tube; otherwise, output the enabling signal of the second level to allow the operation of the HVIC tube;

When the input signal at the second input terminal is not at a rising edge, the adaptive circuit outputs the first voltage when the result of a detection of the input signal at the first input terminal is that the voltage value is higher than a predetermined value. a level enable signal; otherwise, output an enable signal of the second level.

Wherein, the enable signal of the first level may be a low level signal, and the enable signal of the second level may be a high level signal.

According to an embodiment of the present invention, the adaptive circuit includes:

The first voltage comparator, the positive input terminal of the first voltage comparator is used as the first input terminal of the adaptive circuit, the negative input terminal of the first voltage comparator is connected to the positive pole of the voltage source, and the voltage The negative pole of the source is used as the negative pole of the power supply of the adaptive circuit, and the output terminal of the first voltage comparator is connected to the first selection terminal of the analog switch;

A first NOT gate and a second NOT gate connected in series, the input terminal of the first NOT gate is used as the second input terminal of the adaptive circuit, and the output terminal of the second NOT gate is connected to the first NAND gate the first input terminal of

The third NOT gate, the fourth NOT gate and the fifth NOT gate connected in series, the input terminal of the third NOT gate is connected to the input terminal of the first NOT gate, and the output terminal of the fifth NOT gate is connected to The second input terminal of the first NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the sixth NOT gate, and the output terminal of the sixth NOT gate is connected to the control of the analog switch end;

The first capacitor is connected between the input terminal of the fourth NOT gate and the negative pole of the power supply of the adaptive circuit;

The second capacitor is connected between the input terminal of the fifth NOT gate and the negative pole of the power supply of the adaptive circuit;

The seventh NOT gate and the eighth NOT gate connected in series, the input end of the seventh NOT gate is connected to the input end of the first NOT gate, and the output end of the eighth NOT gate is connected to the second NAND gate the first input terminal of

The ninth NOT gate, the tenth NOT gate and the eleventh NOT gate connected in series, the input end of the ninth NOT gate is connected to the input end of the first NOT gate, and the output end of the eleventh NOT gate connected to the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the input end of the twelfth NOT gate;

The third capacitor is connected between the input terminal of the eleventh NOT gate and the negative pole of the power supply of the adaptive circuit;

RS flip-flop, the R end of the RS flip-flop is connected to the output end of the twelfth NOT gate;

An AD converter and a DA converter connected in series, the input terminal of the AD converter is connected to the positive input terminal of the first voltage comparator and the positive input terminal of the second voltage comparator, and the output terminal of the DA converter connected to the negative input terminal of the second voltage comparator, and the output terminal of the second voltage comparator is connected to the S terminal of the RS flip-flop;

The third NAND gate, the output terminal of the sixth NAND gate, the output terminal of the first voltage comparator and the Q terminal of the RS flip-flop are respectively connected to the three input terminals of the third NAND gate , the output end of the third NAND gate is connected to the input end of the thirteenth NOT gate, the output end of the thirteenth NOT gate is connected to the second selection end of the analog switch, and the fixed analog switch The terminal is connected to the input terminal of the fourteenth NOT gate, and the output terminal of the fourteenth NOT gate is used as the output terminal of the adaptive circuit.

According to an embodiment of the present invention, the HVIC tube is also provided with a signal output terminal of the PFC drive circuit, and the intelligent power module further includes: a first power switch tube and a first diode, and the first diode The anode of the tube is connected to the emitter of the first power switch tube, the cathode of the first diode is connected to the collector of the first power switch tube, and the collector of the first power switch tube is connected to The anode of the second diode, the cathode of the second diode is connected to the high voltage input terminal of the intelligent power module, and the base of the first power switch tube is connected to the signal output of the PFC drive circuit terminal, the emitter of the first power switch tube serves as the PFC low voltage reference terminal of the intelligent power module, and the collector of the first power switch tube serves as the PFC terminal of the intelligent power module.

Wherein, the first power switch tube may be an IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor).

According to an embodiment of the present invention, it further includes: a bootstrap circuit, the bootstrap circuit includes: a first bootstrap diode, and the anode of the first bootstrap diode is connected to the positive electrode of the power supply in the low-voltage area of the intelligent power module. terminal, the cathode of the first bootstrap diode is connected to the positive terminal of the U-phase high-voltage area power supply of the intelligent power module; the second bootstrap diode, the anode of the second bootstrap diode is connected to the intelligent power module The positive end of the power supply in the low-voltage area of the second bootstrap diode, the cathode of the second bootstrap diode is connected to the positive end of the V-phase high-voltage area power supply of the intelligent power module; the third bootstrap diode, the anode of the third bootstrap diode is connected to To the positive terminal of the power supply in the low-voltage area of the intelligent power module, and the cathode of the third bootstrap diode is connected to the positive terminal of the power supply in the high-voltage area of the W-phase of the intelligent power module.

According to an embodiment of the present invention, it also includes: a three-phase upper bridge arm circuit, the input end of each phase of the upper bridge arm circuit in the three-phase upper bridge arm circuit is connected to the three-phase high voltage region of the HVIC tube The signal output end of the corresponding phase; the three-phase lower bridge arm circuit, the input end of each phase lower bridge arm circuit in the three-phase lower bridge arm circuit is connected to the signal of the corresponding phase in the three-phase low voltage area of the HVIC tube output.

Among them, the three-phase upper bridge arm circuit includes: U-phase upper bridge arm circuit, V-phase upper bridge arm circuit, W-phase upper bridge arm circuit; the three-phase lower bridge arm circuit includes: U-phase lower bridge arm circuit, V-phase lower bridge arm circuit Arm circuit, W-phase lower bridge arm circuit.

According to an embodiment of the present invention, the upper bridge arm circuit of each phase includes: a second power switch tube and a third diode, the anode of the third diode is connected to the second power switch tube emitter, the cathode of the third diode is connected to the collector of the second power switch tube, the collector of the second power switch tube is connected to the high voltage input terminal of the intelligent power module, the The base of the second power switch tube is used as the input terminal of the upper bridge arm circuit of each phase, and the emitter of the second power switch tube is connected to the negative terminal of the high voltage power supply of the corresponding phase of the intelligent power module. Wherein, the second power switch tube may be an IGBT.

According to an embodiment of the present invention, the lower bridge arm circuit of each phase includes: a third power switch tube and a fourth diode, the anode of the fourth diode is connected to the third power switch tube The emitter, the cathode of the fourth diode is connected to the collector of the third power switch tube, and the collector of the third power switch tube is connected to the third and second diodes in the corresponding upper bridge arm circuit. The anode of the third power switch tube, the base of the third power switch tube is used as the input terminal of the lower bridge arm circuit of each phase, and the emitter of the third power switch tube is used as the low terminal of the corresponding phase of the intelligent power module. Voltage reference terminal. Wherein, the third power switch tube may be an IGBT.

According to an embodiment of the present invention, the voltage of the high voltage input terminal of the intelligent power module is 300V.

According to an embodiment of the present invention, a filter capacitor is connected between the positive terminal and the negative terminal of the power supply in the high-voltage area of each phase of the intelligent power module.

According to an embodiment of the second aspect of the present invention, an air conditioner is also provided, including: the intelligent power module as described in any one of the above embodiments.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

FIG. 1 shows a schematic structural diagram of an intelligent power module in the related art;

FIG. 2 shows a schematic diagram of an external circuit of an intelligent power module;

Fig. 3 shows a schematic diagram of a waveform in which a current signal triggers an intelligent power module to stop working;

FIG. 4 shows a schematic diagram of a waveform of noise generated by an intelligent power module in the related art;

Fig. 5 shows a schematic structural diagram of an intelligent power module according to an embodiment of the present invention;

FIG. 6 shows a schematic diagram of the internal structure of an adaptive circuit according to an embodiment of the present invention.

detailed description

In order to understand the above-mentioned purpose, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described here. Therefore, the protection scope of the present invention is not limited by the specific details disclosed below. EXAMPLE LIMITATIONS.

Fig. 5 shows a schematic structural diagram of an intelligent power module according to an embodiment of the present invention.

As shown in FIG. 5 , the intelligent power module according to the embodiment of the present invention includes: an HVIC tube 1101 and an adaptive circuit 1105 .

The VCC terminal of the HVIC tube 1101 serves as the positive terminal VDD of the power supply in the low-voltage area of the intelligent power module 1100, and VDD is generally 15V;

Inside the HVIC tube 1101:

The ITRIP end is connected to the first input end of the adaptive circuit 1105; the PININP end is connected to the second input end of the adaptive circuit 1105; the VCC end is connected to the positive end of the power supply of the adaptive circuit 1105; the GND end is connected to the negative end of the power supply of the adaptive circuit 1105 end; the output end of the adaptive circuit 1105 is denoted as ICON, and is used to control the validity of the HIN1-HIN3, LIN1-LIN3, and PFCINP signals.

There is also a bootstrap circuit structure inside the HVIC tube 1101 as follows:

The VCC terminal is connected to the anode of the bootstrap diode 1102, the bootstrap diode 1103, and the bootstrap diode 1104; the cathode of the bootstrap diode 1102 is connected to the VB1 of the HVIC tube 1101; the cathode of the bootstrap diode 1103 is connected to the VB2 of the HVIC tube 1101; The cathode of the lifting diode 1104 is connected to the VB3 of the HVIC tube 1101 .

The HIN1 terminal of the HVIC tube 1101 is the U-phase upper bridge arm signal input terminal UHIN of the intelligent power module 1100; the HIN2 terminal of the HVIC tube 1101 is the V-phase upper bridge arm signal input terminal VHIN of the intelligent power module 1100; the HIN3 terminal of the HVIC tube 1101 is the signal input terminal WHIN of the W-phase upper bridge arm of the intelligent power module 1100; the LIN1 terminal of the HVIC tube 1101 is the signal input terminal ULIN of the U-phase lower bridge arm of the intelligent power module 1100; The V-phase lower bridge arm signal input terminal VLIN; the LIN3 end of the HVIC tube 1101 is the W-phase lower bridge arm signal input terminal WLIN of the intelligent power module 1100; the ITRIP end of the HVIC tube 1101 is the MTRIP end of the intelligent power module 1100; the HVIC tube 1101 The PFCINP terminal of the intelligent power module 1100 is used as the PFC control input terminal PFCIN of the intelligent power module 100; Among them, the six inputs UHIN, VHIN, WHIN, ULIN, VLIN, WLIN of the intelligent power module 1100 and the PFCIN terminal receive an input signal of 0V or 5V.

The VB1 end of the HVIC tube 1101 is connected to one end of the capacitor 1141, and serves as the positive terminal UVB of the power supply in the U-phase high-voltage area of the intelligent power module 1100; the HO1 end of the HVIC tube 1101 is connected to the gate of the U-phase upper bridge arm IGBT tube 1121; the HVIC The VS1 end of the tube 1101 is connected to the emitter of the IGBT tube 1121, the anode of the FRD tube 1111, the collector of the U-phase lower bridge arm IGBT tube 1124, the cathode of the FRD tube 1114, and the other end of the capacitor 1141, and serves as an intelligent power module 1100 The negative terminal UVS of the power supply in the U-phase high-voltage area.

The VB2 end of the HVIC tube 1101 is connected to one end of the capacitor 1132, and serves as the positive terminal VVB of the power supply in the V-phase high-voltage area of the intelligent power module 1100; the HO2 end of the HVIC tube 1101 is connected to the gate of the V-phase upper arm IGBT tube 1123; the HVIC The VS2 end of the tube 1101 is connected to the emitter of the IGBT tube 1122, the anode of the FRD tube 1112, the collector of the V-phase lower bridge arm IGBT tube 1125, the cathode of the FRD tube 1115, and the other end of the capacitor 1132, and serves as an intelligent power module 1100 The negative terminal VVS of the power supply in the V-phase high-voltage area.

The VB3 end of the HVIC tube 1101 is connected to one end of the capacitor 1133, which serves as the positive terminal WVB of the power supply in the W-phase high-voltage area of the intelligent power module 1100; the HO3 end of the HVIC tube 1101 is connected to the gate of the W-phase upper arm IGBT tube 1123; the HVIC tube The VS3 terminal of 1101 is connected to the emitter of IGBT tube 1123, the anode of FRD tube 1113, the collector of W-phase lower bridge arm IGBT tube 1126, the cathode of FRD tube 1116, and the other end of capacitor 1133, and serves as the terminal of intelligent power module 1100 The negative terminal WVS of the power supply in the W-phase high-voltage area.

The LO1 end of the HVIC tube 1101 is connected to the grid of the IGBT tube 1124; the LO2 end of the HVIC tube 1101 is connected to the grid of the IGBT tube 1125; the LO3 end of the HVIC tube 1101 is connected to the grid of the IGBT tube 1126; the emitter of the IGBT tube 1124 The pole is connected to the anode of the FRD tube 1114 and used as the U-phase low voltage reference terminal UN of the intelligent power module 1100; the emitter of the IGBT tube 1125 is connected to the anode of the FRD tube 1115 and used as the V-phase low voltage reference of the intelligent power module 1100 terminal VN; the emitter of the IGBT tube 1126 is connected to the anode of the FRD tube 1116 , and serves as the W-phase low voltage reference terminal WN of the intelligent power module 1100 .

VDD is the positive terminal of the power supply of the HVIC tube 1101, GND is the negative terminal of the power supply of the HVIC tube 1101; VDD-GND voltage is generally 15V; VB1 and VS1 are the positive and negative poles of the power supply in the U-phase high voltage area, and HO1 is the U-phase high voltage VB2 and VS2 are the positive pole and negative pole of the power supply in the V-phase high-voltage zone, HO2 is the output terminal of the V-phase high-voltage zone; VB3 and VS3 are the positive pole and negative pole of the power supply in the U-phase high-voltage zone, and HO3 is W LO1, LO2, and LO3 are the output terminals of U-phase, V-phase, and W-phase low-voltage areas respectively.

The PFCO end of the HVIC tube 1101 is connected to the gate of the IGBT tube 1127; the emitter of the IGBT tube 1127 is connected to the anode of the FRD tube 1117, and serves as the PFC low voltage reference terminal-VP of the intelligent power module 1100; the collector of the IGBT tube 1127 It is connected with the cathode of FRD tube 1117 and the anode of FRD tube 1131, and serves as the PFC terminal of the intelligent power module 1100;

The collector of IGBT tube 1121, the cathode of FRD tube 1111, the collector of IGBT tube 1122, the cathode of FRD tube 1112, the collector of IGBT tube 1123, the cathode of FRD tube 1113, and the cathode of FRD tube 1131 are connected, and serve as smart power The high voltage input terminals P and P of the module 1100 are generally connected to 300V.

The function of HVIC tube 1101 is:

When ICON is high level, the logic input signals of 0 or 5V at the input terminals HIN1, HIN2, and HIN3 are respectively transmitted to the output terminals HO1, HO2, and HO3, and the signals of LIN1, LIN2, and LIN3 are respectively transmitted to the output terminals LO1 and LO2 , LO3, transmit the PFCINP signal to the output terminal PFCO, where HO1 is the logic output signal of VS1 or VS1+15V, HO2 is the logic output signal of VS2 or VS2+15V, HO3 is the logic output signal of VS3 or VS3+15V, LO1, LO2, LO3, PFCO are logic output signals of 0 or 15V;

When ICON is at low level, HO1, HO2, HO3, LO1, LO2, LO3, and PFCO are all set at low level.

The effect of adaptive circuit 1105 is:

On the rising edge of the PFCINP of the HVIC tube 1101, the adaptive circuit 1105 detects the signal of ITRIP twice, the voltage detected for the first time is higher than a certain value, and the voltage of ITRIP detected for the second time is higher than the first Once, ICON outputs a low level; when the first detected voltage is lower than a certain value, or although the first detected voltage is higher than a certain value but the second detected ITRIP voltage is low At the first time, ICON keeps enabling the output, that is, outputs high level;

After the rising edge of PFCINP of the HVIC tube 1101 passes, the first input terminal of the adaptive circuit 1105 detects the voltage of ITRIP in real time, and the ICON outputs a high level or a low level according to the voltage of ITRIP.

In one embodiment of the present invention, a schematic diagram of a specific circuit structure of the adaptive circuit 1105 is shown in FIG. 6 , specifically:

PFCINP is connected to the input terminals of the NOT gate 2001, the NOT gate 2003, the NOT gate 2011, and the NOT gate 2013; the output terminal of the NOT gate 2001 is connected to the input terminal of the NOT gate 2002; The input end of the inverter; the output end of the NOT gate 2004 is connected to one end of the capacitor 2009 and the input end of the NOT gate 2005; the other end of the capacitor 2008 is connected to GND; the other end of the capacitor 2009 is connected to GND;

The output terminal of the NOT gate 2002 is connected to one of the input terminals of the NAND gate 2006; the output terminal of the NOT gate 2005 is connected to the other input terminal of the NAND gate 2006; the output terminal of the NAND gate 2006 is connected to the input terminal of the NOT gate 2007; The output terminal of the NOT gate 2007 is connected to one of the input terminals of the NAND gate 2025 and the control terminal of the analog switch 2027;

The output of the NOT gate 2011 is connected to the input of the NOT gate 2012; the output of the NOT gate 2013 is connected to the input of the NOT gate 2014; the output of the NOT gate 2014 is connected to one end of the capacitor 2019 and the input of the NOT gate 2015; The other terminal is connected to GND; the output terminal of the NOT gate 2012 is connected to one of the input terminals of the NAND gate 2016; the output terminal of the NOT gate 2015 is connected to the other input terminal of the NAND gate 2016; the output terminal of the NAND gate 2016 is connected to the NAND gate 2017 connected to the input terminals; the output terminal of the NOT gate 2017 is connected to the R terminal of the RS flip-flop 2024;

The ITRIP end is connected with the positive input terminal of the voltage comparator 2010, the positive input terminal of the voltage comparator 2023, and the input terminal of the AD converter 2021; the positive terminal of the voltage source 2018 is connected with the negative input terminal of the voltage comparator 2010; the voltage source 2018 The negative terminal of the voltage comparator 2010 is connected to GND; the output terminal of the voltage comparator 2010 is connected to one of the input terminals of the NAND gate 2025 and the 0 selection terminal of the analog switch 2027; the output terminal of the AD converter 2021 is connected to the input terminal of the DA converter 2022; The output terminal of the DA converter 2022 is connected with the negative input terminal of the voltage comparator 2023; the output terminal of the voltage comparator 2023 is connected with the S terminal of the RS flip-flop 2024; connected to the input;

The output end of the NAND gate 2025 is connected to the input end of the NOT gate 2026; the output end of the NOT gate 2026 is connected to the 1 selection end of the analog switch 2027; the fixed terminal of the analog switch 2027 is connected to the input end of the NOT gate 2020; the output end of the NOT gate 2020 Connect to ICON.

The working principle and key parameter values of the above-mentioned embodiments are described below:

Because of the delay effect of capacitor 2019, on the rising edge of the PFCINP signal, point A generates a narrow pulse; because of the delay effect of capacitor 2008 and capacitor 2009, on the rising edge of the PFCINP signal, point B generates a pulse narrower than point A pulses with larger pulses;

During the B point pulse, the 1 selection terminal of the analog switch 2027 is connected with the fixed terminal of the analog switch 2027; otherwise, the 0 selection terminal of the analog switch 2027 is connected with the fixed terminal of the analog switch 2027;

When the 0 selection terminal of the analog switch 2027 is connected to the fixed terminal of the analog switch 2027: the ITRIP signal is compared with the voltage V1 of the voltage source 2018, and when the ITRIP voltage is higher than V1, the ICON outputs a low level, otherwise the ICON outputs a high level;

When the 1 selection terminal of the analog switch 2027 is connected to the fixed terminal of the analog switch 2027: after the R terminal of the RS flip-flop 2024 is reset by the high level of the A terminal, the NAND gate 2025 outputs a high level, and passes through the NOT gate 2026 and the NOT gate After 2020, ICON initially outputs a high level;

The ITIRP voltage is compared with the voltage V1 of the voltage comparator 2018:

When the ITRIP voltage is lower than the V1 voltage, the NAND gate 2025 outputs a high level, and after passing through the NOT gate 2026 and the NOT gate 2020, the ICON continues to output a high level unchanged;

When the ITRIP voltage is greater than the V1 voltage, the instantaneous voltage of ITRIP passes through the AD converter 2021 and the DA converter 2022, and is used as the comparison voltage V2 of the negative terminal of the voltage comparator 2023, and the duration of the conversion is recorded as T. After ITRIP passes through the T time The voltage V3 is compared with the voltage V2:

When V3 is less than V2, it indicates that the voltage overshoot of ITRIP is decreasing, which may be noise, and the voltage comparator 2023 outputs a low level, then the low level of the Q terminal of the RS flip-flop 2024 remains unchanged, and the NAND gate 2025 outputs a high level Level, after the NOT gate 2026 and the NOT gate 2020, ICON continues to output high level unchanged;

When V3 is greater than V2, it indicates that the voltage overshoot of ITRIP continues to increase, and there is a great chance of overcurrent, the voltage comparator 2023 outputs a high level, and the Q terminal of the RS flip-flop 2024 is set as a high level, then The three input terminals of the NAND gate 2025 are all at high level, and the output terminal of the NAND gate 2025 is at low level. After passing through the NOT gate 2026 and the NOT gate 2020 , the ICON outputs a low level.

The minimum size allowed by the process can be selected for the NOT gate 2013 and the NOT gate 2014. The value of the NOT gate 2011 is the same as that of the NOT gate 2013, the value of the NOT gate 2012 is the same as that of the NOT gate 2014, and the value of the capacitor 2019 can be 3-5pF. Then the width of the narrow pulse at point A is about 100ns, which is enough to reset the RS flip-flop 2024;

Inverter 2003 and invertor 2004 can choose the minimum size allowed by the process. The value of invertor 2001 is the same as that of invertor 2003, the value of invertor 2002 is the same as that of invertor 2004, the value of capacitor 2009 is the same as that of capacitor 2019, and the value of capacitor 2009 is the same as that of capacitor 2019. The value of 2008 can be 15 ~ 25pF, then the pulse width of point B is 350ns ~ 550ns, this time is the time for the second confirmation of whether the voltage of ITRIP is noise, if this time is too short, the ITIRP voltage The probability of misjudgment is relatively high. If this time is too long, the timeliness of the ITIRP voltage response will be too slow;

The voltage of the voltage source 2018 can be set to 0.5V or 0.7V, depending on the value of the external milliohm resistor connected to ITRIP, or the value of the external milliohm resistor can be adapted to the voltage value of the voltage source 2018 , generally, the voltage of the voltage source 2018 should not be too low, otherwise the probability of false triggering is very high, and it should not be too high, otherwise the resistance value of the external resistor will be very large, resulting in a high power requirement for the external milliohm resistor. increase system cost;

The total delay of AD converter 2021 and DA converter 2022 is designed to be 200-300ns, this time is T, then the voltage of V3 is the voltage at the time point of 200-300ns after the voltage of V2, and it is judged that the voltage of ITRIP is still after 200-300ns. If it is greater than V1 and continues to increase, the abnormal increase in ITRIP voltage is not likely to be caused by the reverse recovery time of the FRD tube 1131 controlled by PFCINP. On the contrary, if it is judged that the ITRIP voltage is still greater than V1 after 200-300ns but continues to decrease Or the ITRIP voltage is less than V1 after 200-300ns, then the abnormal increase of the ITRIP voltage is likely to be caused by the reverse recovery time of the FRD tube 1131 controlled by PFCINP.

It can be seen from the technical solutions of the above embodiments that the intelligent power module proposed by the present invention is completely compatible with the existing intelligent power module, and can be directly replaced with the existing intelligent power module. At the moment of PFCINP high level, if the voltage fluctuation of ITRIP is caused by circuit noise, then the voltage of ITRIP is a process of continuous decrease, and the possibility of malfunction caused by circuit noise can be filtered out through secondary detection; if the voltage fluctuation of ITRIP is If it comes from real overcurrent, then the ITRIP voltage is a process of continuous increase. After the second detection is confirmed, it outputs a low level in time to make the intelligent power module of the present invention stop working to form a protection. After the PFCINP high level passes, the intelligent power module system of the present invention enters the ITRIP routine judgment and detection state, the noise suppression function is canceled, and it can respond to the voltage change of the pin in time to provide timely protection for the intelligent power module.

The technical solution of the present invention has been described in detail above in conjunction with the accompanying drawings. The present invention proposes a new intelligent power module, which can effectively reduce the error of the intelligent power module on the premise of ensuring that the intelligent power module has high reliability and high adaptability. chance of triggering.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A kind of 1. SPM, it is characterised in that including：

   Bridge arm signal input part under bridge arm signal input part, three-phase on three-phase, three-phase low reference voltage end, current detecting end and PFC control signals；

   HVIC is managed, and is provided with the HVIC pipes and is respectively connecting on the three-phase bridge under bridge arm signal input part and the three-phase The terminals of arm signal input part, and it is corresponding to the first port at the current detecting end and defeated corresponding to PFC controls Enter the second port at end, the first port is connected by connecting line with the current detecting end, and the second port passes through company Wiring is connected with the PFC control signals；

   Sampling resistor, the three-phase low reference voltage end and the current detecting end are connected to the first of the sampling resistor End, the second end of the sampling resistor is connected to the low-pressure area power supply negative terminal of the SPM；

   Adaptive circuit, the power supply positive pole and negative pole of the adaptive circuit are respectively connecting to the SPM Low-pressure area power supply anode and negative terminal, the first input end of the adaptive circuit are connected to the first port, it is described from Second input of adaptive circuit is connected to the second port, and the output end of the adaptive circuit is as the HVIC pipes Enable Pin；

   Wherein, the adaptive circuit is when the input signal of second input is in rising edge, according to described first The result that the input signal of input is detected twice exports the enable signal of corresponding level；The adaptive circuit is described When the input signal of second input is not in rising edge, one-time detection is carried out according to the input signal to the first input end Result export the enable signal of corresponding level.
2. 2. SPM according to claim 1, it is characterised in that：

   The adaptive circuit is when the input signal of second input is in rising edge, when to the first input end Input signal is detected twice, and the magnitude of voltage detected for the first time is higher than predetermined value, and the magnitude of voltage detected for the second time During higher than first time, the enable signal of the first level is exported, to forbid the HVIC pipes to work；Otherwise, second electrical level is exported Enable signal, to allow the HVIC pipes to work；

   The adaptive circuit is when the input signal of second input is not in rising edge, when to the first input end Input signal when carrying out the result of one-time detection and be higher than predetermined value for magnitude of voltage, the enable signal of output first level； Otherwise, the enable signal of the second electrical level is exported.
3. 3. SPM according to claim 1, it is characterised in that the adaptive circuit includes：

   First voltage comparator, the positive input terminal of the first voltage comparator input as the first of the adaptive circuit End, the negative input end of the first voltage comparator are connected to the positive pole of voltage source, and the negative pole conduct of the voltage source is described certainly The power supply negative pole of adaptive circuit, the output end of the first voltage comparator are connected to the first choice end of analog switch；

   The first NOT gate and the second NOT gate being connected in series, the input of first NOT gate as the adaptive circuit second Input, the output end of second NOT gate are connected to the first input end of the first NAND gate；

   The 3rd NOT gate, the 4th NOT gate and the 5th NOT gate being connected in series, the input of the 3rd NOT gate are connected to described first The input of NOT gate, the output end of the 5th NOT gate are connected to the second input of first NAND gate, described first with The output end of NOT gate is connected to the input of the 6th NOT gate, and the output end of the 6th NOT gate is connected to the control of the analog switch End processed；

   First electric capacity, it is connected between the input of the 4th NOT gate and the power supply negative pole of the adaptive circuit；

   Second electric capacity, it is connected between the input of the 5th NOT gate and the power supply negative pole of the adaptive circuit；

   The 7th NOT gate being connected in series and the 8th NOT gate, the input of the 7th NOT gate are connected to the input of first NOT gate End, the output end of the 8th NOT gate are connected to the first input end of the second NAND gate；

   The 9th NOT gate, the tenth NOT gate and the 11st NOT gate being connected in series, the input of the 9th NOT gate are connected to described The input of one NOT gate, the output end of the 11st NOT gate are connected to the second input of second NAND gate, and described The output end of two NAND gates is connected to the input of the 12nd NOT gate；

   3rd electric capacity, it is connected between the input of the 11st NOT gate and the power supply negative pole of the adaptive circuit；

   Rest-set flip-flop, the R ends of the rest-set flip-flop are connected to the output end of the 12nd NOT gate；

   The a/d converter and D/A converter being connected in series, the input of the a/d converter are connected to the first voltage comparator The positive input terminal of positive input terminal and second voltage comparator, the output end of the D/A converter are connected to the second voltage and compared The negative input end of device, the output end of the second voltage comparator are connected to the S ends of the rest-set flip-flop；

   3rd NAND gate, the output end of the 6th NOT gate, the output end of the first voltage comparator and the rest-set flip-flop Q ends be respectively connecting to three inputs of the 3rd NAND gate, the output end of the 3rd NAND gate is connected to the 13rd The input of NOT gate, the output end of the 13rd NOT gate are connected to the second selection end of the analog switch, and the simulation is opened The fixing end of pass is connected to the input of the 14th NOT gate, and the output end of the 14th NOT gate is as the adaptive circuit Output end.
4. 4. SPM according to claim 1, it is characterised in that PFC drivings are additionally provided with the HVIC pipes The signal output part of circuit, the SPM also include：

   First power switch pipe and the first diode, the anode of first diode are connected to first power switch pipe Emitter stage, the negative electrode of first diode are connected to the colelctor electrode of first power switch pipe, first power switch The colelctor electrode of pipe is connected to the anode of the second diode, and the negative electrode of second diode is connected to the SPM High voltage input, the base stage of first power switch pipe are connected to the signal output part of the PFC drive circuits, and described PFC low reference voltage end of the emitter stage of one power switch pipe as the SPM, first power switch pipe PFC end of the colelctor electrode as the SPM.
5. 5. SPM according to any one of claim 1 to 4, it is characterised in that also include：Boostrap circuit, The boostrap circuit includes：

   First bootstrap diode, the anode of first bootstrap diode are connected to the low-pressure area power supply of the SPM Power positive end, the negative electrode of first bootstrap diode are being connected to the U phases higher-pressure region power supply of the SPM just End；

   Second bootstrap diode, the anode of second bootstrap diode are connected to the low-pressure area power supply of the SPM Power positive end, the negative electrode of second bootstrap diode are being connected to the V phases higher-pressure region power supply of the SPM just End；

   3rd bootstrap diode, the anode of the 3rd bootstrap diode are connected to the low-pressure area power supply of the SPM Power positive end, the negative electrode of the 3rd bootstrap diode are being connected to the W phases higher-pressure region power supply of the SPM just End.
6. 6. SPM according to any one of claim 1 to 4, it is characterised in that also include：

   Bridge arm circuit on three-phase, the input of bridge arm circuit is connected to described in each phase on the three-phase in bridge arm circuit The signal output part of phase is corresponded in the three-phase high-voltage area of HVIC pipes；

   Bridge arm circuit under three-phase, the input of bridge arm circuit is connected to described under each phase under the three-phase in bridge arm circuit The signal output part of phase is corresponded in the three-phase low-voltage area of HVIC pipes.
7. 7. SPM according to claim 6, it is characterised in that bridge arm circuit includes in each phase：

   Second power switch pipe and the 3rd diode, the anode of the 3rd diode are connected to second power switch pipe Emitter stage, the negative electrode of the 3rd diode are connected to the colelctor electrode of second power switch pipe, second power switch The colelctor electrode of pipe is connected to the high voltage input of the SPM, and the base stage of second power switch pipe is as institute The input of bridge arm circuit in each phase is stated, the emitter stage of second power switch pipe is connected to the SPM pair Answer the higher-pressure region power supply negative terminal of phase.
8. 8. SPM according to claim 7, it is characterised in that bridge arm circuit includes under each phase：

   3rd power switch pipe and the 4th diode, the anode of the 4th diode are connected to the 3rd power switch pipe Emitter stage, the negative electrode of the 4th diode are connected to the colelctor electrode of the 3rd power switch pipe, the 3rd power switch The colelctor electrode of pipe is connected to the anode of the 3rd diode in corresponding upper bridge arm circuit, the 3rd power switch pipe Input of the base stage as bridge arm circuit under each phase, the emitter stage of the 3rd power switch pipe is as the intelligent work( The low reference voltage end of the corresponding phase of rate module.
9. 9. the SPM according to claim 7 or 8, it is characterised in that the high voltage of the SPM The voltage of input is 300V, is connected between the anode and negative terminal of each phase higher-pressure region power supply of the SPM There is filter capacitor.
10. A kind of 10. air conditioner, it is characterised in that including：SPM as claimed in any one of claims 1-9 wherein.