CN103839929A - 射频模块及其制造方法 - Google Patents

射频模块及其制造方法 Download PDF

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CN103839929A
CN103839929A CN201310606590.8A CN201310606590A CN103839929A CN 103839929 A CN103839929 A CN 103839929A CN 201310606590 A CN201310606590 A CN 201310606590A CN 103839929 A CN103839929 A CN 103839929A
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hole
base plate
module
wiring layer
assisting base
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崔丞镕
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Samsung Electro Mechanics Co Ltd
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Abstract

本文公开涉及射频模块及其制造方法。根据本发明的示例性实施方式,RF模块包括:RF IC器件,设置有通孔,该RF IC器件的上表面和下表面通过通孔彼此连接;电子部件,安装在RF IC器件的上表面或下表面上;模制材料,使电子部件被密封于其中以保护电子部件,并且形成在RF IC器件的上表面或下表面上;以及辅助基板,与RF IC器件的上表面或下表面耦接,并且提供安装除了被密封在模制材料中的电子部件之外的其他电子部件的位置,其中,辅助基板设置有具有预定尺寸的通孔以在其中安装其他电子部件。

Description

射频模块及其制造方法
相关申请的交叉引用
本申请要求于2012年11月26日提交的题为“RF(射频)模块及制造其的方法”的韩国专利申请第10-2012-0134455号的权益,在此将其全部内容结合于本申请以供参考。
技术领域
本发明涉及一种RF模块及制造其的方法,且更具体地,涉及一种能够设计圆片级芯片尺寸封装(WLCSP)的IC电路并且能够设计具有足够自由度的输入/输出(I/O)节距(pitch,间距)的RF模块以及制造其的方法。
背景技术
在已用于蜂窝电话等的RF模块中,高频特性非常重要。对高频特性最敏感的部分是在半导体(LSI)芯片终端和外部部件之间的配线。根据现有技术,配线变为结合配线封装基板后电极部件终端的LSI芯片,并且因此变长。在RF模块的情况下,优选地,在模块中增加在模块中的配线数量并且减少在模块中的外部连接终端的数量。在常规模块技术中,封装的基板一侧可采用多层配线和大量配线,但是后电极一侧通常难以采用大量配线。此外,信号路径也具有二维结构。当信号路径具有三维结构时,信号路径可以尽可能地短,并且还可改善高频特性。此外,还可减小安装面积,并且因此可减少产品造价。为此,当三维地安装信号路径时,需要缩短信号路径。
图1是示出根据现有技术的具有其中半导体封装件堆叠在WLCSP上的POP结构的RF模块的示图。
参照图1,在根据现有技术的RF模块中,I/O形成为WLCSP126的TSV134,使用凸块148形成封装件上的封装件(POP)结构,或形成与外部的相互连接。此外,RF模块具有其中器件被进一步安装在半导体管芯(IC)122的上表面和下表面上并且通过TSV134相互连接的结构。在这种情况下,凸块148的高度大于安装在半导体管芯(IC)122上的器件140的高度,使得难以形成精细节距。因此,可能限制电路设计的自由度。
[现有技术文献]
[专利文献]
(专利文献1)美国专利公开第US2011/0215458号
(专利文献2)韩国专利公开第10-2011-0002074号
(专利文献3)日本专利公开第2007-273982号
发明内容
本发明的目的在于提供一种通过允许RF IC器件执行主电路基板的功能并且引入辅助基板来确保I/O实施的灵活性而能够设计圆片级芯片尺寸封装(WLCSP)的IC电路并且能够设计具有足够自由度的输入/输出(I/O)节距的RF模块以及制造其的方法。
根据本发明的示例性实施方式,提供了一种RF模块,包括:RF IC器件,用作主基板并且设置有通孔,所述RF IC器件的上表面和下表面通过所述通孔彼此连接;电子部件,安装在所述RF IC器件的所述上表面或所述下表面上;模制材料,使所述电子部件被密封于其中以保护所述电子部件,并且形成在所述RF IC器件的所述上表面或所述下表面上;以及辅助基板,与所述RF IC器件的所述上表面或所述下表面耦接,并且提供安装除了被密封在所述模制材料中的所述电子部件之外的其他电子部件的位置。
所述辅助基板可设置有具有预定尺寸的通孔以在所述辅助基板中安装所述其他电子部件。
根据本发明的另一示例性实施方式,提供了一种制造RF模块的方法,包括:a)制备用作主基板的RF IC器件;b)在所述RF IC器件中形成通孔并且利用导电材料填充所述通孔,所述RF IC器件的上表面和下表面通过所述通孔彼此连接;c)分别在所述RF IC器件的两个表面上形成金属配线层以连接至所述通孔;d)在所述RF IC器件的一侧的所述金属配线层上安装电子部件;e)利用模制材料模制安装所述电子部件的所述RF IC器件的所述一侧;f)将设置有具有预定尺寸的通孔以便在其中安装其他电子部件的辅助基板与所述RF IC器件的另一表面耦接;以及g)通过所述辅助基板的所述通孔在所述RF IC器件的所述另一表面上安装所述其他电子部件。
在步骤b)中,可通过使用受激准分子激光或CO2激光的干法蚀刻来形成所述通孔。
在步骤b)中,填充在所述通孔中的所述导电材料可以是铜或银。
可通过电镀将所述铜填充在所述通孔中。
制造RF模块的方法可进一步包括:在步骤d)中,为了在所述RF IC器件的所述一侧的所述金属配线层上安装所述电子部件,在所述RF IC器件的所述一侧的所述金属配线层上形成凸块。
在步骤e)中,所述模制材料可以是热固性树脂或热塑性树脂。
制造RF模块的方法可进一步包括:在步骤f)中,为了将所述辅助基板与所述RF IC器件的所述另一表面耦接,在所述RF IC器件的所述另一表面的所述金属配线层上形成凸块。
制造RF模块的方法可进一步包括:在步骤g)中,为了在所述RF IC器件的所述另一表面上安装所述其他电子部件,在与所述辅助基板的所述通孔的区域对应的所述RF IC器件的所述另一表面的所述金属配线层上形成凸块。
附图说明
图1是示出根据现有技术的具有其中半导体封装件堆叠在WLCSP上的PoP结构的RF模块的示图;
图2是示出根据本发明的示例性实施方式的RF模块的结构的示图;
图3是图2的RF模块的辅助基板的平面视图;
图4是示出根据本发明的示例性实施方式的制造RF模块的方法的执行过程的流程图;
图5A至图5E是顺序示出根据制造根据本发明的示例性实施方式的RF模块的方法的制造RF模块的工艺的示图。
具体实施方式
在本说明书和权利要求中使用的术语和词汇不应解释为一般的或者词典的含义,而是基于发明人为了以最佳方式描述他们自己的发明而可以适当定义术语的概念的原则被解释为符合本发明的技术构思的含义和概念。
贯穿本说明书,除非明确地描述与此相反,否则,“包括”任何部件将理解为意指包括其他元件而不排除任何其他元件。在本说明书中描述的术语“部分”、“…器”、“模块”、“器件”等意指处理至少一个功能或操作的单元,并且可通过硬件或软件或者硬件和软件的组合来实施。
下文中,将参照附图详细描述本发明的示例性实施方式。
图2是示出根据本发明的示例性实施方式的RF模块的结构的示图。
参照图2,根据本发明的示例性实施方式的RF模块被配置为包括RFIC器件201、电子部件204a至204c、模制材料205以及辅助基板206。
RF IC器件201用作主基板,并且其内部设置有通孔202,RF IC器件201的上表面和下表面通过通孔202彼此连接。
电子部件204a至204c安装在RF IC器件201的上表面或下表面上。电子部件204a至204c可包括半导体芯片、IC等。
模制材料205形成在RF IC器件201的上表面或下表面(即,安装电子部件的表面)上,从而模制材料205使电子部件204a至204c被密封于其中以保护电子部件204a至204c。在此,作为上述的模制材料205,可使用热固性树脂或热塑性树脂。
辅助基板206耦接在RF IC器件201的上表面或下表面上,并且提供安装除了密封在模制材料205中的电子部件204a至204c之外的其他电子部件207a和207b的位置。
在此,如图3所示,辅助基板206设置有具有预定尺寸的通孔206v以在其中安装其他电子部件207a和207b。类似地,其他电子部件207a和207b也可包括半导体芯片、IC等。在图2中,附图标记203表示金属配线层,并且附图标记211、212以及213分别表示凸块。
接下来,将描述制造具有上述结构的根据本发明的示例性实施方式的RF模块的工艺。
图4是示出根据本发明的示例性实施方式的制造RF模块的方法的执行过程的流程图,并且图5A至图5E是顺序示出根据制造根据本发明的示例性实施方式的RF模块的方法的制造RF模块的工艺的示图。
参照图4和图5A,根据制造根据本发明的示例性实施方式的RF模块的方法,首先制备用作主基板的RF IC器件201(S401)。在此,作为RF IC器件201,可使用硅IC器件。
当完成RF IC器件201的制备时,如图5B所示,在RF IC器件201中形成通孔202并且利用导电材料填充通孔202,RF IC器件201的上表面和下表面通过通孔202彼此连接(S402)。
在此,可通过干法蚀刻或湿法蚀刻形成通孔202,但是优选地,通过使用受激准分子激光或CO2激光的干法蚀刻来形成。此外,作为填充在通孔202中的导电材料,可使用铜或银。在这种情况下,可通过电镀将铜填充在通孔202中。
如上所述,当完成通孔202的形成和导电材料的填充时,如图5C所示,分别在RF IC器件201的两个表面上形成金属配线层203以连接至通孔202(S403)。在此,可通过以下步骤形成期望的金属配线层203:首先在RF IC器件201的两个表面上涂覆绝缘材料(例如,干膜或光敏膜);通过使用掩模和光刻,沿着形成金属配线层的区域以预定图案去除绝缘材料;在通过去除绝缘材料形成的RF IC器件201的两个表面的开放区域中通过使用电镀法等形成金属(例如,铜)配线层;以及然后去除保留在RF IC器件201的两个表面上的绝缘材料。
通过以上描述,当完成金属配线层203的形成时,如图5D所示,在RF IC器件201的一侧的金属配线层203上安装电子部件204a至204c(S404)。在这种情况下,如上所述,为了在RF IC器件201的一侧的金属配线层203上安装电子部件204a至204c,根据本发明的示例性实施方式的方法进一步包括在RF IC器件201的一侧的金属配线层203上形成凸块211。在这种情况下,作为凸块211,可使用普通的焊料凸块。
当完成电子部件204a至204c的安装时,利用模制材料205模制安装电子部件204a至204c的RF IC器件201的一侧(S405)。在这种情况下,作为模制材料205,可使用热固性树脂或热塑性树脂。
当完成模制时,如图5E所示,将辅助基板206与RF IC器件201的另一表面耦接,在辅助基板206上,形成用于在其中安装其他电子部件207a和207b的具有预定尺寸的通孔206v(S406)。
在此,为了将辅助基板206与RF IC器件201的另一表面耦接,根据本发明的示例性实施方式的方法进一步包括在RF IC器件201的另一表面的金属配线层203上形成凸块212。在这种情况下,作为凸块212,可使用普通的焊料凸块。
通过这样做,当完成辅助基板206与RF IC器件201的耦接时,通过辅助基板206的通孔206v在RF IC器件201的另一表面上安装其他电子部件207a和207b(S407)。在这种情况下,为了在RF IC器件201的另一表面上安装其他电子部件207a至207b,根据本发明的示例性实施方式的方法进一步包括在与辅助基板206的通孔206v的区域对应的RF IC器件201的另一表面的金属配线层203上形成凸块213。在这种情况下,作为凸块213,可使用普通的焊料凸块。
在此,如上所述,为了将辅助基板206与RF IC器件201耦接,可单独或同时执行形成凸块212的工艺和用于通过辅助基板206的通孔206v安装其他电子部件207a和207b而形成凸块213的工艺。
如上所述,根据制造根据本发明的示例性实施方式的RF模块的方法,通过允许RF IC器件执行主电路基板的功能并且引入辅助基板以确保I/O实施的灵活性,可以设计圆片级芯片尺寸封装(WLCSP)的IC电路并且可以设计具有足够自由度的I/O节距。
尽管出于说明性的目的,已经公开了本发明的示例性实施方式,但是本发明并不限于此,本领域的技术人员将认识到,在不偏离所附权利要求中公开的本发明的范围和精神的前提下,各种修改、添加和替换是可以的。因此,必需通过所附权利要求来分析本发明的保护范围,并且应当分析为在其等价范围内的所有精神均包括在本发明的所附权利要求中。

Claims (10)

1.一种RF模块,包括:
RF IC器件,用作主基板并且设置有通孔,所述RF IC器件的上表面和下表面通过所述通孔彼此连接;
电子部件,安装在所述RF IC器件的所述上表面或所述下表面上;
模制材料,使所述电子部件被密封于其中以保护所述电子部件,并且形成在所述RF IC器件的所述上表面或所述下表面上;以及
辅助基板,与所述RF IC器件的所述上表面或所述下表面耦接,并且提供安装除了被密封在所述模制材料中的所述电子部件之外的其他电子部件的位置。
2.根据权利要求1所述的RF模块,其中,所述辅助基板设置有具有预定尺寸的通孔以在所述辅助基板中安装所述其他电子部件。
3.一种制造RF模块的方法,包括:
a)制备用作主基板的RF IC器件;
b)在所述RF IC器件中形成通孔并且利用导电材料填充所述通孔,所述RF IC器件的上表面和下表面通过所述通孔彼此连接;
c)分别在所述RF IC器件的两个表面上形成金属配线层以连接至所述通孔;
d)在所述RF IC器件的一侧的所述金属配线层上安装电子部件;
e)利用模制材料对安装有所述电子部件的所述RF IC器件的所述一侧成模;
f)将设置有具有预定尺寸的通孔以便在其中安装其他电子部件的辅助基板与所述RF IC器件的另一表面耦接;以及
g)通过所述辅助基板的所述通孔在所述RF IC器件的所述另一表面上安装所述其他电子部件。
4.根据权利要求3所述的方法,其中,在步骤b)中,通过使用受激准分子激光或CO2激光的干法蚀刻来形成所述通孔。
5.根据权利要求3所述的方法,其中,在步骤b)中,填充在所述通孔中的所述导电材料是铜或银。
6.根据权利要求5所述的方法,其中,通过电镀将所述铜填充在所述通孔中。
7.根据权利要求3所述的方法,进一步包括:
为了在步骤d)中在所述RF IC器件的所述一侧的所述金属配线层上安装所述电子部件,在所述RF IC器件的所述一侧的所述金
属配线层上形成凸块。
8.根据权利要求3所述的方法,其中,步骤e)中的所述模制材料是热固性树脂或热塑性树脂。
9.根据权利要求3所述的方法,进一步包括:
为了在步骤f)中将所述辅助基板与所述RF IC器件的所述另一表面耦接,在所述RF IC器件的所述另一表面的所述金属配线层上形成凸块。
10.根据权利要求3所述的方法,进一步包括:
为了在步骤g)中在所述RF IC器件的所述另一表面上安装所述其他电子部件,在与所述辅助基板的所述通孔的区域对应的所述RF IC器件的所述另一表面的所述金属配线层上形成凸块。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107958878A (zh) * 2016-10-14 2018-04-24 英飞凌科技股份有限公司 Hf组件
CN111883481A (zh) * 2015-06-30 2020-11-03 台湾积体电路制造股份有限公司 3d封装件结构及其形成方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10032722B2 (en) * 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001281A1 (en) * 2005-06-30 2007-01-04 Elpida Memory, Inc. Semiconductor memory device and manufacturing method thereof
CN101299413A (zh) * 2008-06-20 2008-11-05 日月光半导体制造股份有限公司 线路板制造工艺
CN101589468A (zh) * 2007-01-17 2009-11-25 Nxp股份有限公司 具有通过衬底的通路孔的系统级封装
CN102017142A (zh) * 2008-05-09 2011-04-13 国立大学法人九州工业大学 三维安装半导体装置及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4554152B2 (ja) * 2002-12-19 2010-09-29 株式会社半導体エネルギー研究所 半導体チップの作製方法
JP2007188916A (ja) * 2006-01-11 2007-07-26 Renesas Technology Corp 半導体装置
JP5193898B2 (ja) * 2009-02-12 2013-05-08 新光電気工業株式会社 半導体装置及び電子装置
US8058137B1 (en) * 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
JP2011165741A (ja) * 2010-02-05 2011-08-25 Renesas Electronics Corp 半導体装置およびその製造方法
JP2012114334A (ja) * 2010-11-26 2012-06-14 Nec Casio Mobile Communications Ltd キャビティ基板を備える半導体モジュール、その不良解析方法、及び該半導体モジュールの製造方法
US8803326B2 (en) * 2011-11-15 2014-08-12 Xintec Inc. Chip package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001281A1 (en) * 2005-06-30 2007-01-04 Elpida Memory, Inc. Semiconductor memory device and manufacturing method thereof
CN101589468A (zh) * 2007-01-17 2009-11-25 Nxp股份有限公司 具有通过衬底的通路孔的系统级封装
CN102017142A (zh) * 2008-05-09 2011-04-13 国立大学法人九州工业大学 三维安装半导体装置及其制造方法
CN101299413A (zh) * 2008-06-20 2008-11-05 日月光半导体制造股份有限公司 线路板制造工艺

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883481A (zh) * 2015-06-30 2020-11-03 台湾积体电路制造股份有限公司 3d封装件结构及其形成方法
CN111883481B (zh) * 2015-06-30 2023-07-25 台湾积体电路制造股份有限公司 3d封装件结构及其形成方法
CN107958878A (zh) * 2016-10-14 2018-04-24 英飞凌科技股份有限公司 Hf组件

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