KR100645755B1 - 반도체 패키지 및 그 제조방법 - Google Patents
반도체 패키지 및 그 제조방법 Download PDFInfo
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- KR100645755B1 KR100645755B1 KR1020000065894A KR20000065894A KR100645755B1 KR 100645755 B1 KR100645755 B1 KR 100645755B1 KR 1020000065894 A KR1020000065894 A KR 1020000065894A KR 20000065894 A KR20000065894 A KR 20000065894A KR 100645755 B1 KR100645755 B1 KR 100645755B1
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- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
Claims (2)
- 반도체 칩이 실장되는 인쇄회로기판과, 반도체 칩의 본딩패드과 인쇄회로기판의 와이어 본딩용 전도성패턴간에 연결된 와이어와, 상기 반도체 칩과 와이어와 전도성패턴등을 몰딩하고 수지와, 상기 인쇄회로기판의 저면으로 노출된 볼랜드용 전도성패턴에 부착된 인출단자를 포함하는 반도체 패키지에 있어서,상기 인쇄회로기판의 수지층 상면 테두리 부분에 위치한 전도성패턴을 노출시켜 전기적 접속 가능한 전도성물질로 접촉시키고, 상기 반도체 패키지의 몰딩면에 걸쳐 상기 전도성물질과 접촉되게 전도성의 차폐층을 도포한 것을 특징으로 반도체 패키지.
- 다수개의 반도체 패키지 영역이 스트립 형태로 형성되어 있는 인쇄회로기판을 제공하는 단계와; 인쇄회로기판의 칩탑재영역에 반도체 칩을 부착하는 단계와; 상기 반도체 칩의 본딩패드와 상기 인쇄회로기판의 와이어 본딩용 전도성패턴간을 와이어로 본딩하는 단계와; 상기 다수개의 반도체 패키지 영역을 수지로 한꺼번에 몰딩하는 단계와; 상기 인쇄회로기판의 저면으로 노출된 볼랜드용 전도성패턴에 인출단자를 부착하는 단계로 이루어진 반도체 패키지 제조방법에 있어서,상기 반도체 패키지 영역라인을 따라 몰딩된 수지를 관통하는 홀을 가공하되, 상기 인쇄회로기판의 상면 테두리면에 위치된 전도성패턴이 노출되도록 홀을 가공하는 단계와;상기 홀을 통하여 노출된 전도성패턴과 전기적으로 접속 가능하도록 홀에 전도성 물질을 채우는 단계와;상기 홀에 채워진 전도성물질의 상면과 일체로 접촉되면서 상기 각 반도체 패키지 영역의 전체 몰딩면에 걸쳐 전도성의 차폐층을 형성하는 단계와;상기 홀에 채워진 전도성물질을 종방향으로 이등분시키며 낱개의 반도체 패키지로 소잉하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조방법.
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KR1020000065894A KR100645755B1 (ko) | 2000-11-07 | 2000-11-07 | 반도체 패키지 및 그 제조방법 |
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KR20020036039A KR20020036039A (ko) | 2002-05-16 |
KR100645755B1 true KR100645755B1 (ko) | 2006-11-13 |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101046251B1 (ko) * | 2009-05-19 | 2011-07-04 | 앰코 테크놀로지 코리아 주식회사 | 적층형 반도체 패키지 |
KR101046250B1 (ko) * | 2008-12-18 | 2011-07-04 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지의 전자파 차폐장치 |
US8937370B2 (en) | 2011-05-25 | 2015-01-20 | Samsung Electronics Co., Ltd. | Memory device and fabricating method thereof |
KR101571526B1 (ko) | 2007-12-13 | 2015-11-24 | 스태츠 칩팩, 엘티디. | 전자기 장애를 차폐하는 집적회로 패키지 시스템 |
US9433117B1 (en) | 2010-02-18 | 2016-08-30 | Amkor Technology, Inc. | Shield lid interconnect package and method |
KR101698292B1 (ko) * | 2016-01-05 | 2017-01-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 모듈 |
US9818699B2 (en) | 2015-03-10 | 2017-11-14 | Samsung Electronics Co., Ltd. | Semiconductor packages and methods of fabricating the same |
US10177095B2 (en) | 2017-03-24 | 2019-01-08 | Amkor Technology, Inc. | Semiconductor device and method of manufacturing thereof |
US10483222B1 (en) | 2010-03-19 | 2019-11-19 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
Families Citing this family (6)
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KR100679834B1 (ko) * | 2000-12-29 | 2007-02-07 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지의 제조 방법 |
KR101053544B1 (ko) * | 2008-12-10 | 2011-08-03 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
US8008754B2 (en) | 2008-12-10 | 2011-08-30 | Hynix Semiconductor Inc. | Semiconductor package having an antenna with reduced area and method for fabricating the same |
KR101247343B1 (ko) * | 2011-09-30 | 2013-03-26 | 에스티에스반도체통신 주식회사 | 전자파 차폐 수단을 갖는 반도체 패키지 제조방법 |
CN106409793B (zh) * | 2015-07-29 | 2019-11-26 | 乾坤科技股份有限公司 | 具有电磁屏蔽结构的电子模组及其制造方法 |
KR102669030B1 (ko) | 2019-12-06 | 2024-05-23 | 광주대학교산학협력단 | 반도체 소자의 패키징 방법 |
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KR19980033656A (ko) * | 1998-05-06 | 1998-07-25 | 김훈 | 반도체 패키지 및 그 제조방법 |
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2000
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Patent Citations (4)
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JPH08288686A (ja) * | 1995-04-20 | 1996-11-01 | Nec Corp | 半導体装置 |
JPH11145333A (ja) * | 1997-09-02 | 1999-05-28 | Oki Electric Ind Co Ltd | 半導体装置 |
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101571526B1 (ko) | 2007-12-13 | 2015-11-24 | 스태츠 칩팩, 엘티디. | 전자기 장애를 차폐하는 집적회로 패키지 시스템 |
KR101046250B1 (ko) * | 2008-12-18 | 2011-07-04 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지의 전자파 차폐장치 |
KR101046251B1 (ko) * | 2009-05-19 | 2011-07-04 | 앰코 테크놀로지 코리아 주식회사 | 적층형 반도체 패키지 |
US10424556B2 (en) | 2010-02-18 | 2019-09-24 | Amkor Technology, Inc. | Shielded electronic component package |
US9433117B1 (en) | 2010-02-18 | 2016-08-30 | Amkor Technology, Inc. | Shield lid interconnect package and method |
US11031366B2 (en) | 2010-02-18 | 2021-06-08 | Amkor Technology Singapore Pte. Ltd. | Shielded electronic component package |
US11646290B2 (en) | 2010-02-18 | 2023-05-09 | Amkor Technology Singapore Holding Pte. Ltd. | Shielded electronic component package |
US10483222B1 (en) | 2010-03-19 | 2019-11-19 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US8937370B2 (en) | 2011-05-25 | 2015-01-20 | Samsung Electronics Co., Ltd. | Memory device and fabricating method thereof |
US9818699B2 (en) | 2015-03-10 | 2017-11-14 | Samsung Electronics Co., Ltd. | Semiconductor packages and methods of fabricating the same |
KR101698292B1 (ko) * | 2016-01-05 | 2017-01-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 모듈 |
US10177095B2 (en) | 2017-03-24 | 2019-01-08 | Amkor Technology, Inc. | Semiconductor device and method of manufacturing thereof |
US10410973B2 (en) | 2017-03-24 | 2019-09-10 | Amkor Technology, Inc. | Semiconductor device and method of manufacturing thereof |
US11063001B2 (en) | 2017-03-24 | 2021-07-13 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and method of manufacturing thereof |
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