CN103811588A - Double-faced diffusion technology of solar battery - Google Patents
Double-faced diffusion technology of solar battery Download PDFInfo
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- CN103811588A CN103811588A CN201410038290.9A CN201410038290A CN103811588A CN 103811588 A CN103811588 A CN 103811588A CN 201410038290 A CN201410038290 A CN 201410038290A CN 103811588 A CN103811588 A CN 103811588A
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- crystal silicon
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- boron
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 117
- 238000005516 engineering process Methods 0.000 title abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 160
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 144
- 239000010703 silicon Substances 0.000 claims abstract description 144
- 239000012535 impurity Substances 0.000 claims abstract description 116
- 238000000576 coating method Methods 0.000 claims abstract description 114
- 239000011248 coating agent Substances 0.000 claims abstract description 112
- 239000013078 crystal Substances 0.000 claims abstract description 110
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052796 boron Inorganic materials 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000011241 protective layer Substances 0.000 claims abstract description 22
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 58
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 42
- 229910052698 phosphorus Inorganic materials 0.000 claims description 42
- 239000011574 phosphorus Substances 0.000 claims description 42
- 239000007788 liquid Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000006185 dispersion Substances 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 11
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical group O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 11
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical group O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 238000005245 sintering Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000008367 deionised water Substances 0.000 claims description 8
- 229910021641 deionized water Inorganic materials 0.000 claims description 8
- 239000002245 particle Substances 0.000 claims description 8
- 238000003892 spreading Methods 0.000 claims description 8
- 230000007480 spreading Effects 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000005507 spraying Methods 0.000 claims description 7
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical group OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052809 inorganic oxide Inorganic materials 0.000 claims description 4
- 150000007522 mineralic acids Chemical class 0.000 claims description 4
- 238000009966 trimming Methods 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 claims description 3
- 239000004327 boric acid Substances 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 claims description 2
- 238000002242 deionisation method Methods 0.000 claims description 2
- 235000008216 herbs Nutrition 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 210000002268 wool Anatomy 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 239000004615 ingredient Substances 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 21
- 239000000758 substrate Substances 0.000 description 20
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 18
- 239000012071 phase Substances 0.000 description 12
- 238000000151 deposition Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000007650 screen-printing Methods 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 238000007747 plating Methods 0.000 description 7
- 230000009514 concussion Effects 0.000 description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 description 6
- 238000010790 dilution Methods 0.000 description 6
- 239000012895 dilution Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 239000005543 nano-size silicon particle Substances 0.000 description 6
- DLYUQMMRRRQYAE-UHFFFAOYSA-N tetraphosphorus decaoxide Chemical group O1P(O2)(=O)OP3(=O)OP1(=O)OP2(=O)O3 DLYUQMMRRRQYAE-UHFFFAOYSA-N 0.000 description 6
- 229910004205 SiNX Inorganic materials 0.000 description 5
- 239000012530 fluid Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 239000010453 quartz Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 238000000889 atomisation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 3
- 229910020286 SiOxNy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010923 batch production Methods 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000010792 warming Methods 0.000 description 2
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 1
- QVMHUALAQYRRBM-UHFFFAOYSA-N [P].[P] Chemical compound [P].[P] QVMHUALAQYRRBM-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 150000001639 boron compounds Chemical class 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Photovoltaic Devices (AREA)
Abstract
The invention discloses a double-faced diffusion technology of a solar battery. The technology comprises the following steps: (1) selecting a crystal silicon wafer, and washing a first surface and a second surface of the crystal silicon wafer after the flocking; (2) preparing an impurity coating on the second surface of the crystal silicon wafer; (3) preparing a protective layer on the impurity coating on the second surface of the crystal silicon wafer; and (4) performing high temperature boron diffusion or phosphorous diffusion on the crystal silicon wafer: performing high temperature boron re-diffusion or phosphorous re-diffusion on the second surface of the crystal silicon wafer, and then performing boron diffusion or phosphorous diffusion on the first surface of the crystal silicon wafer to form a p-n knot, so as to realize the double-faced diffusion of the crystal silicon wafer; and obtaining the solar battery by subsequent processes. The impurity coating adopted by the method is stable in property, simple in ingredients, succinct in technology of the technological process, and is likely to be compatible with existing production lines and production equipments.
Description
Technical field
The invention belongs to photovoltaic cell technical field, be specifically related to a kind of Double side diffusion technique of solar cell.
Background technology
Phosphorus diffusion (p-type silicon substrate) technique of tradition crystal silicon solar batteries is generally one side diffusion, the surface that does not need diffusion impurity is positioned in carrier face-to-face, in diffusion furnace, only the sensitive surface of solar cell is carried out to phosphorus doping to form emitter, and battery is carried on the back surperficial heavy doping passivation, double-side cell, N-type battery etc. all needs two sides all to carry out different impurity element diffusions, the advantage of Double side diffusion is both can carry out gettering to non-sensitive surface, and then improve cell voltage and export, can can both receive incident light in two sides again, thereby make the overall power output of solar cell array improve 10-30%.Adopt at present two-sided Impurity Diffusion, general auxiliary with silk screen printing, two kinds of modes of liquid gas phase, it is the making that non-sensitive surface spreads required impurity source by the mode of silk screen printing that patent CN201210127547.9 adopts phosphorus slurry; CN201210127523.3 adopts boron slurry, is also to adopt screen printing mode to make, and realizes the heavily doped one side battery of back side boron element; CN200810177806.2 invention is that second silk screen printing dopant source layer mode manufactured double-side cell; And by liquid gas phase mode just like document number CN200910034985.9 for successively by inert gas carry boron source, liquid gas phase diffusion is carried out in phosphorus source.No matter no matter be that screen printing mode or gas phase are taken source side formula, all need the process of 2-4 step could realize the doping on required surface, be that equipment, diffusion furnace tube etc. are all had to higher requirement, and consuming cost increase, processing step complexity.
Compared to existing two kinds of conventional modes, adopt coating to carry impurity element and make impurity diffusion layer, there is the feature that technique is simple, cost is low, in CN201210548232, invent a kind of coating fluid that carries boron source, coating fluid comprises boron compound, organic binder bond, silicon compound and alumina precursor and water etc., and this coating fluid is for being diffused into boron silicon substrate to form p type diffused layer; In CN201210379725.7 and CN201210001178.9, respectively silicon dioxide gel coating liquid and silica dioxide gel layer are done to research.But coating fluids of the prior art etc. exist unstable, easily there is the shortcomings such as sex change, reunion, sedimentation, and complicated component, high for diffusion technology cost, process complexity, is unfavorable for suitability for industrialized production and the combination utilization with existing technique.
Summary of the invention
The object of the present invention is to provide a kind of Double side diffusion technique of solar cell, the impurity coating performance of this process using is stable, and composition is simple, and technical process technique is succinct, and cost is low, is easy to existing production line and production equipment compatible mutually.
Above-mentioned purpose of the present invention realizes by following technical measures: a kind of Double side diffusion technique of solar cell, contains following steps:
(1) choose p-type or N-shaped crystal silicon chip, will after first surface and second surface making herbs into wool, clean;
(2) on the second surface of crystal silicon chip, make impurity coating;
(3) in the impurity coating of crystal silicon chip second surface, make protective layer;
(4) to p-type crystal silicon chip, first second surface is carried out to high temperature boron and heavily diffuse to form the heavy diffusion layer of boron, then the first surface of crystal silicon chip is carried out to phosphorus diffuse to form p-n junction, realize the Double side diffusion of crystal silicon chip, through subsequent handling, prepare solar cell again; To N-shaped crystal silicon chip, first second surface is carried out to high temperature phosphorous and heavily diffuse to form the heavy diffusion layer of phosphorus, then the first surface of crystal silicon chip is carried out to boron diffuse to form p-n junction, realize the Double side diffusion of crystal silicon chip, then through subsequent handling, prepare solar cell.
Adopt the diffusion technology in the present invention, phosphorus diffusion and boron can be diffused in same boiler tube and realize, need to once enter stove, once come out of the stove, from in conventional method, need repeatedly to enter stove, come out of the stove differently, adopt the diffusion technology in the present invention, can a step realize the two sides diffusion of crystal silicon chip.Adopt the impurity coating in the present invention to combine with diffusion technology, can reach in same boiler tube, adopt different diffusion temperatures to realize phosphorus, boron Double side diffusion, solved the drawback that needs repeatedly to pass in and out stove in conventional method.
Diffusion technology in the present invention, first the silica dispersions that adopts the method for spin coating or ultrasonic spraying to be evenly distributed at silicon chip one side formation one deck is carried the coating in boron or phosphorus impurities source, back-to-back packing in quartz boat after drying, reset corresponding diffusion technology, can a step realize the one side diffusion of coated side or the diffusion of the two sides of coated side and non-coated side, and then coordinate subsequent technique can produce dissimilar battery, as heavily spread passivation one side battery, N-type battery etc. in double-side cell, the back side.Increase manufacturing facilities not obvious, on the basis of the costs such as operation, can reach the object of two sides diffusion different impurities.
Solar battery diffusion technology in the present invention, on the basis of existing P type silicon one side battery diffusion technology, the process program that adopts boron, phosphorus to spread respectively at same boiler tube, can simplify battery production process by this scheme, be more convenient for realizing the batch production of double-side cell, N-type battery, reduce battery manufacture cost, reduce because operation is numerous and diverse the cell piece performance loss that uncertain factor too much causes.
As a modification of the present invention: make impurity coating in step of the present invention (2) on the second surface of crystal silicon chip, can also make the impurity coating of the impurity source type opposite of impurity coating on impurity source type and second surface simultaneously on the first surface of crystal silicon chip.
When wherein impurity source type opposite refers to impurity source that the hypothesis impurity coating of making on second surface adopts and is phosphorus source, the impurity source that the impurity coating of making on first surface adopts is boron source, equally, suppose that impurity source that the impurity coating of making adopts is boron source on second surface time, the impurity source that the impurity coating of making on first surface adopts is phosphorus source.
For p-type silicon substrate, adopting the surface that the impurity coating that carries boron element spreads is its second surface.
For N-shaped silicon substrate, adopting the surface that the impurity coating that carries P elements spreads is its second surface.
The coating that impurity coating described in step of the present invention (2) adopts is preferably the nanometer SiO that contains boron impurity source or phosphorus impurities source
2dispersion liquid; Wherein said boron impurity source is preferably the inorganic oxide or the inorganic acid that contain boron element; Described phosphorus impurities source is preferably the inorganic oxide or the inorganic acid that contain P elements.
Boron impurity of the present invention source is diboron trioxide or boric acid, and described phosphorus impurities source is phosphoric acid; Described nanometer SiO
2nanometer SiO in dispersion liquid
2particle diameter be 40～200nm; Described nanometer SiO
2in dispersion liquid, decentralized medium is deionized water, ethanol or isopropyl alcohol, and wherein deionization resistivity of water is more than 18M Ω cm.
Consider colloidal sol, the unsteadiness of gel, use for reference the advantage of coating fluid, the present invention adopts silica nanometer dispersion liquid, silica nanometer dispersion phase is to more stable, be not easy to occur sex change, reunite, even if sedimentation also easily recovers uniform dispersity, disperse therein, dissolve the dopant of required element, except required element, other harmful components can be controlled at limited level by choosing high-purity material, can make equally easily coating, take source diffusion without silk screen printing or the two-sided gas phase replacing, processing procedure is easy, effectively reduce process equipment cost.
Impurity coating described in step of the present invention (2) preferably adopts spin-coating method or ultrasonic atomizatio spraying process to make; In step (2), on the second surface of crystal silicon chip, make on the first surface of impurity coating or crystal silicon chip and second surface and all make after impurity coating, preferably dry film forming at 200～400 ℃.
Protective layer described in step of the present invention (3) is preferably silicon nitride SiN
x, silicon dioxide SiO
2or silicon-oxygen nitride SiO
xn
y, its thickness is preferably 80～150nm.
Wherein protective layer can adopt direct method plasma deposition to make.
Temperature when high temperature boron spreads in step of the present invention (4) is 950～970 ℃, and temperature when high temperature phosphorous diffusion is 820～860 ℃; Wherein for p-type crystal silicon chip, second surface is carried out to high temperature boron while heavily spreading, the second surface of adjacent two crystal silicon chips is arranged face-to-face, be placed in diffusion carrier, carry out high temperature boron and heavily diffuse to form the heavy diffusion layer of boron, the mode that adopts gas phase to carry liquid phosphorus impurity source when the first surface of crystal silicon chip is carried out to phosphorus diffusion is carried out phosphorus diffusion to form p-n junction; Wherein for N-shaped crystal silicon chip, second surface is carried out to high temperature phosphorous while heavily spreading, the second surface of adjacent two crystal silicon chips is arranged face-to-face, be placed in diffusion carrier, carry out high temperature phosphorous and heavily diffuse to form the heavy diffusion layer of phosphorus, the mode that adopts gas phase to carry liquid boron impurity source when the first surface of crystal silicon chip is carried out to boron diffusion is carried out boron diffusion to form p-n junction.
For make impurity coating in step (2) on the second surface of crystal silicon chip, while making the impurity coating of impurity source type opposite of impurity coating on impurity source type and second surface on the first surface of crystal silicon chip simultaneously, temperature when high temperature boron spreads in step of the present invention (4) is 950～970 ℃, and temperature when high temperature phosphorous diffusion is 820～860 ℃; Wherein for p-type crystal silicon chip, second surface is carried out to high temperature boron while heavily spreading, the second surface of adjacent two crystal silicon chips is arranged face-to-face, be placed in diffusion carrier, carry out high temperature boron and heavily diffuse to form the heavy diffusion layer of boron, the impurity coating of making on the first surface of crystal silicon chip by propelling when the first surface of crystal silicon chip is carried out to phosphorus diffusion is to form p-n junction; Wherein for N-shaped crystal silicon chip, second surface is carried out to high temperature phosphorous while heavily spreading, the second surface of adjacent two crystal silicon chips is arranged face-to-face, be placed in diffusion carrier, carry out high temperature phosphorous and heavily diffuse to form the heavy diffusion layer of phosphorus, the impurity coating of making on the first surface of crystal silicon chip by propelling when the first surface of crystal silicon chip is carried out to boron diffusion is to form p-n junction.
Subsequent handling described in step of the present invention (4) comprises employing following steps: (5) chemical corrosion liquid cleans the glassy layer forming while removing impurity coating, protective layer and High temperature diffusion; (6) on the first surface of crystal silicon chip, prepare passivation layer, on the second surface of crystal silicon chip, prepare passivation layer or metal conducting layer; (7) on the first surface of crystal silicon chip and second surface, prepare metal electrode, and carry out sintering metal, make solar cell.
As a kind of preferred implementation in the present invention, the impurity coating that impurity coating described in step (2) is dimension constraint or the impurity coating of non-dimension constraint, in the time of impurity coating that described impurity coating is dimension constraint, the exterior contour of described impurity coating inwardly dwindles 0.4～1.0mm than the exterior contour of crystal silicon chip, in the time of impurity coating that described impurity coating is non-dimension constraint, between step (4) and step (5), have additional etching trimming knot step.Wherein etching trimming knot can using plasma etching be removed the limit knot at crystal silicon chip edge.
While adopting chemical corrosion liquid to clean the glassy layer forming while removing impurity coating, protective layer and High temperature diffusion in step of the present invention (5), chemical corrosion liquid can be hydrofluoric acid.
In step of the present invention (6), for p-type silicon substrate, the passivation layer on crystal silicon chip first surface is preferably SiN
xor SiO
2deielectric-coating, the passivation layer of second surface is preferably SiO
2or Al
2o
3or second surface is not established passivation layer; For N-shaped silicon substrate, be preferably SiO at the passivation layer of the first surface of crystal silicon chip
2or Al
2o
3deielectric-coating, second surface is preferably SiN
xor SiO
2deielectric-coating.Wherein, in the time that second surface is not established passivation layer, can on second surface, prepare metal conducting layer as the conductive layer that adopts metal A l to make, metal A l can adopt aluminium paste silk screen printing or sputter to prepare metal aluminium lamination.
Compared with prior art, tool of the present invention has the following advantages:
(1) the solar cell Double side diffusion technique in the present invention, can make boron diffusion and phosphorus phosphorus be diffused in successively diffusion in same boiler tube, can simplify battery production process by this scheme, be convenient to realize the batch production of double-side cell, N-type battery, reduce battery manufacture cost, reduce because operation is numerous and diverse the cell piece performance loss that uncertain factor too much causes;
(2) in solar cell Double side diffusion technique of the present invention, the silica nanometer dispersion liquid of preparing impurity coating adopting, it is more stable, be not easy to occur sex change, reunion, even if sedimentation also easily recovers uniform dispersity, disperse therein, dissolve the dopant of required element, except required element, other compositions can be controlled at limited level by choosing high-purity material, can make equally easily impurity coating, without silk screen printing, or repeatedly do the process of mask;
(3) solar cell Double side diffusion technique of the present invention, by the size of impurity coating being less than to the size of crystal silicon chip, and make the size of protective layer and the sizableness of crystal silicon chip, and by the two-sided making impurity coating at crystal silicon chip, etching trimming knot step can be removed from, the area of silicon chip edge and the contribution to battery performance can be retained to greatest extent;
(4) the inventive method also has obvious reduction hardware input, simplifies production procedure, reduce production costs, and the features such as environmental friendliness.
Accompanying drawing explanation
Figure 1A is the schematic diagram of preparing boron-containing impurities coating and protective layer in the embodiment of the present invention 1 at p-type crystal silicon chip second surface;
Figure 1B is the schematic diagram that the second surface that in the embodiment of the present invention 1, two p-type crystal silicon chips is covered with to protective layer is placed in carrier face-to-face;
Fig. 1 C is that in the embodiment of the present invention 1, p-type crystal silicon chip is heavily diffused in the heavy diffusion layer of second surface formation boron and diffuses to form the schematic diagram of p-n junction and phosphorosilicate glass at first surface through phosphorus through boron;
Fig. 1 D is that in the embodiment of the present invention 1, p-type crystal silicon chip is removed the schematic diagram after the knot of limit;
Fig. 1 E is that in the embodiment of the present invention 1, p-type crystal silicon chip is removed the schematic diagram after protective layer, impurity coating and phosphorosilicate glass;
Fig. 1 F is the schematic diagram of p-type crystal silicon chip after first surface plating passivated reflection reducing membrane in the embodiment of the present invention 1;
Fig. 1 G be in the embodiment of the present invention 1 p-type crystal silicon chip at second surface plating passivating film and prepare the structural representation of the solar cell with transparent two sides structure of the preparation after metal electrode co-sintering at first surface and second surface;
Fig. 2 A prepares boron-containing impurities coating and prepares the schematic diagram of protective layer at second surface at p-type crystal silicon chip second surface and first surface in the embodiment of the present invention 2;
Fig. 2 B is the schematic diagram that the second surface that in the embodiment of the present invention 2, two P type crystal silicon chips is covered with to protective layer is placed in carrier face-to-face;
Fig. 2 C is that in the embodiment of the present invention 2, p-type crystal silicon chip is heavily diffused in the heavy diffusion layer of second surface formation boron and diffuses to form the schematic diagram of p-n junction at first surface through phosphorus through boron;
Fig. 2 D is that in the embodiment of the present invention 2, p-type crystal silicon chip is removed the schematic diagram after second surface protective layer, first surface impurity coating and second surface impurity coating;
Fig. 2 E is the schematic diagram of p-type crystal silicon chip after first surface plating passivated reflection reducing membrane in the embodiment of the present invention 2;
Fig. 2 F be in the embodiment of the present invention 1 p-type crystal silicon chip at second surface plating conductive layer and prepare the structural representation of the solar cell of the preparation after metal electrode co-sintering at first surface and second surface;
Fig. 3 A is the schematic diagram of preparing boron-containing impurities coating and protective layer in the embodiment of the present invention 3 at p-type crystal silicon chip second surface;
Fig. 3 B is the schematic diagram that the second surface that in the embodiment of the present invention 3, two P type crystal silicon chips is covered with to protective layer is placed in carrier face-to-face;
Fig. 3 C be that in the embodiment of the present invention 3, p-type crystal silicon chip is heavily diffused in through boron that second surface forms the heavy diffusion layer of boron and diffuse to form p-n junction at first surface through phosphorus with phosphorosilicate glass schematic diagram;
Fig. 3 D is that in the embodiment of the present invention 3, p-type crystal silicon chip is removed the schematic diagram after second surface protective layer, second surface impurity coating and phosphorosilicate glass;
Fig. 3 E is the schematic diagram of p-type crystal silicon chip after first surface plating passivated reflection reducing membrane in the embodiment of the present invention 3;
Fig. 3 F is p-type crystal silicon chip and prepare the structural representation of the solar cell of the preparation after metal electrode co-sintering at first surface and second surface in the embodiment of the present invention 3;
Fig. 4 A prepares at N-shaped crystal silicon chip second surface and first surface the schematic diagram that contains phosphorus impurities coating and prepare protective layer at second surface in the embodiment of the present invention 4;
Fig. 4 B is the schematic diagram that the second surface that in the embodiment of the present invention 4, two N-shaped crystal silicon chips is covered with to protective layer is placed in carrier face-to-face;
Fig. 4 C is that in the embodiment of the present invention 4, N-shaped crystal silicon chip is heavily diffused in the heavy diffusion layer of second surface formation phosphorus and diffuses to form the schematic diagram of p-n junction at first surface through boron through phosphorus;
Fig. 4 D is that in the embodiment of the present invention 4, N-shaped crystal silicon chip is removed the schematic diagram after second surface protective layer, first surface impurity coating and second surface impurity coating;
Fig. 4 E is the schematic diagram of N-shaped crystal silicon chip after first surface plating passivated reflection reducing membrane in the embodiment of the present invention 4;
Fig. 4 F be in the embodiment of the present invention 4 N-shaped crystal silicon chip at second surface plating passivating film and prepare the structural representation of the solar cell with transparent two sides structure of the preparation after metal electrode co-sintering at first surface and second surface.
Embodiment
Embodiment 1
As shown in Figure 1A-1G, the Double side diffusion technique of the p-type crystal silicon solar energy battery that the present embodiment provides, concrete containing following steps: with p-type crystalline silicon silicon 1001, through chemical surface, mechanical damage layer is removed in texturing simultaneously, described silicon chip surface is passed through to 5%(wt) the hydrofluoric acid weak solution cleaning of (quality percentage composition), adopt the nano silicon dispersion liquid of 90 ± 50nm particle diameter substep, add the diboron trioxide powder of purity 4N, with the deionized water dilution of 18M Ω cm, and concussion mixes, dispersion liquid is spin-coated on to silicon chip in spin coater wherein on a side surface, it is the second surface of so-called p-type silicon substrate, dry 30min for 200 ℃, solidify to form the coating 1201 that contains impurity source, the SiNx deielectric-coating 1202 that is 100nm at the direct plasma vapor phase deposition deposit thickness of second surface utilization, as shown in Figure 1A, it is fixing that the second surface that two silicon chips are covered with to SiNx deielectric-coating is put into the same gap of quartz boat carrier face-to-face, heat up and pass into clean nitrogen and realize the inert atmosphere in boiler tube, to 950 ℃ of maintenance 30min, realize boron impurity to the diffusion of silicon substrate inside and continue to advance the heavy diffusion layer 1203 of formation, pass into clean oxygen oxidation first surface, and be cooled to 800 ℃ simultaneously, passing into phosphorus oxychloride reacts and realizes the deposition of phosphorus pentoxide at first surface, be warming up to 830 ℃ of propellings that realize P elements and form in the lump p-n junction 1102, as shown in Figure 1B-1C, adopt plasma etching silicon chip edge to reach to remove the N-shaped surface at edge the object of cutting off the first and second surfaces, as shown in Fig. 1 D, hydrofluoric acid weak solution with 5% is removed coating 1201, the phosphorosilicate glass 1103 forming in protective medium film 1202 and P elements diffusion process, as shown in Fig. 1 E, adopt direct plasma gas phase deposition SiNx dielectric layer as p-n junction passivation and reduce the anti-reflection layer 1104 that light reflects at first surface, as shown in Fig. 1 F, make the SiO of direct plasma gas-phase deposit at second surface
2as the passivation layer 1204 of second surface, make respectively the ohmic contact of second surface electrode 1205, first surface electrode 1105 common sintering realization and silicon substrate, form the crystal silicon cell that first surface p-n junction, second surface boron heavily spread, can transparent two sides, as shown in Figure 1 G, coating simple for production, removed printing from or repeatedly done the process of mask.
Embodiment 2
As shown in Fig. 2 A-2F, the Double side diffusion technique of one side battery is heavily spread at the p-type crystal silicon chip back side that the present embodiment provides, concrete containing following steps: with p-type crystalline silicon silicon 2001, through chemical surface, mechanical damage layer is removed in texturing simultaneously, described silicon chip surface is passed through to 5% hydrofluoric acid weak solution cleaning, adopt the nano silicon dispersion liquid of 120 ± 50nm particle diameter substep, add the boric acid of purity 99.8%, with the deionized water dilution of 18M Ω cm, and concussion mixes, adopt ultrasonic atomization spraying by the vaporific droplet settling of dispersion liquid at silicon chip wherein on a side surface, it is the second surface of so-called p-type silicon substrate, dry 20min for 250 ℃, solidify to form the coating 2201 that contains impurity source, the SiO that is 120nm at the direct plasma vapor phase deposition deposit thickness of second surface utilization
2deielectric-coating 2202, adopt the nano silicon dispersion liquid of 120 ± 50nm particle diameter substep, add the phosphorus pentoxide powder of purity 4N, with the deionized water dilution of 18M Ω cm, and concussion mixes, adopt ultrasonic atomization spraying by the vaporific droplet settling of dispersion liquid at silicon chip wherein on a side surface, be the first surface of so-called p-type silicon substrate, dry 20min, solidify to form the coating 2101 that contains impurity source for 250 ℃, as shown in Figure 2 A, two silicon chips are covered with to SiO
2it is fixing that the second surface of deielectric-coating is put into the same gap of quartz boat carrier face-to-face, heat up and pass into clean nitrogen and realize the inert atmosphere in boiler tube, to 960 ℃ of maintenance 25min, realize boron impurity to the diffusion of silicon substrate inside and continue to advance the heavy diffusion layer 2203 of formation, fast cooling to 830 ℃, continue to advance P elements to form p-n junction 2102, due to the SiO adopting
2deielectric-coating 2202 has been protected second surface and edge, can avoid the extrorse diffusion of phosphorus, therefore exempted and adopted plasma etching silicon chip edge to isolate the step on the first and second surfaces, as shown in Fig. 2 B-2C, the coating 2101 that hydrofluoric acid weak solution with 5% is removed coating 2201, protective medium film 2202 and contained P elements, as shown in Figure 2 D, adopt direct plasma gas phase deposition SiO at first surface
2dielectric layer is as p-n junction passivation and reduce the anti-reflection layer 2104 that light reflects, as shown in Figure 2 E, make respectively the ohmic contact of second surface electrode 2205, second surface aluminum metal layer 2204, first surface electrode 2105 common sintering realization and silicon substrate, form the crystal silicon cell that first surface p-n junction, second surface boron heavily spread one side and be subject to light, as shown in Figure 2 F, strengthened the passivation effect at the back side, the battery that is conducive to low-doped matrix is made.
Embodiment 3
As shown in Fig. 3 A-3F, the p-type crystalline silicon one side that the present embodiment provides is subject to photronic Double side diffusion technique, concrete containing following steps: with p-type crystalline silicon silicon 3001, through chemical surface, mechanical damage layer is removed in texturing simultaneously, described silicon chip surface is passed through to 5% hydrofluoric acid weak solution cleaning, adopt the nano silicon dispersion liquid of 150 ± 50nm particle diameter substep, add the diboron trioxide powder of purity 4N, ethanol with 99.8% and deionized water dilution, and concussion mixes, dispersion liquid is deposited on to silicon chip wherein on a side surface with the form of atomized drop with ultrasonic atomizatio spraying, it is the second surface of so-called p-type silicon substrate, before deposition, retrain the scope of droplet deposition by the template of specific dimensions, make the edge 3201 ' of coating finally be less than the largest contours of silicon chip, be 1.0mm apart from silicon chip outermost edges 3202 ', dry 10min for 200 ℃, solidify to form the coating 3201 that contains impurity source, the SiOxNy deielectric-coating 3202 that is 150nm at the direct plasma vapor phase deposition deposit thickness of second surface utilization, as shown in Figure 3A, it is fixing that the second surface that two silicon chips are covered with to SiOxNy deielectric-coating is put into the same gap of quartz boat carrier face-to-face, heat up and pass into clean nitrogen and realize the inert atmosphere in boiler tube, to 950 ℃ of maintenance 20min, realize boron impurity to the diffusion of silicon substrate inside and continue to advance the heavy diffusion layer 3203 of formation, pass into clean oxygen oxidation first surface, and be cooled to 800 ℃ simultaneously, passing into phosphorus oxychloride reacts and realizes the deposition of phosphorus pentoxide at first surface, be warming up to 830 ℃ of propellings that realize P elements and form in the lump p-n junction 3102, because the impurity coating 3201 and the silicon chip second surface that have adopted profile constraint also have extra deielectric-coating 3202 to protect, in the process of phosphorus diffusion, can prevent that the scope between silicon chip back side coating edge 3201 ' and silicon chip edge 3202 ' from also diffusing into P elements simultaneously, so just do not need to carry out again the plasma etching at edge under this flow process, can retain to greatest extent the area of silicon chip edge and the contribution to battery performance, as shown in Fig. 3 B-3C, hydrofluoric acid weak solution with 5% is removed coating 3201, the phosphorosilicate glass 3103 of protective medium film 3202 and first surface, as shown in Figure 3 D, adopt direct plasma gas phase deposition SiNx dielectric layer as p-n junction passivation and reduce the anti-reflection layer 3104 that light reflects at first surface, as shown in Fig. 3 E, make respectively second surface electrode 3205, second surface aluminum metal layer 3204, the ohmic contact of first surface electrode 3105 common sintering realization and silicon substrate, form first surface p-n junction, the pedion (pedia) silion cell that second surface boron heavily spreads, as shown in Fig. 3 F, the part of the silicon chip edge retaining to greatest extent, it is higher that the reliability of making is compared embodiment 2.
Embodiment 4
As shown in Fig. 4 A-4F, the Double side diffusion technique of the N-shaped crystalline silicon double-side cell that the present embodiment provides, concrete containing following steps: with N-shaped crystalline silicon silicon 4001, through chemical surface, mechanical damage layer is removed in texturing simultaneously, described silicon chip surface is passed through to 5% hydrofluoric acid weak solution cleaning, adopt the nano silicon dispersion liquid of 100 ± 50nm particle diameter substep, add purity 85.0% chromatographically pure phosphoric acid, with the deionized water dilution of 18M Ω cm, and concussion mixes, adopt ultrasonic atomization spraying by the vaporific droplet settling of dispersion liquid at silicon chip wherein on a side surface, it is the second surface of so-called N-shaped silicon substrate, before deposition, retrain the scope of droplet deposition by the template of specific dimensions, make the edge 4201 ' of coating finally be less than the largest contours of silicon chip, be 0.4mm apart from silicon chip outermost edges 4202 ', dry 15min for 250 ℃, solidify to form the coating 4201 that contains impurity source, the SiO2 deielectric-coating 4202 that is 150nm at the direct plasma vapor phase deposition deposit thickness of second surface utilization, adopt the nano silicon dispersion liquid of 100 ± 50nm particle diameter substep, add the diboron trioxide powder of purity 4N, ethanol with 99.8% and deionized water dilution, and concussion mixes, with spin coater by dispersion liquid with another side make uniform coating, it is the first surface of so-called N-shaped silicon substrate, dry 20min for 200 ℃, solidify to form the coating 4101 that contains impurity source, as shown in Figure 4 A, two silicon chips are covered with to SiO
2it is fixing that the second surface of deielectric-coating is put into the same gap of quartz boat carrier face-to-face, heat up and pass into clean nitrogen and realize the inert atmosphere in boiler tube, to 970 ℃ of maintenance 15min, realize boron impurity to the diffusion of silicon substrate inside and continue to advance formation p-n junction 4102, the distribution of fast cooling to 840 ℃ stable P elements also forms heavy diffusion layer 4203, because the impurity coating 4201 and the silicon chip second surface that have adopted profile constraint also have extra deielectric-coating 4202 to protect, in the process of phosphorus diffusion, can prevent that the scope between silicon chip back side coating edge 4201 ' and silicon chip edge 4202 ' from also diffusing into boron element simultaneously, so just do not need to carry out again the plasma etching at edge under this flow process, can retain to greatest extent the area of silicon chip edge and the contribution to battery performance, as shown in Fig. 4 B-4C, hydrofluoric acid weak solution with 5% is removed coating 4201, the coating 4101 of protective medium film 3202 and first surface, as shown in Figure 4 D, adopt ald Al at first surface
2o
3with the anti-reflection layer 4104 of SiO2 dielectric layer as p-n junction passivation and the reflection of reduction light, as shown in Figure 4 E, adopt ald SiNx dielectric layer as passivating back and reduce the anti-reflection layer 4204 that light reflects at second surface, make respectively the ohmic contact of second surface electrode 4205, first surface electrode 4105 common sintering realization and silicon substrate, formation first surface p-n junction, second surface phosphorus heavily spread, the two-sided N-shaped crystal silicon cell that is subject to light, as shown in Fig. 4 F.
The present invention will be described more than to enumerate specific embodiment.It is pointed out that above embodiment, only for the invention will be further described, does not represent protection scope of the present invention, nonessential modification and adjustment that other people prompting according to the present invention is made, still belong to protection scope of the present invention.
Claims (10)
1. a Double side diffusion technique for solar cell, is characterized in that containing following steps:
(1) choose p-type or N-shaped crystal silicon chip, will after first surface and second surface making herbs into wool, clean;
(2) on the second surface of crystal silicon chip, make impurity coating;
(3) in the impurity coating of crystal silicon chip second surface, make protective layer;
(4) to p-type crystal silicon chip, first second surface is carried out to high temperature boron and heavily diffuse to form the heavy diffusion layer of boron, then the first surface of crystal silicon chip is carried out to phosphorus diffuse to form p-n junction, realize the Double side diffusion of crystal silicon chip, through subsequent handling, prepare solar cell again; To N-shaped crystal silicon chip, first second surface is carried out to high temperature phosphorous and heavily diffuse to form the heavy diffusion layer of phosphorus, then the first surface of crystal silicon chip is carried out to boron diffuse to form p-n junction, realize the Double side diffusion of crystal silicon chip, then through subsequent handling, prepare solar cell.
2. the Double side diffusion technique of solar cell according to claim 1, it is characterized in that: in step (2), on the second surface of crystal silicon chip, make impurity coating, on the first surface of crystal silicon chip, make the impurity coating of the impurity source type opposite of impurity coating on impurity source type and second surface simultaneously.
3. the Double side diffusion technique of solar cell according to claim 1 and 2, is characterized in that: the coating that the impurity coating described in step (2) adopts is the nanometer SiO that contains boron impurity source or phosphorus impurities source
2dispersion liquid; Wherein said boron impurity source is inorganic oxide or the inorganic acid that contains boron element; Described phosphorus impurities source is inorganic oxide or the inorganic acid that contains P elements.
4. the Double side diffusion technique of solar cell according to claim 3, is characterized in that: described boron impurity source is diboron trioxide or boric acid, and described phosphorus impurities source is phosphoric acid; Described nanometer SiO
2nanometer SiO in dispersion liquid
2particle diameter be 40～200nm; Described nanometer SiO
2in dispersion liquid, decentralized medium is deionized water, ethanol or isopropyl alcohol, and wherein deionization resistivity of water is more than 18M Ω cm.
5. the Double side diffusion technique of solar cell according to claim 1 and 2, is characterized in that: the impurity coating described in step (2) adopts spin-coating method or ultrasonic atomizatio spraying process to make; In step (2), on the second surface of crystal silicon chip, make on the first surface of impurity coating or crystal silicon chip and second surface and all make after impurity coating, dry film forming at 200～400 ℃.
6. the Double side diffusion technique of solar cell according to claim 1 and 2, is characterized in that: the protective layer described in step (3) is silicon nitride SiN
x, silicon dioxide SiO
2or silicon-oxygen nitride SiO
xn
y, its thickness is 80～150nm.
7. the Double side diffusion technique of solar cell according to claim 1, is characterized in that: temperature when high temperature boron spreads in step (4) is 950～970 ℃, and temperature when high temperature phosphorous diffusion is 820～860 ℃; Wherein for p-type crystal silicon chip, second surface is carried out to high temperature boron while heavily spreading, the second surface of adjacent two crystal silicon chips is arranged face-to-face, be placed in diffusion carrier, carry out high temperature boron and heavily diffuse to form the heavy diffusion layer of boron, the mode that adopts gas phase to carry liquid phosphorus impurity source when the first surface of crystal silicon chip is carried out to phosphorus diffusion is carried out phosphorus diffusion to form p-n junction; Wherein for N-shaped crystal silicon chip, second surface is carried out to high temperature phosphorous while heavily spreading, the second surface of adjacent two crystal silicon chips is arranged face-to-face, be placed in diffusion carrier, carry out high temperature phosphorous and heavily diffuse to form the heavy diffusion layer of phosphorus, the mode that adopts gas phase to carry liquid boron impurity source when the first surface of crystal silicon chip is carried out to boron diffusion is carried out boron diffusion to form p-n junction.
8. the Double side diffusion technique of solar cell according to claim 2, is characterized in that: temperature when high temperature boron spreads in step (4) is 950～970 ℃, and temperature when high temperature phosphorous diffusion is 820～860 ℃; Wherein for p-type crystal silicon chip, second surface is carried out to high temperature boron while heavily spreading, the second surface of adjacent two crystal silicon chips is arranged face-to-face, be placed in diffusion carrier, carry out high temperature boron and heavily diffuse to form the heavy diffusion layer of boron, the impurity coating of making on the first surface of crystal silicon chip by propelling when the first surface of crystal silicon chip is carried out to phosphorus diffusion is to form p-n junction; Wherein for N-shaped crystal silicon chip, second surface is carried out to high temperature phosphorous while heavily spreading, the second surface of adjacent two crystal silicon chips is arranged face-to-face, be placed in diffusion carrier, carry out high temperature phosphorous and heavily diffuse to form the heavy diffusion layer of phosphorus, the impurity coating of making on the first surface of crystal silicon chip by propelling when the first surface of crystal silicon chip is carried out to boron diffusion is to form p-n junction.
9. the Double side diffusion technique of solar cell according to claim 1, is characterized in that: the subsequent handling described in step (4) comprises employing following steps: (5) chemical corrosion liquid cleans the glassy layer forming while removing impurity coating, protective layer and High temperature diffusion; (6) on the first surface of crystal silicon chip, prepare passivation layer, on the second surface of crystal silicon chip, prepare passivation layer or metal conducting layer; (7) on the first surface of crystal silicon chip and second surface, prepare metal electrode, and carry out sintering metal, make solar cell.
10. the Double side diffusion technique of solar cell according to claim 9, it is characterized in that: the impurity coating that the impurity coating described in step (2) is dimension constraint or the impurity coating of non-dimension constraint, in the time of impurity coating that described impurity coating is dimension constraint, the exterior contour of described impurity coating inwardly dwindles 0.4～1.0mm than the exterior contour of crystal silicon chip, in the time of impurity coating that described impurity coating is non-dimension constraint, between step (4) and step (5), have additional etching trimming knot step.
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157740A (en) * | 2014-09-03 | 2014-11-19 | 苏州阿特斯阳光电力科技有限公司 | N-type two-side solar cell manufacturing method |
| CN107068804A (en) * | 2017-03-30 | 2017-08-18 | 山东力诺太阳能电力股份有限公司 | A kind of method that solar cell is prepared in N-type silicon substrate |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102241899A (en) * | 2010-05-11 | 2011-11-16 | 3M创新有限公司 | Coating composition, method for modifying matrix surface, and product coated by the coating composition |
| CN102263159A (en) * | 2011-05-31 | 2011-11-30 | 江阴鑫辉太阳能有限公司 | Process for preparing n-type solar cell by utilizing boron-phosphorus coamplification |
| CN102280519A (en) * | 2011-05-30 | 2011-12-14 | 奥特斯维能源（太仓）有限公司 | Process for preparing high-efficient full back electrode n type solar cell with utilization of boron-phosphorus codiffusion |
| CN102437238A (en) * | 2011-11-30 | 2012-05-02 | 晶澳（扬州）太阳能科技有限公司 | Method for boron doping of crystalline silicon solar battery |
| KR20130089053A (en) * | 2012-02-01 | 2013-08-09 | 현대중공업 주식회사 | Method for fabricating bi-facial solar cell |
-
2014
- 2014-01-26 CN CN201410038290.9A patent/CN103811588B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102241899A (en) * | 2010-05-11 | 2011-11-16 | 3M创新有限公司 | Coating composition, method for modifying matrix surface, and product coated by the coating composition |
| CN102280519A (en) * | 2011-05-30 | 2011-12-14 | 奥特斯维能源（太仓）有限公司 | Process for preparing high-efficient full back electrode n type solar cell with utilization of boron-phosphorus codiffusion |
| CN102263159A (en) * | 2011-05-31 | 2011-11-30 | 江阴鑫辉太阳能有限公司 | Process for preparing n-type solar cell by utilizing boron-phosphorus coamplification |
| CN102437238A (en) * | 2011-11-30 | 2012-05-02 | 晶澳（扬州）太阳能科技有限公司 | Method for boron doping of crystalline silicon solar battery |
| KR20130089053A (en) * | 2012-02-01 | 2013-08-09 | 현대중공업 주식회사 | Method for fabricating bi-facial solar cell |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157740B (en) * | 2014-09-03 | 2017-02-08 | 苏州阿特斯阳光电力科技有限公司 | N-type two-side solar cell manufacturing method |
| CN104157740A (en) * | 2014-09-03 | 2014-11-19 | 苏州阿特斯阳光电力科技有限公司 | N-type two-side solar cell manufacturing method |
| CN109983586A (en) * | 2016-11-03 | 2019-07-05 | 道达尔销售服务公司 | The surface treatment of solar battery |
| CN109983586B (en) * | 2016-11-03 | 2024-03-12 | 道达尔销售服务公司 | Surface treatment of solar cells |
| CN107068804A (en) * | 2017-03-30 | 2017-08-18 | 山东力诺太阳能电力股份有限公司 | A kind of method that solar cell is prepared in N-type silicon substrate |
| CN107359112A (en) * | 2017-08-02 | 2017-11-17 | 巨力新能源股份有限公司 | A kind of preparation method of the two-sided crystal silicon battery of p-type |
| CN107359112B (en) * | 2017-08-02 | 2021-06-01 | 巨力新能源股份有限公司 | Manufacturing method of P-type double-sided crystalline silicon battery |
| CN108054088A (en) * | 2017-12-15 | 2018-05-18 | 浙江晶科能源有限公司 | N-type silicon chip Boron diffusion method, crystal silicon solar energy battery and preparation method thereof |
| CN108447949B (en) * | 2018-05-18 | 2024-01-26 | 常州亿晶光电科技有限公司 | Chain type diffusion process and chain type diffusion equipment |
| CN108447949A (en) * | 2018-05-18 | 2018-08-24 | 常州亿晶光电科技有限公司 | A kind of chain type diffusion technique and chain type diffusion equipment |
| CN109950347A (en) * | 2019-04-02 | 2019-06-28 | 河北大学 | A kind of preparation method of double-side cell |
| CN112582259A (en) * | 2019-09-30 | 2021-03-30 | 扬州扬杰电子科技股份有限公司 | Novel N-type layer phosphorus doping process method |
| CN111059999A (en) * | 2019-12-31 | 2020-04-24 | 苏州能斯达电子科技有限公司 | Flexible bending sensor and manufacturing method thereof |
| CN111640825A (en) * | 2020-06-16 | 2020-09-08 | 东方日升（常州）新能源有限公司 | Manufacturing method of N-type contact passivation solar cell and method for improving yield |
| CN111640825B (en) * | 2020-06-16 | 2021-09-21 | 东方日升（常州）新能源有限公司 | Manufacturing method of N-type contact passivation solar cell and method for improving yield |
| CN111916347A (en) * | 2020-08-13 | 2020-11-10 | 中国电子科技集团公司第四十四研究所 | Phosphorus diffusion doping method for SOI (silicon on insulator) wafer |
| WO2023025021A1 (en) * | 2021-08-25 | 2023-03-02 | 中国科学院宁波材料技术与工程研究所 | Impurity diffusion method and solar cell manufacturing method |
| CN114068315A (en) * | 2021-11-16 | 2022-02-18 | 南京欣之禾安全技术有限公司 | Environment-friendly diffusion source for solar cell |
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