CN103733310A - 半导体元件以及半导体元件的制造方法 - Google Patents
半导体元件以及半导体元件的制造方法 Download PDFInfo
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Abstract
本发明提供一种半导体元件,即使在制造工序等中暴露于高温下的情况下,也能抑制半导体区与电极之间的原子的相互扩散,并且抑制界面电阻上升。本发明的半导体元件具备包含硅的半导体区、包含铝的电极、以及介于所述半导体区与电极之间并且含有锗的防扩散层,所述防扩散层的至少一部分的锗含量为4原子%以上。
Description
技术领域
本发明涉及半导体元件以及半导体元件的制造方法。
背景技术
近年来,绝缘栅(MOS)型半导体装置作为控制大电力的功率器件正在普及。作为上述MOS型半导体装置,例如可举出IGBT(绝缘栅型双极晶体管)、功率MOSFET(功率MOS型场效应晶体管)等。
作为上述MOS型半导体装置,以下参考图1说明代表性的IGBT的一般结构。图1的IGBT1具备:p型集电极层2、在该集电极层2的表面形成的n型基极层3、在该基极层3的表面分开形成的p型体区4、以及在各个该体区4的表面形成的n型发射极层5。该集电极层2、基极层3、体区4、以及发射极层5通常是在基板内部形成的部分。集电极电极6连接于上述集电极层2。上述基极层3中,位于两个发射极层5之间的区域是沟道区7。陔IGBT1还具有在沟道区7的表面依次形成的栅极绝缘膜8和栅极电极膜9。另外,在发射极层5的表面形成发射极电极10。该发射极电极10与栅极电极9通过层间绝缘膜11进行绝缘。集电极电极6经由焊层直接固定和电连接于电路基板等。发射极电极10的表面连接有金属制的电线或带状电缆,通过它们电连接于外部端子。此外,集电极电极6等电极使用由纯铝或铝合金形成的铝系电极等。
这种IGBT1中的n型半导体区(基极层3、发射极层5)以及p型半导体区(集电极层2、体区4)例如通过如下处理形成:在由硅(Si)等形成的基板中,离子注入磷(P)、砷(As)、硼(B)等,随后进行用于激活的热处理。此外,上述离子注入以对各区域分别确定的剂量、加速电压、注入角度等进行,热处理也以对各区域分别确定的温度、时间等进行。具体而言,在上述IGBT1的制造过程中,例如在基板表面形成发射极电极10后,从基板背面进行对集电极层2的离子注入。接着,通过进行450℃以下的热处理来进行激活。另外,在利用焊接进行接合时,有时有加热至250℃左右的回流工序。
在这种制造过程中,通常,上述热处理的温度越高,则相互接触的电极与硅(半导体区)之间的原子的相互扩散越大。为了防止该相互扩散,电极有时使用含有百分之一至百分之几的硅的Al-Si合金。但是,即使使用这种合金,对于450℃以上的热处理,也不能完全防止上述相互扩散。此外,专利文献1中记载了为了激活集电极层实施800~950℃的热处理的内容,但这种高温的热处理限于电极形成之前。在形成了电极的状态下,仅实施450℃以下的热处理,未记载以更高温进行热处理的情况。
这样,在形成了Al系电极的状态下进行热处理的情况下,使热处理温度升高至450℃以上时,相互接触的电极与硅之间会产生原子的相互扩散。但是,相反在使热处理温度较低时,集电极层的激活需要长达几小时的时间,或者激活不充分。
其中,作为抑制上述相互扩散的技术,专利文献2中公开了在Al系电极与半导体区的界面上配置作为防扩散层的氮化层的方法。但是,上述氮化层由绝缘性的SiN或AlN等形成,因此界面电阻增高,导致电力损失。此外,若使上述氮化层足够薄,例如为10nm以下,则利用隧道效应等可在某种程度上减小电阻,但由于原本为绝缘体,所以其效果有限。另外,上述氮化层越薄,则相互扩散也越容易进行,因此防扩散性能与界面电阻的减小具有折衷(trade-off)的关系。因此,在使用上述方法的情况下,需要将氮化层精确控制为平衡性好的厚度,这在现实中非常困难。
现有技术文献
专利文献
专利文献1:日本专利公开公报2007-242699号
专利文献2:日本专利公开公报2008-10801号
发明内容
发明要解决的课题
本发明基于上述情况而作,目的在于提供一种半导体元件、以及这种半导体元件的制造方法,即使在制造过程等暴露于高温下的情况下,也能抑制半导体区与电极之间的原子的相互扩散,并且抑制界面电阻上升。
用于解决课题的手段
本发明提供如下半导体元件以及半导体元件的制造方法。
(1)一种半导体元件,具备:
半导体区,其包含硅;
电极,其包含铝;以及
防扩散层,其介于所述半导体区与电极之间,含有锗,
所述防扩散层的至少一部分的锗含量为4原子%以上。
根据该半导体元件,包含指定量的锗的防扩散层介于半导体区与电极之间,因此能够抑制在此之间的原子的相互扩散。另外,根据该半导体元件,上述防扩散层通过包含半导体的锗,能够抑制由于存在该防扩散层而导致的界面电阻上升。
(2)根据(1)所述的半导体元件,所述防扩散层的至少一部分的锗含量为4原子%以上且50原子%以下,
所述防扩散层的膜厚为0.5nm以上且100nm以下。
通过使上述防扩散层的至少一部分的锗含量和膜厚取上述范围,能够抑制生产成本,同时发挥更良好的防扩散性能。
(3)根据(2)所述的半导体元件,所述防扩散层的至少一部分的锗含量为20原子%以上且30原子%以下,
所述防扩散层的膜厚为1nm以上且5nm以下。
通过进一步将上述防扩散层的至少一部分的锗含量和膜厚限定于上述范围,能够进一步提高上述效果。
(4)(1)至(3)中任一项所述的半导体元件的制造方法,具有:
在包含硅的半导体区的表面,形成包含锗的铝合金膜的工序;以及
对形成了所述铝合金膜的半导体区进行热处理的工序。
(5)根据(4)所述的半导体元件的制造方法,所述铝合金膜中的锗含量为0.1原子%以上且3原子%以下,并且所述热处理的温度为300℃以上且600℃以下。
根据该制造方法,上述热处理时在半导体区与铝合金膜之间形成包含锗的防扩散层,因此能够抑制该热处理时等情况下的半导体区与铝合金膜(电极)之间的原子的相互扩散。
(6)利用(4)或(5)所述的制造方法得到的半导体元件。
利用该制造方法得到的半导体元件可抑制半导体区与铝合金膜(电极)之间的原子的相互扩散,另外,虽然形成了防扩散层,但界面电阻的上升得到了抑制。
这里,元素的含量(原子%)是通过进行使用EDX(能量分散型X线分析)的元素分析而得到的值。另外,上述防扩散层的“一部分”指上述分析时的一次测定中的测定区域。上述防扩散层的膜厚是使用TEM(透射型电子显微镜)测定了任意5点的膜厚得到的平均值。
发明效果
如以上所说明,根据本发明的半导体元件,即使在暴露于高温下的情况下,也能抑制半导体区与电极之间的原子的相互扩散,并且抑制界面电阻上升。这样,该半导体元件能够适用于MOS型半导体装置等。另外,根据该制造方法,能够高效地制造上述半导体元件。
附图说明
图1是表示一般的IGBT的示意性剖视图。
图2是表示实施例的半导体元件中的半导体区与电极的界面的截面TEM图像。
具体实施方式
以下详细说明本发明的半导体元件以及半导体元件的制造方法的实施方式。
<半导体元件>
本发明的半导体元件具备半导体区、电极、以及存在于上述半导体区与电极之间的防扩散层。
上述半导体区包含硅。上述半导体区由通常包含硅作为主成分的公知的半导体材料(硅基板、碳化硅基板等)形成。上述半导体区除了硅以外,还可以含有磷、砷、硼等,在此情况下,磷、砷、硼等的含量优选为1016/cm3~1019/cm3。
上述电极经由上述防扩散层与上述半导体区相接。如后面所详细描述,上述防扩散层并非为绝缘性,所以上述电极电连接于上述半导体区。
上述电极包含铝作为主成分。作为上述电极,能够使用公知的纯铝或铝合金。该合金成分不作特别限定,能够举出硅、铜、氮、稀土类元素(钕、钇等)等。在包含硅作为合金元素的情况下,其含量优选为0.5~1.0原子%。在包含铜作为合金元素的情况下,其含量优选为0.1~0.5原子%。在包含稀土类元素作为合金元素的情况下,其含量优选为0.2~2.0原子%。
上述防扩散层如上所述介于半导体区与电极之间。具体而言,例如在半导体区为集电极层,电极为与该集电极层电连接的集电极电极的情况下,上述防扩散层介于上述集电极层与集电极电极之间。另外,在半导体区为发射极层,电极为与该发射极层电连接的发射极电极的情况下,上述防扩散层介于上述发射极层与发射极电极之间。
上述防扩散层包含锗。根据该半导体元件,通过具有包含锗的防扩散层,即使施加高温(例如超过450℃的温度)下的热处理,也能够抑制半导体区的硅与电极的铝之间的相互扩散。
这里,锗虽然为半导体,但在室温下电阻率约为70μΩ·cm,具有近似于金属的值。这样,即使在上述防扩散层仅由锗形成时,与现有的绝缘性防扩散层(SiN等)的情况相比,也能够显著降低界面电阻。另外,该半导体元件中存在包含锗的防扩散层,因此通过半导体区中的硅元素和锗,能够形成具有共价键特征的Si-Ge键合。Si-Ge也是半导体,但在加热时,电极的铝自动作为受主被掺杂,使上述防扩散层的电阻变低。
这样,根据该半导体元件,通过具有包含锗的防扩散层,无论该防扩散层是仅由锗形成,还是包含了其他元素(例如硅元素等),与现有的防扩散层相比都能够降低界面电阻。此外,该界面电阻对上述防扩散层的膜厚不敏感。这样,根据该半导体元件,不太需要严格控制上述防扩散层的膜厚,能够缓和制造过程的控制条件,能够容易地形成防扩散层。
上述防扩散层的至少一部分中的锗含量的下限为4原子%,优选为20原子%。通过使锗含量为上述下限以上,上述防扩散层能够发挥充分的防扩散性能。
该锗含量的上限不作特别限定,但考虑成本等方面,优选为50原子%,更优选30原子%。在上述上限以下的情况下,认为在化学计量中和实际中都形成充分的Si-Ge键合,能够发挥充分的防扩散性能,同时能够实现低电阻化。
作为上述防扩散层中的锗以外的成分,能够包含硅、铝。
在上述防扩散层包含硅的情况下,上述防扩散层的至少一部分中的硅含量的下限优选为4原子%,更优选20原子%。另一方面,其上限优选为50原子%,更优选30原子%。另外,作为上述一部分中的硅含量(原子%)对锗含量(原子%)的比,优选为0.3以上且3以下,进一步优选0.5以上且2以下。通过使上述防扩散层中的硅含量取上述范围,能够在防扩散层中形成充分的Si-Ge键合,能够提高防扩散性能,实现低电阻化。
上述防扩散层的膜厚的下限优选0.5nm,更优选1nm。通过使膜厚为上述下限以上,上述防扩散层能够发挥充分的防扩散性能。
此外,在上述防扩散层的膜厚为1nm以上,并且该防扩散层的至少一部分中的锗含量为20原子%以上的情况下,例如即使在500℃加热20分钟,也能够发挥几乎100%的防扩散性能。
该防扩散层的膜厚的上限不作特别限定,但考虑成本等方面,优选为100nm,更优选5nm。
这样,根据该半导体元件,即使在暴露于高温下的情况下,也可抑制半导体区与电极之间的原子的相互扩散,并且抑制界面电阻的上升。其结果是,使用本发明时,例如在IGBT的制造过程中,能够以450℃以上的高温进行用于集电极层的离子激活等的热处理。这样,能够以高温进行热处理后,可缩短工序时间,能够减少制造成本。另外,根据该半导体元件,利用高温热处理,提高了离子注入到集电极层等中的掺杂剂的激活率,能够实现性能提高。此外,根据该半导体元件,在工作过程中由于某种原因流过浪涌式电流,因其焦耳热局部性地使温度快速上升时,也能够抑制原子的相互扩散,因此不易产生不可逆的破坏,提高了可靠性。
<半导体元件的制造方法>
该半导体元件的制造方法不作特别限定,能够使用如下制造方法等:
(1)制造方法,具有:
在包含硅的半导体区的表面,形成包含锗的铝合金膜的工序;以及
对形成了所述铝合金膜的半导体区进行热处理的工序。
(2)制造方法,具有:
在包含硅的半导体区的表面,利用溅射法等形成防扩散层的工序;以及
在所述防扩散层的表面形成铝膜或铝合金膜的工序。此外,所述铝膜或铝合金膜在得到的半导体元件中作为电极发挥作用。
在上述制造方法中,优选上述(1)制造方法。在上述(1)制造方法中,通过进行热处理,锗从铝合金膜析出或集结到界面上。因此,热处理时,在半导体区与铝合金膜之间形成包含锗的防扩散层。这样,能够抑制该热处理时等情况下的半导体区与铝合金膜之间的原子的相互扩散。另外,根据上述(1)制造方法,通过调整铝合金膜中的锗含量等,能够容易地控制所形成的防扩散层的膜厚。在此情况下,例如,能够较为容易地进行5nm以下的薄的防扩散层的形成,能够抑制价格高的锗的使用量。
这样,通过上述制造方法得到的半导体元件可抑制半导体区与铝合金膜(电极)之间的原子的相互扩散,另外,虽然形成了防扩散层,但界面电阳的上升得到了抑制。
上述铝合金膜的成膜方法不作特别限定,能够使用公知的方法(溅射法、蒸镀法等)。
上述铝合金膜中的锗的含量不作特别限定,例如能够采用0.1原子%以上且3原子%以下。
上述热处理的方法不作特别限定,能够使用公知的方法。此外,上述热处理既可以兼用作向半导体区进行离子注入后的用于激活的热处理,也可以进行独立的热处理。
上述热处理的温度、时间也不作特别限定。温度例如能够采用300℃以上且600℃以下(优选为450℃以上且550℃以下)。时间例如能够采用5分钟以上且1小时以下(优选为30分钟以上且1小时以下)。
此外,在该半导体元件的制造中,上述工序以外的工序(例如离子注入等)能够采用公知的方法。
实施例
以下通过实施例进一步详细说明本发明,但本发明不限定于这些实施例。
通过以下方法测定了所得到的半导体元件的防扩散层中各成分的含量和膜厚。
<含量>
通过EDX线分析进行了各成分的含量的测定。该EDX线分析使用了场发射型透射电子显微镜HF-2000(日立制作所制造)及其附带的EDX分析装置Sigma(Kevex制造)。此时,EDX线分析以约5nm的间隔在测定点取得了数据。
此外,使用的上述装置中的入射电子束直径为1~2nm左右,但由于样品内部的电子束散射的影响扩大为5nm左右,拾取其信息。另外,EDX分析半定量计算,产生10%左右的误差。因此,需要注意并解释的是,含量的绝对值不仅有分析点数据的绝对值的一面,而且还具有线分析数据的相对的含义。
<膜厚>
使用TEM(上述场发射型透射电子显微镜HF-2000(日立制作所制造))测定了防扩散膜上的任意5点的膜厚,取其平均值。
实施例1
在作为半导体区的单晶硅基板(面方向100)的表面上,通过磁控管溅射法,形成了包含0.5原子%的锗的铝合金膜。接着,在惰性气体(N2)的环境中进行以500℃保持20分钟的热处理。这样,在硅基板(半导体区)与铝合金膜(电极)之间形成防扩散层,得到了实施例1的半导体元件。
通过上述方法测定了所得到的半导体元件的防扩散层中的各成分的含量和膜厚。表1中示出各成分的含量。另外,图2中示出所得到的半导体元件的截面TEM图像。此外,表1中的“点”表示图2的箭头的位置。另外,膜厚为3.0nm。
表1
如图2的截面TEM图像所示,确认了在电极(A1)21与半导体区(Si)22之间形成了防扩散层23,同时未发现Al与Si的相互扩散。
该防扩散层23被认为是铝合金膜中包含的Ge从热处理的最初开始就集中到半导体区的界面上,通过Si-Ge的共价键形成了牢固的层而得到的。如果在热处理过程中,即便在局部处存在了Al与Si直接接触的界面,则由于Al与Si的扩散速度非常快,所以应当已经从该部分产生了扩散。根据未观察到扩散这一事实,能够判断,在热处理的最初阶段就形成了防扩散层,热处理之后,Ge集结到界面上(Al与Si之间),由Ge或Ge与Si的键合发挥了该防扩散作用。
参考特定实施方式详细说明了本申请,但对于本领域技术人员而言显而易见的是,能够在不脱离本发明的精神和范围的情况下增加各种变更或修正。
本申请基于2011年7月19日提出的日本专利申请(特愿2011-157571),其内容作为参考引入于此。
产业上的可利用性
本发明的半导体元件能够适用于IGBT、功率MOSFET等MOS型半导体装置。
符号说明
1 IGBT
2集电极层
3 基极层
4 体区
5 发射极层
6 集电极电极
7 沟道区
8 栅极绝缘膜
9 栅极电极膜
10 发射极电极
11 层间绝缘膜
21 电极(Al)
22 半导体区(Si)
23 防扩散层
权利要求书(按照条约第19条的修改)
1.(修改后)一种半导体元件,其特征在于具备:
半导体区,其包含硅;
电极,其包含铝作为主成分;以及
防扩散层,其介于所述半导体区与电极之间,含有锗以及硅,
所述防扩散层的至少一部分的锗含量为4原子%以上且50原子%以下,硅含量相对于所述锗含量为0.3以上且3以下,所述防扩散层的膜厚为1nm以上且5nm以下。
2.(修改后)根据权利要求1所述的半导体元件,其特征在于:
所述防扩散层的至少一部分的锗含量为20原子%以上且30原子%以下。
3.(修改后)一种权利要求1或2所述的半导体元件的制造方法,其特征在于具有:
在包含硅的半导体区的表面,形成包含锗的铝合金膜的工序;以及
对形成了所述铝合金膜的半导体区进行热处理的工序。
4.(修改后)一种利用权利要求3所述的制造方法得到的半导体元件。
5.(删除)
6.(删除)
Claims (6)
1.一种半导体元件,其特征在于具备:
半导体区,其包含硅;
电极,其包含铝;以及
防扩散层,其介于所述半导体区与电极之间,含有锗,
所述防扩散层的至少一部分的锗含量为4原子%以上。
2.根据权利要求1所述的半导体元件,其特征在于:
所述防扩散层的至少一部分的锗含量为4原子%以上且50原子%以下,
所述防扩散层的膜厚为0.5nm以上且100nm以下。
3.根据权利要求2所述的半导体元件,其特征在于:
所述防扩散层的至少一部分的锗含量为20原子%以上且30原子%以下,
所述防扩散层的膜厚为1nm以上且5nm以下。
4.一种权利要求1至3中任一项所述的半导体元件的制造方法,其特征在于具有:
在包含硅的半导体区的表面,形成包含锗的铝合金膜的工序;以及
对形成了所述铝合金膜的半导体区进行热处理的工序。
5.根据权利要求4所述的半导体元件的制造方法,其特征在于:
所述铝合金膜中的锗含量为0.1原子%以上且3原子%以下,并且所述热处理的温度为300℃以上且600℃以下。
6.一种利用权利要求4所述的制造方法得到的半导体元件。
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JP2011157571A JP5303008B2 (ja) | 2011-07-19 | 2011-07-19 | 半導体素子及び半導体素子の製造方法 |
JP2011-157571 | 2011-07-19 | ||
PCT/JP2012/068383 WO2013012050A1 (ja) | 2011-07-19 | 2012-07-19 | 半導体素子及び半導体素子の製造方法 |
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JP (1) | JP5303008B2 (zh) |
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JP2001185571A (ja) * | 1999-12-22 | 2001-07-06 | Matsushita Electronics Industry Corp | 突起電極の形成方法およびその形成装置 |
CN101599522A (zh) * | 2009-06-30 | 2009-12-09 | 厦门市三安光电科技有限公司 | 一种采用绝缘介质阻挡层的垂直发光二极管及其制备方法 |
JP2011035153A (ja) * | 2009-07-31 | 2011-02-17 | Kobe Steel Ltd | 薄膜トランジスタ基板および表示デバイス |
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JPH065734B2 (ja) * | 1985-09-28 | 1994-01-19 | 新日本無線株式会社 | 半導体装置 |
JP2730265B2 (ja) * | 1990-05-14 | 1998-03-25 | 日本電気株式会社 | 半導体装置とその製造方法 |
JPH04280424A (ja) * | 1991-03-07 | 1992-10-06 | Hitachi Ltd | 半導体配線構造およびその製造方法 |
JP3804945B2 (ja) * | 1996-04-29 | 2006-08-02 | 株式会社半導体エネルギー研究所 | 薄膜トランジスタの作製方法 |
US6607948B1 (en) * | 1998-12-24 | 2003-08-19 | Kabushiki Kaisha Toshiba | Method of manufacturing a substrate using an SiGe layer |
JP3940385B2 (ja) * | 2002-12-19 | 2007-07-04 | 株式会社神戸製鋼所 | 表示デバイスおよびその製法 |
JP2008010801A (ja) | 2005-08-17 | 2008-01-17 | Kobe Steel Ltd | ソース−ドレイン電極、薄膜トランジスタ基板およびその製造方法、並びに表示デバイス |
JP4826290B2 (ja) | 2006-03-06 | 2011-11-30 | トヨタ自動車株式会社 | 半導体素子の製造方法 |
JP2010238800A (ja) * | 2009-03-30 | 2010-10-21 | Kobe Steel Ltd | 表示装置用Al合金膜、薄膜トランジスタ基板および表示装置 |
US8536043B2 (en) * | 2011-01-31 | 2013-09-17 | International Business Machines Corporation | Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001185571A (ja) * | 1999-12-22 | 2001-07-06 | Matsushita Electronics Industry Corp | 突起電極の形成方法およびその形成装置 |
CN101599522A (zh) * | 2009-06-30 | 2009-12-09 | 厦门市三安光电科技有限公司 | 一种采用绝缘介质阻挡层的垂直发光二极管及其制备方法 |
JP2011035153A (ja) * | 2009-07-31 | 2011-02-17 | Kobe Steel Ltd | 薄膜トランジスタ基板および表示デバイス |
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EP2741318A1 (en) | 2014-06-11 |
EP2741318A4 (en) | 2015-03-25 |
EP2741318B1 (en) | 2020-08-26 |
KR20140024460A (ko) | 2014-02-28 |
TW201330252A (zh) | 2013-07-16 |
KR101541656B1 (ko) | 2015-08-03 |
JP5303008B2 (ja) | 2013-10-02 |
US20140151886A1 (en) | 2014-06-05 |
TWI493706B (zh) | 2015-07-21 |
JP2013026308A (ja) | 2013-02-04 |
WO2013012050A1 (ja) | 2013-01-24 |
CN103733310B (zh) | 2016-08-17 |
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