CN103718286A - 热压键合期间用于保护tsv末端的保护层 - Google Patents

热压键合期间用于保护tsv末端的保护层 Download PDF

Info

Publication number
CN103718286A
CN103718286A CN201280037713.4A CN201280037713A CN103718286A CN 103718286 A CN103718286 A CN 103718286A CN 201280037713 A CN201280037713 A CN 201280037713A CN 103718286 A CN103718286 A CN 103718286A
Authority
CN
China
Prior art keywords
tsv
die
protective layer
bottom side
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201280037713.4A
Other languages
English (en)
Chinese (zh)
Inventor
J·A·韦斯特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN103718286A publication Critical patent/CN103718286A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207—Temporary substrates, e.g. removable substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/245—Dispositions, e.g. layouts of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/255—Materials of outermost layers of multilayered bumps, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
CN201280037713.4A 2011-06-01 2012-06-01 热压键合期间用于保护tsv末端的保护层 Pending CN103718286A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/150,899 US8623763B2 (en) 2011-06-01 2011-06-01 Protective layer for protecting TSV tips during thermo-compressive bonding
US13/150,899 2011-06-01
PCT/US2012/040388 WO2012167027A2 (en) 2011-06-01 2012-06-01 Protective layer for protecting tsv tips during thermo-compressive bonding

Publications (1)

Publication Number Publication Date
CN103718286A true CN103718286A (zh) 2014-04-09

Family

ID=47260364

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280037713.4A Pending CN103718286A (zh) 2011-06-01 2012-06-01 热压键合期间用于保护tsv末端的保护层

Country Status (5)

Country Link
US (2) US8623763B2 (https=)
EP (1) EP2783393A4 (https=)
JP (1) JP6038902B2 (https=)
CN (1) CN103718286A (https=)
WO (1) WO2012167027A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106211005A (zh) * 2014-08-08 2016-12-07 佳能株式会社 具有与贯通线连接的电极的设备及其制造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8970043B2 (en) * 2011-02-01 2015-03-03 Maxim Integrated Products, Inc. Bonded stacked wafers and methods of electroplating bonded stacked wafers
KR101916225B1 (ko) * 2012-04-09 2018-11-07 삼성전자 주식회사 Ｔｓｖ를 구비한 반도체 칩 및 그 반도체 칩 제조방법
US8907494B2 (en) 2013-03-14 2014-12-09 International Business Machines Corporation Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures
CN104810319A (zh) * 2014-01-28 2015-07-29 中芯国际集成电路制造(上海)有限公司 晶圆键合的方法
EP2908337B1 (en) * 2014-02-12 2025-11-12 ams AG Semiconductor device with a thermally stable bump contact on a TSV and method of producing such a semiconductor device
EP3167485A4 (en) 2014-07-11 2018-03-07 Intel Corporation Scalable package architecture and associated techniques and configurations
CN104502903B (zh) * 2014-11-28 2017-12-29 成都嘉纳海威科技有限责任公司 一种基于tsv转接板的多波束接收sip系统
WO2016154526A1 (en) * 2015-03-26 2016-09-29 Board Of Regents, The University Of Texas System Capped through-silicon-vias for 3d integrated circuits
KR102649471B1 (ko) 2016-09-05 2024-03-21 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11469194B2 (en) * 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
US11152333B2 (en) * 2018-10-19 2021-10-19 Micron Technology, Inc. Semiconductor device packages with enhanced heat management and related systems
WO2022147429A1 (en) 2020-12-28 2022-07-07 Invensas Bonding Technologies, Inc. Structures with through-substrate vias and methods for forming the same
CN116762163A (zh) 2020-12-28 2023-09-15 美商艾德亚半导体接合科技有限公司 具有贯穿衬底过孔的结构及其形成方法
US20250218903A1 (en) * 2023-12-28 2025-07-03 Adeia Semiconductor Bonding Technologies Inc. Via reveal processing and structures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7365436B2 (en) * 2004-11-08 2008-04-29 Shinko Electric Industries Co., Ltd. Substrate having a penetrating via and wiring connected to the penetrating via and a method for manufacturing the same
US20090321948A1 (en) * 2008-06-27 2009-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking devices
CN102054787A (zh) * 2010-10-21 2011-05-11 日月光半导体制造股份有限公司 堆栈式封装结构及其制造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0853337B1 (en) * 1996-07-12 2004-09-29 Fujitsu Limited Method for manufacturing semiconductor device
JP4151164B2 (ja) * 1999-03-19 2008-09-17 株式会社デンソー 半導体装置の製造方法
US6734532B2 (en) * 2001-12-06 2004-05-11 Texas Instruments Incorporated Back side coating of semiconductor wafers
US6713366B2 (en) * 2002-06-12 2004-03-30 Intel Corporation Method of thinning a wafer utilizing a laminated reinforcing layer over the device side
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
TWI309456B (en) * 2004-04-27 2009-05-01 Advanced Semiconductor Eng Chip package structure and process for fabricating the same
EP1742255B1 (en) * 2004-04-28 2012-10-31 Lintec Corporation Sheet peeling apparatus and peeling method
EP1949432B1 (en) * 2005-11-08 2017-10-18 Invensas Corporation Producing a covered through substrate via using a temporary cap layer
JP2007317822A (ja) * 2006-05-25 2007-12-06 Sony Corp 基板処理方法及び半導体装置の製造方法
KR20090075883A (ko) * 2006-10-31 2009-07-09 어드밴스드 마이크로 디바이시즈, 인코포레이티드 알루미늄 단자 금속층이 없는 금속화층 스택
KR100871382B1 (ko) * 2007-06-26 2008-12-02 주식회사 하이닉스반도체 관통 실리콘 비아 스택 패키지 및 그의 제조 방법
JP5159273B2 (ja) * 2007-11-28 2013-03-06 ルネサスエレクトロニクス株式会社 電子装置の製造方法
US7759212B2 (en) * 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
US8178976B2 (en) * 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
KR20100021856A (ko) * 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
US7687311B1 (en) * 2008-11-13 2010-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing stackable dies
US8097964B2 (en) 2008-12-29 2012-01-17 Texas Instruments Incorporated IC having TSV arrays with reduced TSV induced stress
TWI380421B (en) 2009-03-13 2012-12-21 Advanced Semiconductor Eng Method for making silicon wafer having through via
JP5563785B2 (ja) * 2009-05-14 2014-07-30 新光電気工業株式会社 半導体パッケージ及びその製造方法
US20100327465A1 (en) * 2009-06-25 2010-12-30 Advanced Semiconductor Engineering, Inc. Package process and package structure
US8313982B2 (en) * 2010-09-20 2012-11-20 Texas Instruments Incorporated Stacked die assemblies including TSV die
TWI429055B (zh) * 2010-10-07 2014-03-01 日月光半導體製造股份有限公司 堆疊式封裝結構及其製造方法
US8298944B1 (en) * 2011-06-01 2012-10-30 Texas Instruments Incorporated Warpage control for die with protruding TSV tips during thermo-compressive bonding

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7365436B2 (en) * 2004-11-08 2008-04-29 Shinko Electric Industries Co., Ltd. Substrate having a penetrating via and wiring connected to the penetrating via and a method for manufacturing the same
US20090321948A1 (en) * 2008-06-27 2009-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking devices
CN102054787A (zh) * 2010-10-21 2011-05-11 日月光半导体制造股份有限公司 堆栈式封装结构及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106211005A (zh) * 2014-08-08 2016-12-07 佳能株式会社 具有与贯通线连接的电极的设备及其制造方法

Also Published As

Publication number Publication date
EP2783393A2 (en) 2014-10-01
WO2012167027A2 (en) 2012-12-06
EP2783393A4 (en) 2016-03-23
US20120306085A1 (en) 2012-12-06
US8623763B2 (en) 2014-01-07
JP6038902B2 (ja) 2016-12-07
US20130249098A1 (en) 2013-09-26
JP2014517531A (ja) 2014-07-17
WO2012167027A3 (en) 2013-04-25
US8723330B2 (en) 2014-05-13

Similar Documents

Publication Publication Date Title
US12119320B2 (en) Chip package structure with bump
US8623763B2 (en) Protective layer for protecting TSV tips during thermo-compressive bonding
CN110970407B (zh) 集成电路封装件和方法
US8298944B1 (en) Warpage control for die with protruding TSV tips during thermo-compressive bonding
US11069539B2 (en) 3D packages and methods for forming the same
US8344493B2 (en) Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips
US11749651B2 (en) Semiconductor package and manufacturing method thereof
TWI397977B (zh) 積體電路結構及其形成方法
US9496189B2 (en) Stacked semiconductor devices and methods of forming same
US9570368B2 (en) Method of manufacturing semiconductor package including forming a recessed region in a substrate
CN107622982B (zh) 芯片封装结构及其制造方法
US9543242B1 (en) Semiconductor package and fabricating method thereof
CN102148203B (zh) 半导体芯片以及形成导体柱的方法
CN101060088B (zh) 半导体封装结构及其制造方法
US12002778B2 (en) Semiconductor packages and methods of forming the same
US10141291B2 (en) Semiconductor device and method of manufacturing the same
CN114765150A (zh) 金属化结构及封装结构
US20190139886A1 (en) Package structure and manufacturing method thereof
CN111564379A (zh) 芯片的封装方法及芯片结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20140409