CN103715265B - 薄膜晶体管、阵列基板和显示装置 - Google Patents

薄膜晶体管、阵列基板和显示装置 Download PDF

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CN103715265B
CN103715265B CN201310718480.0A CN201310718480A CN103715265B CN 103715265 B CN103715265 B CN 103715265B CN 201310718480 A CN201310718480 A CN 201310718480A CN 103715265 B CN103715265 B CN 103715265B
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semiconductor layer
grid
film transistor
thin film
grid line
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CN103715265A (zh
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刘翔
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BOE Technology Group Co Ltd
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Priority to US14/420,737 priority patent/US9423662B2/en
Priority to PCT/CN2014/073970 priority patent/WO2015096287A1/zh
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Abstract

本发明提供一种薄膜晶体管、阵列基板和显示装置，属于显示技术领域，其可解决现有的底栅型薄膜晶体管在制作过程中可能导致源漏电极金属与栅极金属发生短路的问题。本发明的薄膜晶体管包括：形成在衬底上方的栅极，所述栅极连接在栅线上；以及形成在所述栅极和栅线上方的半导体层；其中，所述半导体层至少部分超出所述栅极。本发明的阵列基板包括上述薄膜晶体管，所述显示装置包括上述阵列基板。本发明可提高底栅型薄膜晶体管的产品良率。

Description

薄膜晶体管、阵列基板和显示装置
技术领域
本发明属于显示技术领域，具体涉及一种薄膜晶体管、阵列基板和显示装置。
背景技术
薄膜晶体管液晶显示器（ThinFilmTransistorLiquidCrystalDisplay，简称TFT-LCD）因具有体积小、功耗低、无辐射等特点而深受市场欢迎。其中，金属氧化物TFT迁移率高，均一性好，透明，制作工艺简单，能够更好地满足大尺寸、高刷新频率的薄膜晶体管液晶显示器的发展要求。
结合图1～3所示，现有技术中在制作金属氧化物TFT过程中，为防止在刻蚀源漏金属电极时腐蚀掉金属氧化物半导体层，一般在金属氧化物半导体层上面增加一层刻蚀阻挡层，保护金属氧化物半导体层不被源漏金属的刻蚀液腐蚀。刻蚀阻挡层一般采用接触过孔设计。图1示出了现有技术中的一种栅极11和半导体层2的位置和大小关系，半导体层2下方是栅极11（半导体层2和栅极11之间有栅绝缘层，栅绝缘层在图1和图2中未示出），在垂直于栅线12的方向（如图1中BB方向）上，半导体层2比栅极11小，在平行于栅线方向（如图1中AA方向）上，半导体层2与栅极11齐平。如图2和图3所示，栅极11上方为栅绝缘层6，栅绝缘层6上形成有有源层2，其上沉积有刻蚀阻挡层5，刻蚀阻挡层5包括源电极接触过孔3和漏电极接触过孔4，通过接触过孔3、4，源电极和漏电极分别与有源层实现电连接。
在实现本发明的过程中，发明人发现现有技术中至少存在如下问题：由于对位精度要求很高，而现有工艺达到的精度有限以及半导体层比栅极小，故对刻蚀阻挡层的源电极和漏电极的接触过孔进行刻蚀时可能会偏出半导体层而到达无半导体层的栅极上方，从而会继续刻蚀掉栅极绝缘层，导致源电极或漏电极金属与栅极金属短路，降低了产品的良率。
发明内容
本发明所要解决的技术问题包括，针对现有的采用底栅型薄膜晶体管的阵列基板刻蚀源电极和漏电极的接触过孔时可能导致源电极或漏电极金属与栅极金属短路的问题，提供一种薄膜晶体管、阵列基板和显示装置，其能有效解决上述源电极或漏电极金属与栅极金属短路的问题从而提高产品良率。
解决本发明技术问题所采用的技术方案是一种薄膜晶体管，包括：
形成在衬底上方的栅极，所述栅极连接在栅线上；
形成在所述栅极和栅线上方的半导体层；
所述半导体层至少部分超出所述栅极。
优选的是，所述半导体层在垂直于所述栅线的方向上超出所述栅极。
进一步优选的是，所述半导体层在远离栅线的一侧超出所述栅极，且半导体层在远离所述栅线一侧的中间部分向靠近栅线的方向凹进，且与所述栅极边缘齐平。
更进一步优选的是，所述半导体层在靠近栅线的一侧超出所述栅极，且半导体层在靠近所述栅线一侧的中间部分向远离栅线的方向凹进以露出部分所述栅极。
进一步优选的是，所述半导体层在远离栅线的一侧超出所述栅极，且半导体层在远离所述栅线一侧的中间部分向靠近栅线的方向凹进以露出部分所述栅极。
更进一步优选的是，所述半导体层在靠近栅线的一侧超出所述栅极，且半导体层在靠近所述栅线一侧的中间部分向远离栅线的方向凹进以露出部分所述栅极。
进一步优选的是，所述半导体层在靠近栅线的一侧超出所述栅极，且半导体层在靠近所述栅线一侧的中间部分向远离栅线的方向凹进以露出部分所述栅极。
优选的是，所述半导体层在平行于栅线的方向超出所述栅极。
优选的是，所述薄膜晶体管还包括覆盖所述半导体层的刻蚀阻挡层，所述刻蚀阻挡层包括位于半导体层上方的漏电极的接触过孔和源电极的接触过孔，所述源电极的接触过孔和漏电极的接触过孔与半导体层接触形成接触部，每个所述接触部的边缘到半导体层的边缘至少有4微米的距离。
优选的是，所述薄膜晶体管还包括覆盖所述半导体层的刻蚀阻挡层，所述刻蚀阻挡层包括位于半导体层上方的漏电极的接触过孔和源电极的接触过孔，所述源电极的接触过孔和漏电极的接触过孔与半导体层接触形成接触部，每个所述接触部的边缘到半导体层的边缘至少有4微米的距离。
优选的是，所述半导体层的材料为金属氧化物半导体或石墨烯半导体。
优选的是，所述半导体层的厚度范围为
本发明的薄膜晶体管的半导体层至少部分超出栅极，因此，当对刻蚀阻挡层的源电极和漏电极的接触过孔进行刻蚀时，即使接触过孔的位置与设计要求的位置有所偏出，但由于半导体层至少部分超出栅极，这样偏出的接触过孔与栅极间仍有半导体层存在，半导体层就起到了阻挡层的作用，栅绝缘层就不会被刻蚀而厚度变薄甚至栅绝缘层被刻蚀掉，从而既能够避免栅绝缘层被静电击穿，又能够有效地解决源电极或漏电极金属与栅极金属短路的问题，进而可以较大幅度地提升薄膜晶体管的良品率。
解决本发明技术问题所采用的技术方案是一种阵列基板，所述阵列基板包括上述的薄膜晶体管。
本发明的阵列基板包括上述薄膜晶体管，因此阵列基板的良品率得到了进一步的提高。
解决本发明技术问题所采用的技术方案是一种显示装置，所述显示装置包括上述阵列基板。
本发明的显示装置包括上述阵列基板，阵列基板的良品率的提高进而降低了显示装置的生产成本。
附图说明
图1为现有技术中一种阵列基板的栅极和半导体层的平面示意图；
图2为现有技术中一种阵列基板的源电极接触过孔和漏电极接触过孔在半导体层上的位置和大小的平面示意图；
图3为图2中C-C方向的剖面图；
图4为本发明的实施例1的半导体层在垂直栅线方向超出栅极的阵列基板的平面示意图；
图5为本发明的实施例1的半导体层在垂直栅线方向超出栅极的另一种阵列基板的平面示意图；
图6为本发明的实施例1的半导体层在垂直栅线方向超出栅极的第三种阵列基板的平面示意图；
图7为本发明的实施例1的半导体层在平行于栅线方向超出栅极的阵列基板的平面示意图；
图8为本发明的实施例1的半导体层在垂直栅线方向和平行于栅线方向同时超出栅极的阵列基板的平面示意图；
图9为图8中D-D方向的剖面图；
其中附图标记为：11、栅极；12、栅线；2、半导体层；3、源电极接触过孔；4、漏电极接触过孔；5、刻蚀阻挡层；6、栅绝缘层。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
如图4至图9所示，本实施例提供一种薄膜晶体管，其包括形成在衬底上方的栅极11和栅线12，栅极11连接在栅线12上，覆盖栅极11和栅线12的栅绝缘层6，形成在栅绝缘层6上方的半导体层2，覆盖半导体层2的刻蚀阻挡层5，刻蚀阻挡层5包括位于半导体层2上方的漏电极接触过孔4和源电极接触过孔3；其中，半导体层2至少部分超出栅极11。当然，薄膜晶体管还包括如钝化层等其他已知的结构，在此不再详细描述。
其中，栅极11和栅线12的材料可以采用金属Cr、W、Ti、Ta、Mo、Al、Cu等金属中的一种或其合金，也可以采用多层金属组成的栅金属层作为栅极材料。
优选的，栅绝缘层的厚度在间。栅绝缘层也可以采用两层栅绝缘层的结构。栅绝缘层材料可以选用氧化物、氮化物或者氧氮化合物。当然栅极绝缘层也不局限于上述厚度与上述材料，其也可以根据实际需要具体设置。
优选的，半导体层2的材料为金属氧化物半导体或石墨烯半导体。
需要说明的是，半导体层2的材料为金属氧化物时，其材料可以是包含铟（In）、镓（Ga）、锌（Zn）、氧（O）、锡（Sn）等元素，且其中必须包含氧元素和前述的两种或两种以上的元素，具体的可以进一步优选的，金属氧化物为IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb和Cd-Sn-O中的一种。
在刻蚀源电极和漏电极接触过孔3、4时由金属氧化物半导体或石墨烯半导体构成的半导体层2不易被刻蚀液刻蚀，因此半导体层2就起到了阻挡层的作用。
优选的，由石墨烯半导体或上述金属氧化物中的一种构成的半导体层2的厚度在间，上述厚度的半导体层2足以起到阻挡层的作用，从而能够防止半导体层2下方的栅绝缘层被刻蚀。
本实施例中的薄膜晶体管，其半导体层2至少部分超出栅极11包括以下几种情形。
优选的，如图4至图6所示，半导体层2在垂直于栅线12方向上超出栅极11，此种情形下，由于半导体层2超出栅极11，在刻蚀源电极接触过孔3和漏电极接触过孔4的过程中，能避免源电极的接触过孔3和漏电极的接触过孔4在垂直栅线12方向上偏出半导体层2，从而也就不会刻蚀掉栅绝缘层6，进而有效地解决了源电极或漏电极金属与栅极金属短路的问题。
进一步优选的，如图4所示，半导体层2在远离栅线12的一侧超出所述栅极11，且半导体层2在远离栅线12一侧的中间部分向靠近栅线12方向凹进到与栅极边缘齐平。这样，有了上述凹进的设计后，半导体层2超出栅极11的部分在背光源的光线照射下源极和漏极就不会发生导通的情况，从而避免薄膜晶体管失效。
可以理解的是，只要半导体层2超出栅极11的中间部分不导电，即可避免薄膜晶体管失效。而半导体层2的两侧分别用于连接源极和漏极，即使受到光照导电也无关，故只需半导体层2的超出栅极11中间部分向靠近栅线12的方向凹进即可。
更优选的，如图5所示，半导体层2在远离栅线12的一侧超出栅极11，且半导体层2在远离栅线12一侧的中间部分向靠近栅线12方向凹进以露出部分所述栅极。此种情形下半导体层2与栅极11的正对面积变小，使得半导体层2与栅极11之间的寄生电容变小，从而减少了对薄膜晶体管性能的不良影响。
更进一步优选的，如图6所示，半导体层2在靠近栅线12的一侧超出栅极11，且半导体层2在靠近栅线12方向的下部中间部分向远离栅线12方向凹进以露出部分所述栅极。此种情形下，半导体层2与栅极11的正对面积变得更小，从而使得半导体层2与栅极11之间的寄生电容进一步变小，进而更进一步地减少了对薄膜晶体管性能的不良影响。
需要说明的是，前述半导体层2在垂直栅线12的方向远离栅线12的一侧和/或靠近栅线12的一侧有凹进的设计。在栅线方向上，漏电极的接触过孔4和源电极的接触过孔3与半导体层接触的位置分别位于上述凹进两侧，所以半导体层2在平行于栅线12的方向的两侧就不能进行凹进设计，否则半导体层2就起不到阻挡层的作用了。
优选的，如图7所示，半导体层2在平行于栅线12的方向超出栅极11。刻蚀源电极接触过孔3和漏电极接触过孔4过程中，如果接触过孔的位置在平行于栅线方向上偏出半导体层2，将导致偏出半导体层2的接触过孔3、4处的下方的栅绝缘层被刻蚀从而厚度变薄甚至被完全刻蚀掉，这样通电时将会出现栅绝缘层被静电击穿甚至导致源电极或漏电极金属与栅极金属短路的情况。半导体层2在平行于栅线12方向上超出栅极11则可以有效避免上述情况的发生。
需要说明的是，对半导体层2的上述几种情形进行组合，可以使半导体层2形成不同的形状，显然，包括上述不同形状的半导体层的薄膜晶体管属于本发明的保护范围。比如经过组合可以使得半导体层2既在垂直栅线12的方向又在平行于栅线12的方向超出栅极11，并且使得半导体层2既在远离栅线12方向的一侧中间部分向靠近栅线12方向凹进又在靠近栅线12方向的一侧的中间部分向远离栅线12方向凹进，其平面图如图8所示，剖面图如图9所示。
本实施例中，优选的，源电极的接触过孔3和漏电极的接触过孔4与半导体层2接触形成接触部，每个接触部的边缘到半导体层2的边缘至少有4微米距离。也就是说，接触过孔3或4与半导体层2接触而形成接触部，接触部的形状就是接触过孔3或4的形状，该接触部的边缘距离半导体层2的边缘的距离至少为4微米，以满足现有的工艺精度的要求。
本实施例中的薄膜晶体管的半导体层2至少部分超出栅极11，对刻蚀阻挡层5的源电极和漏电极的接触过孔进行刻蚀时，即使过孔的位置与设计要求的位置有所偏出，但由于半导体层2至少部分超出栅极11，这样半导体层2就起到了阻挡层的作用，栅极绝缘层就不会被被刻蚀，从而能够有效地解决源电极或漏电极金属与栅极金属发生短路的问题，进而可以较大幅度地提升薄膜晶体管的良品率。
本实施例还提供上述薄膜晶体管的制作方法，结合图4至图9，包括如下步骤：
在衬底上形成栅金属薄膜，通过构图工艺形成包括栅极11和栅线12的图形，所述栅极11连接在栅线12上。
其中，上述形成薄膜通常有沉积、涂敷、溅射等多种方式，上述的构图工艺通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。
其中，上述衬底可以是玻璃基板、石英基板等基于无机材料的衬底基板，也可以是采用有机材料的基板；
在形成有栅极11和栅线12的基板上沉积栅绝缘层6，然后沉积有源层，通过构图工艺形成半导体层2的图形，其中，半导体层2至少部分超出栅极11；
在半导体层2上沉积刻蚀阻挡层5，通过构图工艺形成至少包括漏电极的接触过孔4和源电极的接触过孔3。
当然，本实施例中的薄膜晶体管的制作方法，还应当包括如源漏电极、钝化层等已知结构的制作步骤，在此不再详细描述。
本实施例提供的薄膜晶体管的制作方法，该方法制备的薄膜晶体管能有效避免源电极或漏电极金属与栅极金属短路，从而提高了薄膜晶体管的产品良率。
实施例2：
本实施例提供一种阵列基板，阵列基板包括实施例1中的薄膜晶体管，还包括如像素电极等已知的结构，在此不再详细描述。
本实施例的阵列基板包括实施例1中的薄膜晶体管，其能够有效地避免源电极或漏电极金属与栅极金属短路的问题。因此，阵列基板的良品率也得到了进一步的提高。
实施例3：
本实施例提供一种显示装置，显示装置包括实施例2中的阵列基板，当然还包括如彩膜基板等已知的结构。显示装置可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置包括上述阵列基板，由于阵列基板的良品率提高进而降低了显示装置的生产成本。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (9)

1.一种薄膜晶体管，包括：
形成在衬底上方的栅极，所述栅极连接在栅线上；
形成在所述栅极和栅线上方的半导体层；
其特征在于，
所述半导体层在垂直于所述栅线的方向上超出所述栅极；
所述半导体层在远离栅线的一侧超出所述栅极，且半导体层在远离所述栅线一侧的中间部分向靠近栅线的方向凹进，且与所述栅极边缘齐平，或者，所述半导体层在远离栅线的一侧超出所述栅极，且半导体层在远离所述栅线一侧的中间部分向靠近栅线的方向凹进以露出部分所述栅极；
所述薄膜晶体管还包括覆盖所述半导体层的刻蚀阻挡层，所述刻蚀阻挡层包括位于半导体层上方的漏电极的接触过孔和源电极的接触过孔，所述源电极的接触过孔和漏电极的接触过孔与半导体层接触形成接触部。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述半导体层在靠近栅线的一侧超出所述栅极，且半导体层在靠近所述栅线一侧的中间部分向远离栅线的方向凹进以露出部分所述栅极。
3.根据权利要求1至2任意一项所述的薄膜晶体管，其特征在于，所述半导体层在平行于栅线的方向超出所述栅极。
4.根据权利要求1至2任意一项所述的薄膜晶体管，其特征在于，每个所述接触部的边缘到半导体层的边缘至少有4微米的距离。
5.根据权利要求3所述的薄膜晶体管，其特征在于，每个所述接触部的边缘到半导体层的边缘至少有4微米的距离。
6.根据权利要求1所述的薄膜晶体管，其特征在于，所述半导体层的材料为金属氧化物半导体或石墨烯半导体。
7.根据权利要求1所述的薄膜晶体管，其特征在于，所述半导体层的厚度范围为
8.一种阵列基板，其特征在于，所述阵列基板包括如权利要求1至7中任意一项所述的薄膜晶体管。
9.一种显示装置，其特征在于，所述显示装置包括如权利要求8所述的阵列基板。
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