CN103681838A - 一种肖特基mos半导体装置及其制备方法 - Google Patents
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Abstract
本发明提出一种肖特基MOS半导体装,将肖特基势垒结代替传统MOS器件的源区和体区,通过栅极偏压在漂移区形成高浓度的载流子区域,形成器件的沟道;同时本发明将电荷补偿结构引入到肖特基MOS结构中。本发明还提供一种肖特基MOS半导体装置的制备方法。
Description
技术领域
本发明主要涉及到一种肖特基MOS半导体装置,本发明还涉及一种肖特基MOS半导体装置的制备工艺。
背景技术
具有肖特基结构和超结结构的半导体器件,已成为器件发展的重要趋势。对于功率半导体器件,不断降低导通电阻和不断提高电流密度的要求成为器件发展的重要趋势。
传统MOS器件具有栅氧,栅氧表面设置有多晶硅,器件表面半导体材料依次设置有源区、体区和漏区,器件开通状态下的导通电阻主要受到漂移层电阻和沟导电阻的影响。
发明内容
本发明提出一种肖特基MOS半导体装置及其制备方法。
一种肖特基MOS半导体装置,其特征在于:包括:衬底层,为半导体材料;漂移层,为第一传导类型的半导体材料,位于衬底层之上;栅绝缘层,为绝缘材料,位于漂移层表面;栅电极,多晶半导体材料或金属,位于栅绝缘层上表面;肖特基势垒结,位于漂移层表面,与栅绝缘层交替排列;沟道区,为漂移层中临靠栅绝缘层和肖特基势垒结的第一传导类型的半导体材料。
一种肖特基MOS半导体装置的制备方法,其特征在于:包括如下步骤:在衬底层上通过外延生产形成第一传导类型的半导体材料漂移层;在表面形成绝缘层,淀积多晶半导体材料,光刻腐蚀去除部分多晶半导体材料,淀积绝缘材料;光刻腐蚀去除部分绝缘材料,淀积势垒金属,形成肖特基势垒结。
本发明的一种肖特基MOS半导体装置,将肖特基势垒结代替传统MOS器件的源区和体区,通过栅极偏压在漂移区形成高浓度的载流子区域,形成器件的沟道;同时本发明将电荷补偿结构引入到肖特基MOS结构中。
附图说明
图1为本发明一种肖特基MOS半导体装置剖面示意图;
图2为本发明第二种肖特基MOS半导体装置剖面示意图;
图3为本发明第三种肖特基MOS半导体装置剖面示意图;
图4为本发明第四种肖特基MOS半导体装置剖面示意图;
图5为本发明第五种肖特基MOS半导体装置剖面示意图。
其中,1、衬底层;2、漂移层;3、肖特基势垒结;4、沟道区;5、栅氧化层;6、P型单晶半导体材料;7、栅极N型多晶半导体材料;8、一氧化硅;9、三氧化二铝;10、掺氧多晶硅。
具体实施方式
实施例1
图1示出了本发明一种沟槽肖特基MOS半导体装置剖面示意图,下面结合图1详细说明通过本发明的一种沟槽肖特基MOS半导体装置。
一种沟槽肖特基MOS半导体装置包括:衬底层1,为N导电类型半导体硅材料,磷原子掺杂浓度为1E19cm-3;漂移层2,位于衬底层1之上,为N传导类型的半导体硅材料,磷原子掺杂浓度为1E16cm-3,厚度为38um;肖特基势垒结3,位于漂移层2表面;沟道区4,临靠肖特基势垒结3;栅氧化层5,为硅材料的氧化物,位于漂移层2表面,厚度为0.2um;栅极N型多晶半导体材料7,位于栅氧化层5表面,为高浓度杂质掺杂的多晶半导体材料。
本实施例的工艺制造流程如下:
第一步,在衬底层1上通过外延生产形成漂移层2;
第二步,在表面热氧化形成栅氧化层5,淀积N型多晶半导体材料形成栅极N型多晶半导体材料7,进行光刻腐蚀,去除部分栅极N型多晶半导体材料7和栅氧化层5;
第三步,淀积势垒金属烧结形成肖特基势垒结3,如图1所示。
在此基础上淀积电极金属,光刻腐蚀工艺腐蚀去除部分电极金属,为器件引出肖特基上表面的源极和栅极N型多晶半导体材料7表面的栅极,然后在此基础上,通过背面金属化工艺为器件引出漏极。
实施例2
图2示出了本发明第二种肖特基MOS半导体装置剖面示意图,下面结合图2详细说明通过本发明的半导体装置。
一种肖特基MOS半导体装置包括:衬底层1,为N导电类型半导体硅材料,磷原子掺杂浓度为1E19cm-3;漂移层2,位于衬底层1之上,为N传导类型的半导体硅材料,磷原子掺杂浓度为1E16cm-3,厚度为38um;肖特基势垒结3,位于漂移层2表面;沟道区4,临靠肖特基势垒结3;栅氧化层5,为硅材料的氧化物,位于漂移层2表面;栅极N型多晶半导体材料7,位于栅氧化层5表面,为高浓度杂质掺杂的多晶半导体材料;P型单晶半导体材料6,位于栅氧化层5下部,为P传导类型的半导体硅材料,硼原子掺杂浓度为1E16cm-3,厚度为33um。
本实施例的工艺制造流程如下:
第一步,在衬底层1上通过外延生产形成漂移层2;
第二步,在表面热氧化形成栅氧化层5,在待形成沟槽区域表面去除氧化层5;
第三步,进行干法刻蚀,去除半导体材料,形成沟槽;
第四步,淀积P型单晶半导体材料6,反刻蚀P型单晶半导体材料6;
第五步,进行热氧化,然后在沟槽内淀积形成栅极N型多晶半导体材料7;
第六步,光刻腐蚀,去除部分栅极N型多晶半导体材料7和栅氧化层5;
第七步,淀积势垒金属烧结形成肖特基势垒结3,如图2所示。
在此基础上淀积电极金属,光刻腐蚀工艺腐蚀去除部分电极金属,为器件引出肖特基上表面的源极和栅极N型多晶半导体材料7表面的栅极,然后在此基础上,通过背面金属化工艺为器件引出漏极。
图3实例,为在图2器件制造的基础上,将一氧化硅8材料设置在栅氧化层5底部。
图4实例,为在图2器件制造的基础上,将三氧化二铝9材料设置在栅氧化层5底部。
图5实例,为在图2器件制造的基础上,将掺氧多晶硅10材料设置在栅氧化层5底部。
通过上述实例阐述了本发明,同时也可以采用其它实例实现本发明,本发明不局限于上述具体实例,因此本发明由所附权利要求范围限定。
Claims (10)
1.一种肖特基MOS半导体装置,其特征在于:包括:
衬底层,为半导体材料;
漂移层,为第一传导类型的半导体材料,位于衬底层之上;
栅绝缘层,为绝缘材料,位于漂移层表面;
栅电极,多晶半导体材料或金属,位于栅绝缘层上表面;
肖特基势垒结,位于漂移层表面,与栅绝缘层交替排列;
沟道区,为漂移层中临靠栅绝缘层和肖特基势垒结的第一传导类型的半导体材料。
2.如权利要求1所述的半导体装置,其特征在于:所述的栅电极的多晶半导体材料可以为第一传导类型的多晶半导体材料,并且为高浓度杂质掺杂。
3.如权利要求1所述的半导体装置,其特征在于:所述的肖特基势垒结表面电极可以作为器件的源极。
4.如权利要求1所述的半导体装置,其特征在于:所述的栅绝缘层底部可以添加条状的第二传导类型的半导体材料,形成电荷补偿结构,当器件接反向偏压时,形成电荷补偿,从而实现电场相对均匀分布。
5.如权利要求1所述的半导体装置,其特征在于:所述的栅绝缘层底部可以添加条状的掺氧多晶硅材料,从而可以与漂移层中第一传导类型的半导体材料形成电荷补偿结构。
6.如权利要求1所述的半导体装置,其特征在于:所述的栅绝缘层底部可以添加条状的绝缘材料,同时绝缘材料界面具有较高的界面态,从而可以与漂移层中第一传导类型的半导体材料形成电荷补偿结构。
7.如权利要求1所述的半导体装置,其特征在于:所述的栅绝缘层底部可以添加条状的化学配比失配绝缘材料,其化合物元素配比为非饱和状态,从而可以与漂移层中第一传导类型的半导体材料形成电荷补偿结构。
8.如权利要求1所述的层结构,其特征在于:所述的沟槽底部绝缘层厚度可以大于沟槽侧壁的绝缘层厚度。
9.如权利要求1所述的层结构,其特征在于:所述的衬底层可以为较薄的第二传导类型的半导体材料。
10.如权利要求1所述的一种肖特基MOS半导体装置的制备方法,其特征在于:包括如下步骤:
1)在衬底层上通过外延生产形成第一传导类型的半导体材料漂移层;
2)在表面形成绝缘层,淀积多晶半导体材料,光刻腐蚀去除部分多晶半导体材料和绝缘材料;
3)淀积势垒金属,形成肖特基势垒结。
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Patent Citations (5)
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US20010046744A1 (en) * | 1999-01-13 | 2001-11-29 | Brian S. Doyle | Transistor with reduced series resistance junction regions |
CN201038163Y (zh) * | 2007-03-30 | 2008-03-19 | 东南大学 | 沟槽高压p型金属氧化物半导体管 |
CN101807597A (zh) * | 2010-04-02 | 2010-08-18 | 中国电子科技集团公司第五十五研究所 | 一种自对准亚微米栅结构及其制作方法 |
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