CN103633031A - Forming method of semiconductor apparatus - Google Patents
Forming method of semiconductor apparatus Download PDFInfo
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- CN103633031A CN103633031A CN201210306872.1A CN201210306872A CN103633031A CN 103633031 A CN103633031 A CN 103633031A CN 201210306872 A CN201210306872 A CN 201210306872A CN 103633031 A CN103633031 A CN 103633031A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
The embodiment of the invention provides a forming method of a semiconductor apparatus. The forming method comprises the following steps: providing a substrate; forming a grid dielectric layer, a grid material layer, an oxidation barrier layer, and a hard mask curtain layer sequentially at the substrate; carrying out etching on the hard mask curtain layer, the oxidation barrier layer, the grid material layer, the grid dielectric layer, and the substrate sequentially so as to form a groove in the substrate; filling the groove with an oxide layer; carrying out etchback on the oxide layer in the groove to reduce the height of the oxide layer; removing the hard mask curtain layer and protecting the grid material layer under the oxidation barrier layer by the oxidation barrier layer during the removing process, and removing the oxidation barrier layer to expose the grid material layer.
Description
Technical field
Present invention is directed to the formation method of semiconductor structure, and particularly relevant for a kind of, utilize resistance to hinder oxide skin(coating) as the formation method of the semiconductor structure of protective layer.
Background technology
Flash memory device (Flash Memory) is that a kind of power consumption that do not need just can be preserved the nonvolatile memory device of data, and it can repeatedly delete or write in operating process.In addition, compared to other storage arrangements, flash memory has lower delay, the dynamic shock resistance and have significant speed advantage while writing great mass of data preferably of reading, therefore be often applied to general data storage, and exchange data transmission between computer and other numerical digit products, as memory card and Portable disk.
In addition, another advantage of flash memory is for the cost of manufacturing is lower, therefore flash memory has become the most important technology of also the most widely adopting of non-volatile solid-state storage at present, such as can be applicable in the Related products such as notebook computer, numerical digit walkman, digital still camera, mobile phone, game host.
For not b gate flash memory (NAND fash memory), mainly focus on the charge storage capacity of floating grid.In addition,, in semi-conductive manufacturing process, along with the reduction of memory-size, the usefulness of floating grid also comes into one's own more.In the manufacturing process of general floating grid, hard cover screen remove the infringement that can cause grid polycrystalline silicon, and cause the reduction of gate performance.On the other hand, the pointed shape of grid rectangle may have the problem of point discharge.
Therefore, need at present a kind of semiconductor fabrication process of novelty badly, can promote the usefulness of floating grid.
Summary of the invention
One embodiment of the invention provides a kind of formation method of semiconductor device, comprising: a substrate is provided, sequentially forms a gate dielectric, a gate material layers, resistance barrier oxide layer and a curtain layer of hard hood on this substrate; Sequentially this curtain layer of hard hood of etching, this resistance hinders oxide layer, this gate material layers, this gate dielectric and this substrate, to form a groove in this substrate; In this groove, insert monoxide layer; This oxide skin(coating) in this groove of etchback, to reduce the height of this oxide skin(coating); Remove this curtain layer of hard hood, and remove in step with this its this lower gate material layers of resistance barrier protect oxide layer at this; And remove this resistance barrier oxide layer, and expose this gate material layers.
For the present invention's above and other object, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and coordinate appended graphicly, be described in detail below:
Accompanying drawing explanation
Fig. 1 is presented at the flow chart of formation method of the semiconductor device of one embodiment of the invention.
Fig. 2 to Figure 13 shows the profile in each fabrication stage according to the formed semiconductor device of the method for Fig. 1 in one embodiment.
Main element symbol description:
102,104,106,108,110,112 ~ step;
200 ~ substrate;
202 ~ gate dielectric;
204 ~ gate material layers;
206 ~ resistance barrier oxide layer;
208 ~ curtain layer of hard hood;
210 ~ patterning photoresist layer;
212 ~ groove;
214 ~ oxide skin(coating);
The residual fraction of 216 ~ oxide skin(coating);
220 ~ control grid layer.
Embodiment
According to the present invention's different characteristic, enumerate several different embodiment below.In the present invention, specific element and arrangement have been simplification, but the present invention is not limited with these embodiment.For example, the description that forms the first element on the second element can comprise the embodiment that the first element directly contacts with the second element, also comprises and has the embodiment that extra element is formed between the first element and the second element, the first element is not directly contacted with the second element.In addition, for simplicity's sake, the present invention is component symbol and/or the letter representation to repeat in different examples, but does not represent between described each embodiment and/or structure to have specific relation.
Fig. 1 shows in an embodiment of the present invention, forms the method flow diagram of semiconductor device.In step 102, substrate is provided, and on substrate, sequentially form gate dielectric, gate material layers, resistance barrier oxide layer and curtain layer of hard hood.In step 104, sequentially etching curtain layer of hard hood, resistance hinders oxide layer, gate material layers, gate dielectric and substrate, to form a groove in substrate.In step 106, in groove, insert oxide skin(coating).In step 108, the oxide skin(coating) in etchback groove, to reduce the height of this oxide skin(coating).In step 110, remove curtain layer of hard hood, and with resistance, hinder its lower gate material layers of protect oxide layer in removing step.In step 112, remove resistance barrier oxide layer, and expose gate material layers.
Fig. 2 to Figure 11 shows the profile in each fabrication stage according to the formed semiconductor device of the method for Fig. 1 in one embodiment.For clearer, easy understanding concept of the present invention, Fig. 2 to Figure 11 is through simplifying.In certain embodiments, can in semiconductor device, can increase extra element, in other embodiments, some elements in following semiconductor device can be substituted or remove.
With reference to Fig. 2, substrate 200 is provided, and forms gate dielectric 202 on substrate 200.In one embodiment, substrate 200 comprises silicon substrate, sige substrate or semiconductor on insulator (semiconductor-on-insulator) substrate.Gate dielectric 202 can comprise that dielectric material is as silica, high-k dielectric materials, other applicable dielectric materials or aforementioned combination.In one embodiment, gate dielectric 202 can be the passage oxide skin(coating) (tunnel oxide layer) that utilizes thermal oxidation manufacturing process to form.In another embodiment, also can utilize the additive methods such as chemical vapour deposition (CVD) (CVD), ald (ALD) to form gate dielectric 202.
With reference to Fig. 3, on gate dielectric 202, form gate material layers 204.In one embodiment, gate material layers 204 comprises polysilicon layer.The formation of gate material layers 204 can utilize deposit manufacture technique, for example chemical vapour deposition (CVD) (CVD).
With reference to Fig. 4, in gate material layers 204, form resistance barrier oxide layer 206.Resistance barrier oxide layer 206 can comprise silica, silicon oxynitride, aluminium oxide, lanthana, hafnium oxide, zirconia, nitrogen hafnium oxide or aforementioned combination.Resistance barrier oxide layer 206 can utilize any applicable manufacturing process to form, such as thermal oxidation method, chemical vapour deposition (CVD), spin coating etc.In one embodiment, the formation of resistance barrier oxide layer 206 can be the silicon oxide dielectric layer of growing up in gate material layers 204 (silicon oxide dielectric).
With reference to Fig. 5, in resistance barrier oxide layer 206, form curtain layer of hard hood 208.Curtain layer of hard hood 208 can comprise silicon nitride layer or other applicable hard cover screen materials.The formation of curtain layer of hard hood 208 can utilize deposit manufacture technique, for example chemical vapour deposition (CVD) (CVD).
With reference to Fig. 6, on curtain layer of hard hood 208, form patterning photoresist layer 210.The formation of patterning photoresist layer 210 can utilize photoresist and the method for any known or future development.With reference to Fig. 7, utilize patterning photoresist layer 210 for cover curtain, sequentially etching curtain layer of hard hood 208, resistance hinders oxide layer 206, gate material layers 204, gate dielectric 202 and substrate 200, to form groove 212 in substrate 200.Above-mentioned etching manufacturing process can comprise dry etching, as electricity slurry etching or reactive ion etching.
With reference to Fig. 8, after forming groove 212, the structure of Fig. 7 is carried out cleaning after ashing, and remove patterning photoresist layer 210.With reference to Fig. 9, in groove 212, insert oxide skin(coating) 214, make oxide skin(coating) 214 on the whole fill up groove 212.Oxide skin(coating) 214 is for example silicon dioxide.The formation of oxide skin(coating) 214 can utilize thermal oxidation method, for example, under 900 ° of C to 1050 ° of C, react 14 seconds to 22 seconds.It should be noted, in forming the process of oxide skin(coating) 214, the corner of gate material layers 204 can be oxidized in the lump, and form the corner of circular arc.
With reference to Figure 10, the oxide skin(coating) 214 in etchback groove 212, to reduce the height of oxide skin(coating) 214.In one embodiment, the upper surface of oxide skin(coating) 214 can be on the whole between the upper and lower surface of gate material layers 204.With reference to Figure 11, remove curtain layer of hard hood 208, and utilize the gate material layers 204 of resistance barrier oxide layer 206 its belows of protection.In one embodiment, can utilize wet etching erosion manufacturing process to remove curtain layer of hard hood 208, for example, utilize hot phosphoric acid etching.Then, then remove resistance barrier oxide layer 206, and expose gate material layers 204, as shown in figure 12.In traditional manufacturing process, when removing curtain layer of hard hood with hot phosphoric acid etching, can directly expose gate material layers, now hot phosphoric acid can prolong in the lattice infiltration gate material layers of gate material layers (as polysilicon layer), and formed element efficiency is suffered damage.Yet, in this embodiment, be to utilize extra resistance barrier oxide layer 206 protection gate material layers 204 not to be subject to the infringement of hot phosphoric acid, then can not damage the manufacturing process of gate material layers 204, remove resistance barrier oxide layer 206 again.The method that removes resistance barrier oxide layer 206 for example comprises buffer oxide etching (buffered oxide etch; BHF).
It should be noted, when the oxide skin(coating) 214 that Fig. 9 formed is carried out to etchback step, a part 216 for oxide skin(coating) 214 still can remain on the sidewall of groove 212, as shown in figure 10.Therefore,, after removing curtain layer of hard hood 208, generally need utilize another etching manufacturing process to remove the residual fraction 216 of oxide skin(coating).In this embodiment, can utilize single etching manufacturing process, remove the residual fraction 216 of resistance barrier oxide layer 206 and oxide skin(coating) simultaneously.That is resistance barrier oxide layer 206 not only can be protected gate material layers 204 in removing the etching manufacturing process of curtain layer of hard hood 208, and can remove in the lump in the etch step of residual fraction 216 that removes oxide skin(coating), and does not need extra manufacturing technology steps.In a preferred embodiment, on the whole the thickness that oxide skin(coating) 214 remains in the part 216 of sidewall equal the thickness that resistance hinders oxide layer 206.For example, the thickness of resistance barrier oxide layer 206 can be between 5nm to 10nm.
With reference to Figure 12, remove the corner that the gate material layers 204 exposing after resistance barrier oxide layer 206 has circular arc.The ill effect of formed element point discharge (point discharge) in follow-up manufacturing process can be avoided in the corner of this circular arc.In one embodiment, gate material layers 204 can be used as the floating grid in flash memory device.
In one embodiment, can will on above-mentioned semiconductor structure, be applied in the manufacturing process of not b gate flash memory (NAND flash memory).For example, after removing resistance barrier oxide layer 206, further in gate material layers 204, sequentially form oxygen-nitrogen-oxygen (ONO) layer 218 and control grid layer 220, as shown in figure 13, O-N-O layer 218 is conformably formed on gate material layers 204 and oxide skin(coating) 214.Controlling grid layer 220 is for example polysilicon, and it is cover on O-N-O layer 218 and have a smooth plane.In various embodiments of the invention, can utilize any method and material known or future development to form O-N-O layer 218 and control grid layer 220.In this embodiment, the corner of gate material layers 204 circular arcs is conducive to the formation of O-N-O layer 218, can avoid the generation of space (voids).
In various embodiments of the invention; a kind of undamaged floating gate structure can be provided; can utilize resistance barrier oxide layer as the protective layer of gate material layers, to avoid gate material layers to suffer damage, affect element efficiency in removing the etching manufacturing process of curtain layer of hard hood.In addition, in groove, form in the step of oxide skin(coating), can make gate material layers form circular arc corner, to avoid the problem of element point discharge.In addition, can utilize the etch step that removes the residual oxide skin(coating) of trenched side-wall, remove in the lump above-mentioned resistance barrier oxide layer, therefore not need to carry out again extra manufacturing technology steps and removed.
Although the present invention discloses as above with several preferred embodiments; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the invention; when doing any change and retouching, thus the present invention's protection range when with the claims in the present invention scope the person of being defined be as the criterion.
Claims (10)
1. a formation method for semiconductor device, is characterized in that, described formation method comprises:
One substrate is provided, on described substrate, sequentially forms a gate dielectric, a gate material layers, resistance barrier oxide layer and a curtain layer of hard hood;
The sequentially curtain layer of hard hood described in etching, described resistance barrier oxide layer, described gate material layers, described gate dielectric and described substrate, to form a groove in described substrate;
In described groove, insert monoxide layer;
Described oxide skin(coating) in groove described in etchback, to reduce the height of described oxide skin(coating);
Remove described curtain layer of hard hood, and described remove step in described its lower described gate material layers of resistance barrier protect oxide layer; And
Remove described resistance barrier oxide layer, and expose described gate material layers.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the described gate material layers exposing after the resistance barrier oxide layer described in removing has the corner of circular arc.
3. the formation method of semiconductor device as claimed in claim 2, is characterized in that, described oxide series of strata form with thermal oxidation method, and described gate material layers forms the corner of circular arc in described step of thermal oxidation.
4. the formation method of semiconductor device as claimed in claim 1, is characterized in that, described gate dielectric comprises passage oxide skin(coating).
5. the formation method of semiconductor device as claimed in claim 1, is characterized in that, removing of described curtain layer of hard hood is to utilize wet etching erosion manufacturing process, and removing of oxide layer of described resistance barrier is to utilize dry etching manufacturing process.
6. the formation method of semiconductor device as claimed in claim 5, is characterized in that, removing of described curtain layer of hard hood is to utilize hot phosphoric acid etching, and removing of oxide layer of described resistance barrier is to utilize buffer oxide etching.
7. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, after described oxide skin(coating) in the groove described in etchback, a part for described oxide skin(coating) still remains on the sidewall of described groove, and removes in the lump residual part when removing described resistance barrier oxide layer.
8. the formation method of semiconductor device as claimed in claim 7, is characterized in that, on the whole the thickness that described oxide skin(coating) remains in the described part of sidewall equal the thickness of described resistance barrier oxide layer.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, after removing described resistance barrier oxide layer, is more included in described gate material layers and forms an O-N-O layer.
10. the formation method of semiconductor device as claimed in claim 9, is characterized in that, described method is more included on described O-N-O layer and forms a control grid.
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| CN201210306872.1A CN103633031B (en) | 2012-08-27 | 2012-08-27 | The formation method of semiconductor device |
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| CN201210306872.1A CN103633031B (en) | 2012-08-27 | 2012-08-27 | The formation method of semiconductor device |
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| CN109981961A (en) * | 2019-05-15 | 2019-07-05 | 德淮半导体有限公司 | A kind of camera module structure and preparation method thereof |
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| TWI334633B (en) * | 2005-03-30 | 2010-12-11 | Winbond Electronics Corp | Non-volatile memory device and method of fabricating the same |
| KR100745957B1 (en) * | 2006-02-07 | 2007-08-02 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
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| CN109981961A (en) * | 2019-05-15 | 2019-07-05 | 德淮半导体有限公司 | A kind of camera module structure and preparation method thereof |
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