CN109686665A - Semiconductor devices isolation side walls manufacturing method - Google Patents
Semiconductor devices isolation side walls manufacturing method Download PDFInfo
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- CN109686665A CN109686665A CN201811607276.0A CN201811607276A CN109686665A CN 109686665 A CN109686665 A CN 109686665A CN 201811607276 A CN201811607276 A CN 201811607276A CN 109686665 A CN109686665 A CN 109686665A
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- side walls
- isolation side
- semiconductor devices
- sacrificial layer
- etching
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- 238000002955 isolation Methods 0.000 title claims abstract description 108
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 54
- 125000006850 spacer group Chemical group 0.000 claims abstract description 24
- RAHZWNYVWXNFOC-UHFFFAOYSA-N Sulphur dioxide Chemical compound O=S=O RAHZWNYVWXNFOC-UHFFFAOYSA-N 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 4
- -1 fluoro alkyl compound Chemical class 0.000 claims description 3
- 238000000034 method Methods 0.000 description 13
- 238000003860 storage Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000010422 painting Methods 0.000 description 3
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a kind of semiconductor devices isolation side walls manufacturing methods, it include: production semiconductor isolation side wall spacer, it makes sacrificial layer and covers isolation side walls spacer, carry out first time sacrificial layer etching removal partial sacrificial layer, it carries out isolation side walls and etches the isolation side walls spacer to form design pattern, carry out second of sacrificial layer etching and remove whole sacrificial layers.The present invention makes isolation side walls form the influence that rectangular pattern is avoided that asymmetric pattern isolation side walls etchs lower layer layer after the completion of device isolation side wall manufactures by etching, improves the homogeneity of device, raising device performance.
Description
Technical field
The present invention relates to semiconductor fields, more particularly to a kind of semiconductor devices isolation side walls manufacturing method.
Background technique
Increasingly increase for the semiconductor storage demand of high capacity, the integration density of these semiconductor storages
It is concerned by people, in order to increase the integration density of semiconductor storage, uses many different sides in the prior art
Method, such as multiple storage units are formed on single wafer by structural unit in reducing wafer size and/or changing, for
For the method for increasing integration density by changing cellular construction, carry out attempting horizontal layout of the ditch by changing active area
Or changes cell layout and carry out reduction unit area.
Nand-flash memory is one kind of flash memory, internal to use non-linear macroelement mode, is solid-state
The realization of large capacity memory provides cheap effective solution scheme.Nand flash memory is a kind of storage more better than hard disk drive
Scheme, since nand flash memory reads and writes data as unit of page, so be suitable for storing continuous data, as picture, audio or its
His file data；Simultaneously because of its is at low cost, capacity is big and writing speed is fast, the erasing time is short advantage in mobile communication device and
The field of storage of portable multimedia device is widely used.Currently, needing making to improve the capacity of nand flash memory
The integration density of nand flash memory is improved during standby.The data of NAND Flash are that minimum operation wiping is stored in a manner of bit
In general write-read unit memory cell, abbreviation cell can only store one in the erasable reading unit CELL of a minimum operation
A bit.The erasable reading unit CELL of these minimum operations is linked to be bit line as unit of 8 or 16, is formed so-called
Byte (x8)/word (x16), here it is the bit wides of NAND Device.These Line can recomposition Page.Specific a piece of flash
How many upper Block optionally determines.
Nand-flash memory has many advantages, such as that capacity is larger, and it is fast to rewrite speed, suitable for the storage of mass data, because
And be in the industry cycle more and more widely used, as included digital camera, MP3 walkman memory card, body in embedded product
The small and exquisite USB flash disk etc. of product.
During preparing nand flash memory, spacer patterns technology (Spacer patterning technology,
SPT) and self-aligned double patterning case technology (self aligned double patterning, SADP) can be used to prepare to receive
The transistor of metrical scale exists when handling the chip of semiconductor using the method usually using well known patterning and etch process
The feature of semiconductor devices is formed in chip, in these photoetching processes, Other substrate materials are deposited on chip, are then exposed to
By the light that reticule filters, after reticule, the surface of the light contacts Other substrate materials, the light changes
The chemical component of the Other substrate materials can remove a part of the Other substrate materials to developing machine, obtain required figure
Case,
20nm NAND is under 2X generation node, due to the exposure limit of ArF, the minimum of AA/GT/CM2loop
It operates the erasable reading area unit cell and final graphics pattern is formed using self-aligned double patterning case technique SADP technology.Traditional
Asymmetric pattern after isolation side walls etching spacer etch will affect succeeding layer etching layer etch processing procedure plasma
The directionality of plasma leads to the generation of size offset pitch-walking phenomenon, causes device homogeneity poor, influences device
Performance.
Summary of the invention
The technical problem to be solved in the present invention is to provide one kind to be avoided that isolation side walls pattern impacts lower layer's etching
Semiconductor devices isolation side walls manufacturing method.
In order to solve the above technical problems, semiconductor devices isolation side walls manufacturing method provided by the invention, including following step
It is rapid:
1) semiconductor isolation side wall spacer is made；
2) production sacrificial layer covers isolation side walls spacer
3) first time sacrificial layer etching removal partial sacrificial layer is carried out；
4) isolation side walls are carried out and etches the isolation side walls spacer to form design pattern；
5) it carries out second of sacrificial layer etching and removes whole sacrificial layers.
It is further improved the semiconductor devices isolation side walls manufacturing method, the semiconductor devices is NAND
flash。
It is further improved the semiconductor devices isolation side walls manufacturing method, the semiconductor devices is 2X NAND
flash。
It is further improved the semiconductor devices isolation side walls manufacturing method, the sacrificial layer is organic dielectric layer
(organic dielectric layer, ODL) or Spun-on carbon (spin on carbon, S0C).
It is further improved the semiconductor devices isolation side walls manufacturing method, the first time sacrificial layer etching will sacrifice
Layer is etched to the asymmetric pattern initial position of isolation side walls.
It is further improved the semiconductor devices isolation side walls manufacturing method, the first time sacrificial layer etching is using dry
Method etching.
It is further improved the semiconductor devices isolation side walls manufacturing method, the first time sacrificial layer etching uses nitrogen
Gas N2, hydrogen H2, sulfur dioxide SO2Or oxygen O2。
It is further improved the semiconductor devices isolation side walls manufacturing method, the design pattern is rectangular isolation side walls
Figure pattern.
It is further improved the semiconductor devices isolation side walls manufacturing method, the isolation side walls etching sacrifices residue
Layer or more isolation side walls etch removal.
It is further improved the semiconductor devices isolation side walls manufacturing method, the isolation side walls etching is carved using dry method
Erosion.
It is further improved the semiconductor devices isolation side walls manufacturing method, the isolation side walls etching is carbonized using fluorine
Object CxHy gas or fluoro alkyl compound gas CxHyFz are closed as base gas.
It is further improved the semiconductor devices isolation side walls manufacturing method, second of etching is carved using dry method
Erosion.
It is further improved the semiconductor devices isolation side walls manufacturing method, second of etching uses nitrogen N2、
Hydrogen H2, sulfur dioxide SO2Or oxygen O2。
The present invention increases production sacrificial layer covering isolation side walls after the completion of making semiconductor isolation side wall, passes through secondary sacrifice
Layer etching removal sacrificial layer simultaneously etches the isolation side walls to form design pattern by isolation side walls.Technical solution of the present invention is in device
So that isolation side walls is formed rectangular pattern by etching after the completion of manufacture before part isolation is surveyed and is avoided that asymmetric pattern isolation side walls pair
The influence of lower layer layer etching, improves the homogeneity of device, improves device performance.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is flow diagram one of the present invention.
Fig. 2 is flow diagram two of the present invention.
Fig. 3 is flow diagram three of the present invention.
Fig. 4 is flow diagram four of the present invention.
Fig. 5 is flow diagram five of the present invention.
Description of symbols
Isolation side walls 1
Polysilicon 2
Teos layer 3
Silicon nitride layer 4
Floating gate 5
Oxide layer 6
Sacrificial layer 7
Specific embodiment
Semiconductor devices isolation side walls manufacturing method first embodiment provided by the invention, by taking 2X NAND as an example, including with
Lower step:
1) as shown in Figure 1, production semiconductor isolation side wall spacer；
2) as shown in Fig. 2, production sacrificial layer covers isolation side walls spacer；
3) as shown in figure 3, carrying out first time sacrificial layer etching removal partial sacrificial layer, the first time sacrificial layer etching will
Sacrificial layer is etched to the asymmetric pattern initial position of isolation side walls；
4) as shown in figure 4, carrying out isolation side walls etches the isolation side walls spacer to form design pattern, the design pattern
It is rectangular isolation side walls figure pattern；
5) as shown in figure 5, carrying out second of sacrificial layer etching removes whole sacrificial layers.
Semiconductor devices isolation side walls manufacturing method second embodiment provided by the invention, by taking 2X NAND as an example, including with
Lower step:
1) as shown in Figure 1, production semiconductor isolation side wall spacer；
2) as shown in Fig. 2, production sacrificial layer covers isolation side walls spacer, the sacrificial layer is organic dielectric layer or standing grain mouth
Dote on painting carbon in side；
3) as shown in figure 3, carrying out first time sacrificial layer etching removal partial sacrificial layer, the first time sacrificial layer etching will
Sacrificial layer is etched to the asymmetric pattern initial position of isolation side walls；
4) as shown in figure 4, carrying out isolation side walls etches the isolation side walls spacer to form design pattern, the design pattern
It is rectangular isolation side walls figure pattern；
5) as shown in figure 5, carrying out second of sacrificial layer etching removes whole sacrificial layers.
Semiconductor devices isolation side walls manufacturing method 3rd embodiment provided by the invention, by taking 2X NAND as an example, including with
Lower step:
1) as shown in Figure 1, production semiconductor isolation side wall spacer；
2) as shown in Fig. 2, production sacrificial layer covers isolation side walls spacer, the sacrificial layer is organic dielectric layer or standing grain mouth
Dote on painting carbon in side；
3) as shown in figure 3, carrying out first time sacrificial layer etching removal partial sacrificial layer, the first time sacrificial layer etching is adopted
With dry etching, sacrificial layer is etched to the asymmetric pattern initial position of isolation side walls by the first time sacrificial layer etching；
4) as shown in figure 4, carrying out isolation side walls etches the isolation side walls spacer to form design pattern, the design pattern
It is rectangular isolation side walls figure pattern；Isolation side walls more than remaining sacrificial layer are etched removal by the isolation side walls etching；Institute
Isolation side walls etching is stated using dry etching.
5) as shown in figure 5, carrying out second of sacrificial layer etching removes whole sacrificial layers, second of etching uses dry method
Etching.
Semiconductor devices isolation side walls manufacturing method fourth embodiment provided by the invention, by taking 2X NAND as an example, including with
Lower step:
1) as shown in Figure 1, production semiconductor isolation side wall spacer；
2) as shown in Fig. 2, production sacrificial layer covers isolation side walls spacer, the sacrificial layer is organic dielectric layer or standing grain mouth
Dote on painting carbon in side；
3) as shown in figure 3, carrying out first time sacrificial layer etching removal partial sacrificial layer, the first time sacrificial layer etching is adopted
With dry etching, sacrificial layer is etched to the asymmetric pattern initial position of isolation side walls by the first time sacrificial layer etching, described
First time sacrificial layer etching uses nitrogen N2, hydrogen H2, sulfur dioxide SO2Or oxygen O2；
4) as shown in figure 4, carrying out isolation side walls etches the isolation side walls spacer to form design pattern, the design pattern
It is rectangular isolation side walls figure pattern；Isolation side walls more than remaining sacrificial layer are etched removal by the isolation side walls etching；Every
Dry etching is used from side wall etching, the isolation side walls etching uses fluorocarbons CxHy gas or fluoro alkyl compound
Gas CxHyFz is as base gas；
5) as shown in figure 5, carrying out second of sacrificial layer etching removes whole sacrificial layers, second of etching uses dry method
Etching, second of sacrificial layer etching use nitrogen N2, hydrogen H2, sulfur dioxide SO2Or oxygen O2。
The present invention increases production sacrificial layer covering isolation side walls after the completion of making semiconductor isolation side wall, passes through secondary sacrifice
Layer etching removal sacrificial layer simultaneously etches the isolation side walls to form rectangular pattern by isolation side walls.According to recorded in above-described embodiment
Scheme, the influence that lower layer layer can be etched to avoid unsymmetrical looks isolation side walls when manufacturing isolation side walls, improve
The homogeneity of device.
Above by specific embodiment and embodiment, invention is explained in detail, but these are not composition pair
Limitation of the invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Into these also should be regarded as protection scope of the present invention.
Claims (13)
1. a kind of semiconductor devices isolation side walls manufacturing method, which comprises the following steps:
1) semiconductor isolation side wall (spacer) is made；
2) production sacrificial layer covering isolation side walls (spacer)
3) first time sacrificial layer etching removal partial sacrificial layer is carried out；
4) isolation side walls are carried out and etches the isolation side walls (spacer) to form design pattern；
5) it carries out second of sacrificial layer etching and removes whole sacrificial layers.
2. semiconductor devices isolation side walls manufacturing method as described in claim 1, it is characterised in that: the semiconductor devices is
NAND flash。
3. semiconductor devices isolation side walls manufacturing method as claimed in claim 2, it is characterised in that: the semiconductor devices is
2X NAND flash。
4. semiconductor devices isolation side walls manufacturing method as claimed in claim 3, it is characterised in that: the sacrificial layer is organic
Dielectric layer (organic dielectric layer, ODL) or Spun-on carbon (spin on carbon, S0C).
5. semiconductor devices isolation side walls manufacturing method as described in claim 1, it is characterised in that: the first time sacrificial layer
Sacrificial layer is etched to the asymmetric pattern initial position of isolation side walls by etching.
6. semiconductor devices isolation side walls manufacturing method as claimed in claim 5, it is characterised in that: the first time sacrificial layer
Etching uses dry etching.
7. semiconductor devices isolation side walls manufacturing method as claimed in claim 6, it is characterised in that: the first time sacrificial layer
Etching uses nitrogen (N2), hydrogen (H2), sulfur dioxide (SO2) or oxygen (O2)。
8. semiconductor devices isolation side walls manufacturing method as described in claim 1, it is characterised in that: the design pattern side of being
Shape isolation side walls figure pattern.
9. semiconductor devices isolation side walls manufacturing method as claimed in claim 5, it is characterised in that: the isolation side walls etching
Isolation side walls more than remaining sacrificial layer are etched into removal.
10. semiconductor devices isolation side walls manufacturing method as claimed in claim 9, it is characterised in that: the side of isolation stela
Erosion uses dry etching.
11. semiconductor devices isolation side walls manufacturing method as claimed in claim 10, it is characterised in that: the side of isolation stela
Erosion is used as base gas using fluorocarbons (CxHy) gas or fluoro alkyl compound gas (CxHyFz).
12. semiconductor devices isolation side walls manufacturing method as described in claim 1, it is characterised in that: second of etching
Using dry etching.
13. semiconductor devices isolation side walls manufacturing method as claimed in claim 12, it is characterised in that: second of etching
Using nitrogen (N2), hydrogen (H2), sulfur dioxide (SO2) or oxygen (O2)。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811607276.0A CN109686665A (en) | 2018-12-27 | 2018-12-27 | Semiconductor devices isolation side walls manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811607276.0A CN109686665A (en) | 2018-12-27 | 2018-12-27 | Semiconductor devices isolation side walls manufacturing method |
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ID=66189879
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| CN201811607276.0A Pending CN109686665A (en) | 2018-12-27 | 2018-12-27 | Semiconductor devices isolation side walls manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599816A (en) * | 2020-05-28 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for improving line width difference of grid etching process in SADP process |
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| US20050136649A1 (en) * | 2003-12-22 | 2005-06-23 | Min-Suk Lee | Method and fabricating semiconductor device |
| CN103578931A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Multiple graphical mask layer and forming method thereof |
| CN104900495A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned double patterning method and fin field effect transistor manufacturing method |
| CN108206131A (en) * | 2016-12-20 | 2018-06-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure and semiconductor structure |
-
2018
- 2018-12-27 CN CN201811607276.0A patent/CN109686665A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050136649A1 (en) * | 2003-12-22 | 2005-06-23 | Min-Suk Lee | Method and fabricating semiconductor device |
| CN103578931A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Multiple graphical mask layer and forming method thereof |
| CN104900495A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned double patterning method and fin field effect transistor manufacturing method |
| CN108206131A (en) * | 2016-12-20 | 2018-06-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure and semiconductor structure |
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| CN111599816A (en) * | 2020-05-28 | 2020-08-28 | 上海华力集成电路制造有限公司 | Method for improving line width difference of grid etching process in SADP process |
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Application publication date: 20190426 |