TWI508187B - Method for manufacturing a semiconductor device - Google Patents

Description

Method of forming a semiconductor device

The present invention relates to a method of forming a semiconductor structure, and more particularly to a method of forming a semiconductor structure using a barrier oxide layer as a protective layer.

Flash Memory is a non-volatile memory device that saves data without consuming power and can be deleted or written multiple times during operation. In addition, compared to other memory devices, flash memory has lower read latency, better dynamic shock resistance, and has a significant speed advantage when writing large amounts of data, so it is often used for general data storage, and Exchange data between computers and other digital products, such as memory cards and flash drives.

In addition, another advantage of flash memory is the low cost of manufacturing. Therefore, flash memory has become the most important and widely adopted technology for non-volatile solid-state storage, for example, it can be applied to notebook computers. Digital Walkman, digital camera, mobile phone, game console and other related products.

For NAND flash memory, the main focus is on the charge storage capability of the floating gate. In addition, in the semiconductor manufacturing process, as the size of the memory is reduced, the performance of the floating gate is also paid more attention. In the process of a general floating gate, the removal of the hard mask causes damage to the gate polysilicon and causes a decrease in gate efficiency. On the other hand, the tip shape of the gate rectangle may have a problem of tip discharge.

Therefore, there is a need for a novel semiconductor process that can improve floating. The effectiveness of the gate.

An embodiment of the present invention provides a method of forming a semiconductor device, including: providing a substrate on which a gate dielectric layer, a gate material layer, a barrier oxide layer, and a hard mask are sequentially formed. a layer; the hard mask layer, the barrier oxide layer, the gate material layer, the gate dielectric layer, and the substrate are sequentially etched to form a trench in the substrate; filling the trench An oxide layer; the oxide layer in the trench is recessed to reduce the height of the oxide layer; the hard mask layer is removed, and the barrier oxide layer is protected under the removing step The gate material layer; and removing the barrier oxide layer to expose the gate material layer.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Several different embodiments are set forth below in accordance with various features of the invention. The specific elements and arrangements of the present invention are intended to be simplified, but the invention is not limited to these embodiments. For example, a description of forming a first element on a second element can include an embodiment in which the first element is in direct contact with the second element, and also includes having additional elements formed between the first element and the second element such that An embodiment in which one element is not in direct contact with the second element. Moreover, for the sake of brevity, the present invention is represented by repeated element symbols and/or letters in the different examples, but does not represent a specific relationship between the various embodiments and/or structures. system.

1 is a flow chart showing a method of forming a semiconductor device in an embodiment of the present invention. In step 102, a substrate is provided, and a gate dielectric layer, a gate material layer, a barrier oxide layer, and a hard mask layer are sequentially formed on the substrate. In step 104, the hard mask layer, the barrier oxide layer, the gate material layer, the gate dielectric layer, and the substrate are sequentially etched to form a trench in the substrate. In step 106, an oxide layer is filled in the trench. In step 108, the oxide layer in the trench is recessed to reduce the height of the oxide layer. In step 110, the hard mask layer is removed and the underlying gate material layer is protected by a barrier oxide layer during the removal step. In step 112, the barrier oxide layer is removed to expose the gate material layer.

Figures 2 through 11 show cross-sectional views of the semiconductor device formed in accordance with the method of Figure 1 at various stages of fabrication in an embodiment. In order to understand the concept of the present invention more clearly and easily, the figures 2 to 11 have been simplified. In some embodiments, additional components may be added in the semiconductor device, and in other embodiments, some of the semiconductor devices described below may be replaced or removed.

Referring to FIG. 2, a substrate 200 is provided, and a gate dielectric layer 202 is formed on the substrate 200. In an embodiment, the substrate 200 includes a germanium substrate, a germanium substrate, or a semiconductor-on-insulator substrate. Gate dielectric layer 202 can comprise a dielectric material such as hafnium oxide, a high dielectric constant dielectric material, other suitable dielectric materials, or a combination of the foregoing. In an embodiment, the gate dielectric layer 202 can be a tunnel oxide layer formed using a thermal oxidation process. In another embodiment, it may also be formed by other methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. Gate dielectric layer 202.

Referring to FIG. 3, a gate material layer 204 is formed over the gate dielectric layer 202. In an embodiment, the gate material layer 204 comprises a polysilicon layer. The formation of the gate material layer 204 can utilize a deposition process such as chemical vapor deposition (CVD).

Referring to FIG. 4, a barrier oxide layer 206 is formed on the gate material layer 204. The barrier oxide layer 206 may include hafnium oxide, hafnium oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium oxynitride, or a combination thereof. The barrier oxide layer 206 can be formed using any suitable process, such as thermal oxidation, chemical vapor deposition, spin coating, and the like. In one embodiment, the barrier oxide layer 206 can be formed by growing a silicon oxide dielectric on the gate level material layer 204.

Referring to FIG. 5, a hard mask layer 208 is formed on the barrier oxide layer 206. The hard mask layer 208 can include a tantalum nitride layer or other suitable hard mask material. The formation of the hard mask layer 208 can utilize a deposition process such as chemical vapor deposition (CVD).

Referring to FIG. 6, a patterned photoresist layer 210 is formed on the hard mask layer 208. The formation of the patterned photoresist layer 210 can utilize any known or future developed photoresist material and method. Referring to FIG. 7, the patterned photoresist layer 210 is used as a mask, and the hard mask layer 208, the barrier oxide layer 206, the gate material layer 204, the gate dielectric layer 202, and the substrate 200 are sequentially etched to A trench 212 is formed in the substrate 200. The above etching process may include dry etching such as plasma etching or reactive ion etching.

Referring to FIG. 8, after the trench 212 is formed, the structure of FIG. 7 is ashed and then cleaned, and the patterned photoresist layer 210 is removed. Referring to Figure 9, The oxide layer 214 is filled in the trench 212 such that the oxide layer 214 substantially fills the trench 212. The oxide layer 214 is, for example, cerium oxide. The formation of the oxide layer 214 can be carried out by a thermal oxidation method, for example, at 900 ° C to 1050 ° C for 14 seconds to 22 seconds. It should be noted that in the process of forming the oxide layer 214, the corners of the gate material layer 204 may be oxidized together to form a circular arc-shaped corner.

Referring to FIG. 10, the oxide layer 214 in the trench 212 is recessed to reduce the height of the oxide layer 214. In an embodiment, the upper surface of the oxide layer 214 may be substantially between the upper and lower surfaces of the gate material layer 204. Referring to Figure 11, the hard mask layer 208 is removed and the barrier material layer 204 underneath is protected by a barrier oxide layer 206. In an embodiment, the hard mask layer 208 can be removed using a wet etch process, such as with a hot phosphoric acid etch. Then, the barrier oxide layer 206 is removed to expose the gate material layer 204 as shown in FIG. In the conventional process, when the hard mask layer is removed by hot phosphoric acid etching, the gate material layer is directly exposed, and the hot phosphoric acid will extend into the gate of the gate material layer (such as the polysilicon layer). In the material layer, the performance of the formed element is impaired. However, in this embodiment, the additional barrier oxide layer 206 is used to protect the gate material layer 204 from thermal phosphoric acid, and then the barrier oxide layer is removed in a process that does not damage the gate material layer 204. 206. The method of removing the barrier oxide layer 206 includes, for example, buffered oxide etch (BHF).

It should be noted that when the oxide layer 214 formed in FIG. 9 is subjected to the etching step, a portion 216 of the oxide layer 214 remains on the sidewalls of the trench 212 as shown in FIG. Therefore, after the hard mask layer 208 is removed, it is generally necessary to remove the residual portion 216 of the oxide layer using another etching process. In this embodiment, a single etch process can be utilized while removing the barrier oxide layer 206 and the residual portion 216 of the oxide layer. That is, the barrier oxide layer 206 can protect the gate material layer 204 not only in the etching process of removing the hard mask layer 208, but also in the etching step of removing the residual portion 216 of the oxide layer. No additional process steps are required. In a preferred embodiment, the thickness of the portion 216 of the oxide layer 214 remaining on the sidewall is substantially equal to the thickness of the barrier oxide layer 206. For example, the barrier oxide layer 206 can have a thickness between 5 nm and 10 nm.

Referring to Fig. 12, the gate material layer 204 exposed after removing the barrier oxide layer 206 has a circular arc-shaped corner. This rounded corner avoids the undesirable effects of component point discharges that are formed in subsequent processes. In an embodiment, the gate material layer 204 can serve as a floating gate in a flash memory device.

In one embodiment, the above semiconductor structure can be applied to a process of NAND flash memory. For example, after the barrier oxide layer 206 is removed, an oxygen-nitrogen-oxygen (ONO) layer 218 and a control gate layer 220 are sequentially formed on the gate material layer 204, as shown in FIG. A nitrogen-oxygen layer 218 is conformally formed on the gate material layer 204 and the oxide layer 214. The control gate layer 220 is, for example, a polysilicon which covers the oxy-nitrogen-oxygen layer 218 and has a flat plane. In various embodiments of the invention, the oxygen-nitrogen-oxygen layer 218 and the control gate layer 220 may be formed using any known or future developed methods and materials. In this embodiment, the corners of the arc of the gate material layer 204 facilitate the formation of the oxygen-nitrogen-oxygen layer 218, avoiding the generation of voids.

In various embodiments of the invention, a damage-free floating gate can be provided The pole structure can utilize the barrier oxide layer as a protective layer of the gate material layer to prevent the gate material layer from being damaged in the etching process for removing the hard mask layer and affecting the device performance. Further, in the step of forming an oxide layer in the trench, the gate material layer can be formed into a circular arc corner to avoid the problem of discharge of the tip of the element. In addition, the above-mentioned barrier oxide layer can be removed by an etching step of removing the oxide layer remaining on the trench sidewalls, so that no additional process steps are required to remove it.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

102, 104, 106, 108, 110, 112‧‧‧ steps

200‧‧‧Substrate

202‧‧‧ gate dielectric layer

204‧‧‧ gate material layer

206‧‧‧Block oxide layer

208‧‧‧hard mask layer

210‧‧‧ patterned photoresist layer

212‧‧‧ trench

214‧‧‧Oxide layer

216‧‧‧Residual part of the oxide layer

220‧‧‧Control gate layer

Fig. 1 is a flow chart showing a method of forming a semiconductor device according to an embodiment of the present invention.

Figures 2 through 13 show cross-sectional views of the semiconductor device formed in accordance with the method of Figure 1 at various stages of fabrication in an embodiment.

200‧‧‧Substrate

202‧‧‧ gate dielectric layer

204‧‧‧ gate material layer

206‧‧‧Block oxide layer

208‧‧‧hard mask layer

214‧‧‧Oxide layer

216‧‧‧Residual part of the oxide layer

Claims (10)

A method for forming a semiconductor device includes: providing a substrate on which a gate dielectric layer, a gate material layer, a barrier oxide layer, and a hard mask layer are sequentially formed; a hard mask layer, the barrier oxide layer, the gate material layer, the gate dielectric layer and the substrate to form a trench in the substrate; filling an oxide layer in the trench; Etching the oxide layer in the trench to reduce the height of the oxide layer; removing the hard mask layer, and protecting the gate material layer under the barrier oxide layer in the removing step And removing the barrier oxide layer to expose the gate material layer. The method of forming a semiconductor device according to claim 1, wherein the gate material layer exposed after removing the barrier oxide layer has a rounded corner. The method of forming a semiconductor device according to claim 2, wherein the oxide layer is formed by a thermal oxidation method, and the gate material layer forms a circular arc-shaped corner in the thermal oxidation step. The method of forming a semiconductor device according to claim 1, wherein the gate dielectric layer comprises a channel oxide layer. The method of forming a semiconductor device according to claim 1, wherein the removal of the hard mask layer is performed by a wet etching process, and the removal of the barrier oxide layer is performed by a dry etching process. The method of forming a semiconductor device according to claim 5, wherein the removal of the hard mask layer is performed by hot phosphoric acid etching, and the barrier is The removal of the oxide layer utilizes buffered oxide etch (BHF). The method of forming a semiconductor device according to claim 1, wherein after etching the oxide layer in the trench, a portion of the oxide layer remains on the sidewall of the trench and is moving The residual portion is removed together with the barrier oxide layer. The method of forming a semiconductor device according to claim 7, wherein a thickness of the portion of the oxide layer remaining on the sidewall is substantially equal to a thickness of the barrier oxide layer. The method for forming a semiconductor device according to claim 1, after removing the barrier oxide layer, further comprising forming an oxygen-nitrogen-oxygen (ONO) layer on the gate material layer. The method of forming a semiconductor device according to claim 9, further comprising forming a control gate on the oxy-nitrogen-oxygen layer.