JP2010157557A - Method of manufacturing non-volatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device which is hard to cause degradation of memory properties by the ISSG oxidation method. <P>SOLUTION: A method of manufacturing a non-volatile semiconductor memory device includes the following steps of: sequentially forming a first gate insulating film 106 and a first conductive film 107 on a memory area 101 and a periphery transistor region 102 (a); removing a part formed on the periphery transistor region 102 in the first conductive film 107 and the first gate insulating film 106 (b); and of carrying out ISSG (in-situ steam generation) oxidation while the first conductive film 107 is remained on the memory area 101, forming a second gate insulating film 109 on the periphery transistor region 102, and forming an on-conductive-film oxidation film 110 on the first conductive film 107 remained on the memory area 101 (c). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly to a method for manufacturing a nonvolatile semiconductor memory device in which a MONOS type memory and a peripheral circuit coexist.

  Conventionally, an impurity diffusion layer formed on a surface layer of a semiconductor substrate is a bit line (buried bit line), and a word line orthogonal to the bit line traps charges and stores data through a gate insulating film that stores data. A nonvolatile semiconductor memory device (MONOS type memory) formed thereon is known.

  In a nonvolatile semiconductor memory device, it is a common practice to mount MOS transistors such as a drive circuit and a logic circuit on the periphery of a memory area. Therefore, it is necessary to form a gate insulating film in the memory region and the peripheral transistor region. The MOS transistor in the memory region preferably has a relatively thick gate insulating film to ensure reliability. On the other hand, in the peripheral MOS transistor, it is preferable to make the gate insulating film relatively thin in order to enable high speed operation. As a method of forming gate insulating films having different thicknesses on the same substrate, a method of forming a laminated gate insulating film by a chemical vapor deposition method (CVD method), or a desired film thickness by a photoresist mask and wet etching. A method for forming a gate insulating film is known.

However, if a photoresist mask and wet etching are repeated to form gate insulating films having various thicknesses, the reliability of the gate insulating film is reduced due to organic contamination and cleaning damage. In addition, an increase in effective gate width due to a reduction in the film thickness of the element isolation region occurs, and an influence on leakage characteristics occurs. For this reason, for example, a method of simultaneously forming oxide films having different film thicknesses using a difference in oxidation rate between a nitride film and a silicon substrate has been studied (see, for example, Patent Document 1). .
JP-A-2005-005516

  However, ISSG (in-situ steam generation) oxidation is used in the conventional method for forming a gate insulating film having a different thickness. In ISSG oxidation, unreacted hydrogen gas is present in the chamber during film formation. For this reason, unreacted hydrogen gas at the time of film formation may enter the interface between the substrate and the gate insulating film in the memory region, increasing the interface state between the substrate and the gate insulating film, and possibly degrading the rewriting characteristics. . The inventor of the present application has found that this phenomenon becomes particularly prominent with miniaturization and becomes a serious problem.

  On the other hand, when film formation is performed using an external combustion type pyrogenic oxidation method in order to avoid the influence of unreacted hydrogen gas, the thermal budget becomes large and profile control becomes difficult.

  An object of the present invention is to solve the above-described problems and to realize a nonvolatile semiconductor memory device in which deterioration of memory characteristics due to the ISSG oxidation method hardly occurs.

  To achieve the above object, the present invention provides a method for manufacturing a nonvolatile semiconductor memory device in which a gate insulating film of a peripheral transistor is formed in a state where a gate insulating film in a memory region is covered with a conductive film.

  Specifically, in the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, a first gate insulating film including an insulating film having a charge holding function and a first gate on a semiconductor substrate having a memory region and a peripheral transistor region. From the step (a) of sequentially forming the conductive film, the step (b) of removing the portion formed on the peripheral transistor region in the first conductive film and the first gate insulating film, and the step (b) Thereafter, by performing ISSG oxidation in a state where the first conductive film remains on the memory region, a second gate insulating film is formed on the peripheral transistor region and the first remaining on the memory region. A step (c) of forming an oxide film on the conductive film on the upper portion of the conductive film, a step (d) of forming a second conductive film on the semiconductor substrate after the step (c), and a step (d). Later than the memory area The memory cell is formed by selectively removing the second conductive film, the first conductive film, and the first gate insulating film, and the second conductive film and the second gate are formed in the peripheral transistor region. And (e) forming a peripheral transistor by selectively removing the insulating film.

  According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the ISSG oxidation is performed in a state where the first conductive film remains on the memory region, and the second gate insulating film is formed on the peripheral transistor region and the memory is formed. An oxide film on the conductive film is formed on the first conductive film remaining on the region. For this reason, unreacted hydrogen gas is unlikely to enter the interface between the first gate insulating film and the semiconductor substrate in the memory region during ISSG oxidation. Therefore, it is possible to realize a method for manufacturing a nonvolatile semiconductor memory device in which the interface state of the first gate insulating film due to hydrogen gas does not easily increase and the rewrite characteristics and the like hardly deteriorate.

  In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the step (e) includes forming a bit line in the memory region in the second conductive film, the oxide film on the conductive film, the first conductive film, and the first gate insulating film. A step (e1) of forming an opening exposing the semiconductor substrate by removing a portion formed on the region, and a step of forming a bit line by introducing impurities into the portion exposed from the opening of the semiconductor substrate (E2) and, after forming the insulating film on the bit line so as to fill the opening, removing the portion formed on the memory region in the second conductive film (e3), and more than the step (e3) Later, a step (e4) of removing a portion formed on the memory region in the oxide film on the conductive film and a portion remaining on the peripheral transistor region in the insulating film on the bit line, and after the step (e4), the memory region And forming a third conductive film on the peripheral transistor region (e5) and may be configured to include a.

  The step (e) includes a step (e1) of removing a portion formed on the memory region in the second conductive film, and a first insulating film on the semiconductor substrate after the step (e1). And the step (e2) of sequentially forming the second insulating film, and after the step (e2), the second insulating film, the first insulating film, the oxide film on the conductive film, the first conductive film, and the first conductive film A step (e3) of forming an opening exposing the semiconductor substrate by removing a portion of the gate insulating film formed on the bit line formation region of the memory region, and a portion exposed from the opening of the semiconductor substrate A step (e4) of forming a bit line by introducing an impurity, and after forming an insulating film on the bit line so as to fill the opening, memory in the second insulating film, the first insulating film, and the oxide film on the conductive film Part formed on region and peripheral transistor region And step (e5) removing, after the step (e5), forming a third conductive film on the memory region and the peripheral transistor region (e6) and may be configured to include a.

  In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a memory transistor constituting a metal / oxide film / nitride film / oxide film / silicon (MONOS) type memory circuit is formed in the memory region, and a logic transistor is formed in the peripheral transistor region. A transistor included in the circuit may be formed.

  In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, the first gate insulating film may be composed of a silicon oxide film, a silicon nitride film having a charge holding function, and a silicon oxide film sequentially stacked from the lower side. Good.

  According to the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, it is possible to realize a nonvolatile semiconductor memory device in which deterioration of memory characteristics due to the ISSG oxidation method hardly occurs.

(First embodiment)
A method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1, a memory region 101 and a peripheral transistor region 102 are defined on a semiconductor substrate 100 such as a silicon substrate. Although an example in which the boundary between the memory region 101 and the peripheral transistor region 102 is on the semiconductor substrate 100 is shown, the boundary may be on an element isolation film (not shown). Next, a first gate insulating film 106 is formed on the semiconductor substrate 100. The first gate insulating film 106 includes a lower oxide film (SiO ₂ film) 103 having a thickness of 4.0 nm, a nitride film (SiN film) 104 having a charge holding function of 15 nm, and a thickness of about An ONO film in which a 12 nm upper oxide film 105 is sequentially stacked may be used. The lower oxide film 103 may be formed using an ISSG oxidation method under the conditions of a temperature of 850 ° C. and a hydrogen concentration of 5%, for example. The upper oxide film 105 may be formed, for example, using an external combustion type pyrogenic oxidation method at a temperature of 1050 ° C. The nitride film 104 may be formed by, for example, a chemical vapor deposition (CVD) method. Subsequently, after forming a first gate electrode formation film 107 which is a conductive film having a thickness of about 50 nm, a first resist mask 108 having an opening in the peripheral transistor region 102 is formed using a known photolithography technique. .

  Next, as shown in FIG. 2, using the first resist mask 108 as a mask, the first gate electrode formation film 107 and the first gate insulating film 106 are selectively removed by etching. The first resist mask 108 may be removed by a known ashing process or the like.

  Next, as shown in FIG. 3, a second gate insulating film 109 is formed on the exposed portion of the semiconductor substrate 100 as a gate insulating film of a peripheral MOS transistor having a thickness of 3.2 nm. The second gate insulating film 109 may be formed by an ISSG oxidation method. When the second gate insulating film 109 is formed, the surface of the first gate electrode formation film 107 is also oxidized, and the oxide film 110 on the conductive film is formed. Since unreacted hydrogen gas generated when the second gate insulating film 109 is formed is blocked by the first gate electrode formation film 107, the first gate insulating film 106, the first gate insulating film 106, and the semiconductor The interface with the substrate 100 is protected. As a result, it is possible to avoid the deterioration of the rewriting characteristics of the ONO film due to the generation of the interface state. In addition, the thickness of the second gate insulating film 109 formed in the peripheral transistor region 102 can be adjusted. For example, a desired film thickness can be realized by using a laminated film combined with an HTO (High Temperature Oxide) film.

  Next, as shown in FIG. 4, a second gate electrode formation film 111, which is a conductive film having a thickness of about 50 nm, is formed on the second gate insulating film 109 in the peripheral transistor region 102. Thereafter, a second resist mask 112 that opens the bit line diffusion layer in the memory region 101 is formed.

  Next, as shown in FIG. 5, in the memory region 101, the second gate electrode formation film 111, the conductive oxide film 110, the first gate electrode formation film 107, and the second resist mask 112 are used as a mask. The one gate insulating film 106 is selectively removed by etching to expose the semiconductor substrate 100. After the second resist mask 112 is removed using an ashing process or the like, ion implantation is performed on the exposed portion of the semiconductor substrate 100 by a known ion implantation method to form the bit line 113 made of a diffusion layer.

  Next, as shown in FIG. 6, for example, an HDP (High Density Plasma) oxide film 114 serving as an insulating film on the bit line that fills the opening on the bit line is formed on the entire surface of the semiconductor substrate 100 using a known technique. .

  Next, as shown in FIG. 7, the HDP insulating film 114 is polished and removed by, for example, a known CMP (Chemical Mechanical Polishing) method until the second gate electrode formation film 111 formed in the memory region 101 is exposed. Subsequently, the upper portion of the HDP oxide film 114 is removed from the upper surface of the HDP oxide film 114 on the bit line 113 by a known wet etching technique so that the oxide film 110 on the conductive film is not exposed, and the height is adjusted.

  Next, as shown in FIG. 8, the second gate electrode formation film 111 formed in the memory region 101 is removed by a known wet etching technique until the oxide film 110 on the conductive film is exposed. The second gate electrode formation film 111 in the peripheral transistor region 102 is protected by the remaining HDP oxide film 114. Therefore, the second gate electrode formation film 111 in the memory region 101 may be removed using the HDP oxide film 114 as a mask and using a dry etching technique.

  Next, as shown in FIG. 9, the oxide film 110 on the conductive film is removed using the wet etching technique until the first gate electrode formation film 107 is exposed in the memory region 101. In the peripheral transistor region 102, the HDP oxide film 114 is removed until the second gate electrode formation film 111 is exposed.

  Next, as shown in FIG. 10, the third gate electrode formation film 115 which is a conductive film covers the first gate electrode formation film 107 in the memory region 101, and the second gate electrode in the peripheral transistor region 102. It is formed so as to cover the formation film 111. Thereafter, a gate forming process, a metal wiring forming process, a protective film forming process, and a bonding pad forming process are performed using a known technique. Details of these steps are omitted.

  According to the present embodiment, the first gate insulating film 106 that is an ONO film formed in the memory region 101 when the second gate insulating film 109 serving as the gate insulating film in the peripheral transistor region is formed is the first gate insulating film 106. It is protected by the gate electrode formation film 107. Therefore, even if the ISSG oxidation method is applied when forming the second gate insulating film 109, the unreacted hydrogen gas in the ISSG oxidation hardly affects the ONO film. Therefore, the influence of hydrogen in ISSG oxidation can be avoided, and the stability of memory characteristics, particularly rewrite characteristics, can be improved. As a result, a nonvolatile semiconductor memory device with excellent gate insulating film reliability can be realized.

(Second Embodiment)
A method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described below with reference to FIGS.

  First, as shown in FIG. 11, a memory region 201 and a peripheral transistor region 202 are defined in a semiconductor substrate 200 such as a silicon substrate. Although an example in which the boundary between the memory region 201 and the peripheral transistor region 202 is on the semiconductor substrate 200 is shown, the boundary may be on an element isolation film (not shown). Next, a first gate insulating film 206 is formed over the semiconductor substrate 200. The first gate insulating film 206 includes a lower oxide film 203 having a thickness of 4.0 nm, a nitride film 204 having a charge holding function having a thickness of 15 nm, and an upper oxide film 205 having a thickness of about 12 nm. A stacked ONO film may be used. The lower oxide film 203 may be formed by using the ISSG oxidation method, for example, under conditions where the temperature is 850 ° C. and the hydrogen concentration is 5%. The upper oxide film 205 may be formed, for example, using an external combustion type pyrogenic oxidation method at a temperature of 1050 ° C. The nitride film 204 may be formed by a chemical vapor deposition (CVD) method, for example. Subsequently, after forming a first gate electrode formation film 207 which is a conductive film having a thickness of about 50 nm, a first resist mask 208 having an opening in the peripheral transistor region 202 is formed using a known photolithography technique. .

  Next, as shown in FIG. 12, using the first resist mask 208 as a mask, the first gate electrode formation film 207 and the first gate insulating film 206 are selectively etched and removed. The first resist mask 208 may be removed by a known ashing process or the like.

  Next, as shown in FIG. 13, a second gate insulating film 209 that forms the gate insulating film of the peripheral MOS transistor having a thickness of 3.2 nm is formed on the exposed portion of the semiconductor substrate 200. The second gate insulating film 209 may be formed by an ISSG oxidation method. When the second gate insulating film 209 is formed, the surface of the first gate electrode formation film 207 is also oxidized to form an oxide film 210 on the conductive film. Since unreacted hydrogen gas generated when the second gate insulating film 209 is formed is blocked by the first gate electrode formation film 207, the first gate insulating film 206, the first gate insulating film 206, and the semiconductor The interface with the substrate 200 is protected. As a result, it is possible to avoid the deterioration of the rewriting characteristics of the ONO film due to the generation of the interface state. In addition, the thickness of the second gate insulating film 209 formed in the peripheral transistor region 202 can be adjusted. For example, a desired film thickness can be realized by using a laminated film combined with an HTO (High Temperature Oxide) film.

  Next, as shown in FIG. 14, a second gate electrode formation film 211 which is a conductive film having a thickness of about 50 nm is formed on the second gate insulating film 209 in the peripheral transistor region 202. Thereafter, a second resist mask 212 having an opening in the entire memory region 201 is formed.

  Next, after the second gate electrode formation film 211 is selectively removed by etching using the second resist mask 212 as a mask until the oxide film 210 on the conductive film in the memory region 201 is exposed, as shown in FIG. Then, the second resist mask 212 is removed by ashing or the like. By selectively removing the second gate electrode formation film 211 in the memory region 201, the level difference between the memory region 201 and the peripheral transistor region 202 is alleviated. A nonvolatile semiconductor memory device with excellent process margin such as focus control can be manufactured.

  Next, as shown in FIG. 16, for example, an HTO film 213 having a film thickness of 10 nm is formed on the conductive film oxide film 210 exposed in the memory region 201 and the second gate electrode formation film 211 in the peripheral transistor region 202. Then, for example, a 20 nm-thick nitride film 214 serving as a polishing stop layer in the subsequent CMP and a second resist mask 215 opening the bit line diffusion layer in the memory region 201 are formed.

  Next, as shown in FIG. 17, in the memory region 201, using the second resist mask 215 as a mask, the nitride film 214, the HTO film 213, the conductive oxide film 210, the first gate electrode formation film 207, and the first film The gate insulating film 206 is selectively removed by etching. Subsequently, the second resist mask 215 is removed using an ashing process or the like, and a bit line 216 made of a diffusion layer is formed on the exposed surface region of the semiconductor substrate 200 using a known ion implantation method.

  Next, as shown in FIG. 18, an HDP oxide film 217 is formed on the entire surface of the semiconductor substrate 200 by using, for example, a known technique. As a result, the opening on the bit line 216 is filled.

  Next, as shown in FIG. 19, the HDP oxide film 217 is polished and removed by, for example, a known CMP method until the nitride film 214 formed on the memory region 201 and the peripheral transistor region 202 is exposed. The remaining nitride film 214 is removed by an etching technique.

  Next, as shown in FIG. 20, the HTO film 213 and the conductive film upper oxide film 210 are removed by wet etching until the first gate electrode formation film 207 is exposed in the memory region 201. The HTO film 213 is removed until the second gate electrode formation film 211 is exposed in the peripheral transistor region 202.

  Next, as shown in FIG. 21, the third gate electrode formation film 218 that is a conductive film covers the first gate electrode formation film 207 in the memory region 201, and the second gate electrode in the peripheral transistor region 202. It is formed so as to cover the formation film 211. Thereafter, a gate forming process, a metal wiring forming process, a protective film forming process, and a bonding pad forming process are performed using a known technique. Details of these steps are omitted.

  According to the present embodiment, when the second gate insulating film 209 is formed in the peripheral transistor region, the first gate insulating film 206 in the memory region 201 is protected by the first gate electrode formation film 207. For this reason, even if the ISSG oxidation method is applied when forming the second gate insulating film 209, the unreacted hydrogen gas in the ISSG oxidation hardly affects the ONO film. Therefore, the influence of hydrogen in ISSG oxidation can be avoided, and the stability of memory characteristics, particularly rewrite characteristics, can be improved. As a result, a nonvolatile semiconductor memory device with excellent gate insulating film reliability can be realized.

  Furthermore, according to the present embodiment, the level difference between the memory region 201 and the peripheral transistor region 202 is alleviated during the manufacturing process, so that the process such as the suppression of dishing that occurs in the subsequent CMP and the focus control of the resist mask can be performed. A nonvolatile semiconductor memory device having an excellent margin can be manufactured.

  The method for manufacturing a nonvolatile semiconductor memory device according to the present invention can realize a nonvolatile semiconductor memory device in which deterioration of memory characteristics due to the ISSG oxidation method does not easily occur, and can improve the stability of memory characteristics, particularly rewrite characteristics. In particular, it is useful as a method for manufacturing a nonvolatile semiconductor memory device in which a MONOS type memory and a peripheral circuit coexist.

It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention.

Explanation of symbols

100 Semiconductor substrate 101 Memory region 102 Peripheral transistor region 103 Lower oxide film 104 Nitride film 105 Upper oxide film 106 First gate insulating film 107 First gate electrode formation film 108 First resist mask 109 Second gate insulating film 110 Oxide film on conductive film 111 Second gate electrode formation film 112 Second resist mask 113 Bit line 114 HDP oxide film 115 Third gate electrode formation film 200 Semiconductor substrate 201 Memory region 202 Peripheral transistor region 203 Lower oxide film 204 Nitride Film 205 upper oxide film 206 first gate insulating film 207 first gate electrode forming film 208 first resist mask 209 second gate insulating film 210 conductive film oxide film 211 second gate electrode forming film 212 second Resist mask 213 HTO film 214 Nitride film 21 5 Second resist mask 216 Bit line 217 HDP oxide film 218 Third gate electrode formation film

Claims (5)

(A) sequentially forming a first gate insulating film and a first conductive film including an insulating film having a charge holding function on a semiconductor substrate having a memory region and a peripheral transistor region;
Removing a portion of the first conductive film and the first gate insulating film formed on the peripheral transistor region (b);
After the step (b), a second gate insulating film is formed on the peripheral transistor region by performing ISSG oxidation in a state where the first conductive film remains on the memory region. A step (c) of forming an oxide film on the conductive film on the first conductive film remaining on the memory region;
A step (d) of forming a second conductive film on the semiconductor substrate after the step (c);
After the step (d), in the memory region, the second conductive film, the first conductive film, and the first insulating film are selectively removed to form a memory transistor, and the peripheral transistor region And (e) forming a peripheral transistor by selectively removing the second conductive film and the second gate insulating film. The step (e)
The semiconductor substrate is removed by removing a portion formed on the bit line formation region of the memory region in the second conductive film, the oxide film on the conductive film, the first conductive film, and the first gate insulating film. Forming an exposed opening (e1);
A step (e2) of forming a bit line by introducing an impurity into a portion exposed from the opening of the semiconductor substrate;
A step (e3) of removing a portion of the second conductive film formed on the memory region after forming an insulating film on the bit line so as to fill the opening;
A step (e4) of removing a portion formed on the memory region in the oxide film on the conductive film and a portion remaining on the peripheral transistor region in the insulating film on the bit line after the step (e3); ,
The nonvolatile semiconductor memory device according to claim 1, further comprising a step (e5) of forming a third conductive film on the memory region and the peripheral transistor region after the step (e4). Manufacturing method. The step (e)
Removing a portion of the second conductive film formed on the memory region (e1);
A step (e2) of sequentially forming a first insulating film and a second insulating film on the semiconductor substrate after the step (e1);
After the step (e2), the bit line formation region of the memory region in the second insulating film, the first insulating film, the conductive film oxide film, the first conductive film, and the first gate insulating film is formed. Forming an opening exposing the semiconductor substrate by removing a portion formed thereon (e3);
A step (e4) of forming a bit line by introducing an impurity into a portion exposed from the opening of the semiconductor substrate;
After forming an insulating film on the bit line so as to fill the opening, a portion formed on the memory region and the peripheral transistor region in the second insulating film, the first insulating film, and the conductive oxide on the conductive film is formed. Removing (e5);
The nonvolatile semiconductor memory device according to claim 1, further comprising a step (e6) of forming a third conductive film on the memory region and the peripheral transistor region after the step (e5). Manufacturing method.   A memory transistor constituting a metal / oxide film / nitride film / oxide film / silicon (MONOS) type memory circuit is formed in the memory region, and a transistor constituting a logic circuit is formed in the peripheral transistor region. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1.   5. The device according to claim 1, wherein the first gate insulating film includes a silicon oxide film, a silicon nitride film having a charge holding function, and a silicon oxide film that are sequentially stacked from the lower side. The manufacturing method of the non-volatile semiconductor memory device of description.

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